CN111799188A - Thinning wafer packaging process utilizing TSV and TGV - Google Patents
Thinning wafer packaging process utilizing TSV and TGV Download PDFInfo
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- CN111799188A CN111799188A CN202010694662.9A CN202010694662A CN111799188A CN 111799188 A CN111799188 A CN 111799188A CN 202010694662 A CN202010694662 A CN 202010694662A CN 111799188 A CN111799188 A CN 111799188A
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- 238000012858 packaging process Methods 0.000 title claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 45
- 238000004891 communication Methods 0.000 claims abstract description 38
- 239000011521 glass Substances 0.000 claims abstract description 34
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000009713 electroplating Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000010354 integration Effects 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000003475 lamination Methods 0.000 claims abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 4
- 238000005516 engineering process Methods 0.000 claims description 26
- 239000000126 substance Substances 0.000 claims description 19
- 238000007747 plating Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
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- 208000014903 transposition of the great arteries Diseases 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a thinning wafer packaging process by using TSV and TGV, which comprises the following steps: s1, bonding the wafer with the glass carrier plate, and manufacturing TSV communication holes on the back side; s2, electroplating the TSV interconnecting hole to form a Ni/Pd/Cu seed layer; s3 filling Cu into the TSV communication hole; s4, forming a wafer copper pillar bump; s5, electroplating a Ni/Pd/Au metal lamination; s6, manufacturing a TGV communication hole on the back of the glass carrier plate; s7, electroplating a TGV communication hole to form a Ni/Pd/Cu seed layer, and S8, filling Cu into the TGV communication hole and forming a copper pillar bump; s9, forming an RDL on the back of the glass carrier plate; s10, removing the redundant Ni/Pd/Cu seed layer by etching; s11, electroplating a Ni/Pd/Au metal lamination on the surface of the copper pillar bump of the glass carrier; and S12, respectively welding the connecting lines of the through holes of the TSV and the TGV with Clip or Board to complete the 3D framework. The invention does not need TSV/TGV flat hole filling electroplating of a Cu CMP process, double-sided wiring connection of TSV and TGV communication hole connecting lines is respectively completed on the front side and the back side, Clip or Board can be welded up and down, and the 3D framework with high integration degree and low delay conduction is completed.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to a thinning wafer packaging process by using TSV and TGV.
Background
With the rise of communication electronics, people have increasingly high demands on miniaturization and high-sensitivity modules or systems, and the requirements on signal quality are also increasingly strict. High-density integration technologies, such as System-in-Package (SiP) technologies, have been rapidly developed, but the miniaturized integrated Package of the mixed-signal multi-chip System has become one of the technical difficulties in this field. In addition to technologies such as three-dimensional chip stacking (Stacked chip), Package On Package (POP), and the like, the application of some new materials and new technologies brings opportunities for Package miniaturization, and for example, a flexible substrate, a Through Silicon Via (TSV) interposer technology and a Through Glass Via (TGV) interposer technology become one of hot research directions for vertical 3D interconnection.
Through Silicon Via (TSV) technology is a high-density packaging technology, and is gradually replacing the mature wire bonding technology in the current technology, and is considered as a fourth generation packaging technology. The TSV technology realizes vertical electrical interconnection of the through-silicon vias by filling conductive substances such as copper, tungsten, polysilicon, and the like. The through silicon via technology can reduce the interconnection length, reduce signal delay, reduce capacitance/inductance, realize low power consumption and high-speed communication between chips, increase broadband and realize miniaturization of device integration through vertical interconnection.
The Glass material and the ceramic material have no freely moving charges, the dielectric property is excellent, the thermal expansion coefficient is close to that of silicon, the problem of poor insulating property of TSV can be avoided by using a Glass Through Glass Via (TGV) technology of replacing silicon materials with Glass, and the three-dimensional integration solution is ideal. The Through Glass Via (TGV) technology is considered as a key technology for next generation three-dimensional integration, and the core of the technology is a deep hole forming process. In addition, the TGV technology does not need to manufacture an insulating layer, thereby reducing the process complexity and the processing cost. TGV and related technologies have broad application prospects in the fields of optical communication, radio frequency, microwave, micro-electro-mechanical systems, micro-fluidic devices and three-dimensional integration.
The conventional ECP technology fills the through-holes (TSVs) or TGVs, and after metal-in-silicon vias (TSVs) are filled, the CMP chemical mechanical polishing technology is used to remove the metal layer on the outer surface of the through-holes to achieve planarization of the through-hole filling.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the background art, the present invention provides a process for packaging a thinned wafer using TSV and TGV, wherein chemical plating is used as a contact and barrier layer, a seed layer is provided during subsequent copper electroplating, via holes of TSV or TGV are filled using electrode plating, RDL or bump Post and PAD are formed using a yellow pattern, photoresist is removed before connecting a package wire, and perfect fusion bonding of an external wire is formed using cladding of a chemical plating Ni/Pd/Au metal stack.
The purpose of the invention can be realized by the following technical scheme:
a thinning wafer packaging process utilizing TSV and TGV comprises the following steps:
s1, bonding the front surface of the wafer with a glass carrier plate to finish back surface thinning, and manufacturing TSV communication holes on the back surface of the wafer through a yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV through hole;
s3, filling Cu into the TSV through holes by using electrode electroplating, and polishing the back of the wafer by chemical mechanical planarization CMP to complete the filling of the TSV through holes;
s4, coating photoresist on the back of the wafer, and making a wafer copper Pillar bump Cu Pillar at the corresponding TSV through hole on the back of the wafer through an ECP process;
s5, performing chemical electroplating on the surface of the wafer copper Pillar bump Cu Pillar to form a Ni/Pd/Au metal laminated MetaStack, and completing TSV through hole communication;
s6, manufacturing TGV communication holes on the back of the glass carrier plate by a yellow light process or a Laser perforation combined etching technology;
s7, forming a Ni/Pd/Cu Seed layer on the surface of the glass carrier and on the side wall and bottom of the TGV via holes by chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and then filling Cu into the TGV communication holes by using electrode electroplating to form a copper column bump Cu Pillar;
s9, forming a RDL circuit pattern on the back of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni/Pd/Cu Seed layer outside the Cu Pillar covering area of the copper Pillar bump on the back of the glass carrier;
s11, performing electrodeless chemical plating on the surface of the copper Pillar bump Cu Pillar of the glass carrier plate to form Ni/Pd/Au metal lamination covering, and completing TGV through hole communication;
and S12, after the TSV and TGV communication hole connecting lines are manufactured, respectively welding the TSV and TGV communication hole connecting lines with clips or boards, and finishing the 3D framework with high integration degree and low time delay conduction.
Preferably, in step S1, the TSV via is connected to a metal layer of copper or aluminum on the front side of the wafer, the metal layer has completed Sidewall insulation, and electroless plating may be performed.
Preferably, the TGV communication hole is connected to the wafer front PAD in step S6.
Preferably, the thickness of the Seed layer of the Ni/Pd/Cu Seed layer is less than 1 um.
The invention has the beneficial effects that:
1. the invention does not need TSV/TGV flat hole filling electroplating in a Cu CMP (chemical mechanical polishing) process, overcomes the problem that the thickness of the substrate is limited by CMP, and the problem of fragment or mechanical damage caused by uneven stress if the substrate is too thin.
2. The front side and the back side of the invention respectively complete the connection of the TSV and the TGV communication holes, and a Clip or a Board can be welded up and down to complete the 3D framework with high integration degree and low delay conduction, so that the upper element and the lower element (the front side and the back side) can be communicated, the integration degree can be increased, and the speed delay caused by the wire communication can be reduced.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a TSV and TGV combined package structure of the present invention;
FIG. 2 is an enlarged schematic view of the present invention at position A of FIG. 1;
FIG. 3 is an enlarged schematic view of the present invention at position B of FIG. 1;
FIG. 4 is a schematic view of the forming structure of step S1 according to the present invention;
FIG. 5 is a schematic view of the forming structure of step S2 according to the present invention;
FIG. 6 is a schematic view of the forming structure of step S3 according to the present invention;
FIG. 7 is a schematic view of the forming structure of step S4 according to the present invention;
FIG. 8 is a schematic view of the forming structure of step S5 according to the present invention;
FIG. 9 is a schematic view of the forming structure of step S6 according to the present invention;
FIG. 10 is a schematic view of the forming structure of step S7 according to the present invention;
FIG. 11 is a schematic view of the forming structure of step S8 according to the present invention;
FIG. 12 is a schematic view of the forming structure of step S10 according to the present invention;
fig. 13 is a schematic view of the forming structure of step S11 of the present invention.
In the figure:
1-thinning a wafer, 2-glass carrier plate, 3-adhesive layer, 4-TSV communication holes, 5-Ni/Pd/Cu seed layer Seedlayer, 6-filling Cu, 7-copper column bump Cu Pillar, 8-Ni/Pd/Au metal lamination MetalStack, and 9-TGV communication holes.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
A thinning wafer packaging process utilizing TSV comprises the following steps:
s1, performing RDL wiring on the front side of the wafer through a yellow light process, then bonding the front side of the wafer with a glass carrier plate to finish back side thinning, and manufacturing TSV communication holes on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV through hole;
s3, filling Cu into the TSV through holes by using electrode electroplating, and polishing the back of the wafer by chemical mechanical planarization CMP to complete TSV through hole filling;
s4, coating photoresist on the back of the wafer, and making a wafer copper Pillar bump Cu Pillar at the corresponding TSV through hole on the back of the wafer through an ECP process;
s5, performing chemical electroplating on the surface of the wafer copper Pillar bump Cu Pillar to form a Ni/Pd/Au metal laminated MetaStack, and completing TSV through hole communication;
s6, after the TSV through holes are communicated, packaging key joint or RDL wiring is carried out, and then Solder balls are communicated to other chips or PCBs through the Solder ball Bump;
s7, fixing the thinned wafer on a cutting film frame, debonding by using a Laser/UV/Thermald mode, and then turning over to remove the glass carrier plate;
and S8, removing the adhesive from the thinned wafer by using an organic solvent on the cutting film frame, and then performing cutting and subsequent packaging engineering.
Example 2
A thinning wafer packaging process utilizing TSV and TGV comprises the following steps:
s1, performing RDL wiring on the front side of the wafer through a yellow light process, then bonding the front side of the wafer with a glass carrier plate to finish back side thinning, and manufacturing TSV communication holes on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV through hole;
s3, filling Cu into the TSV through holes by using electrode electroplating, and polishing the back of the wafer by chemical mechanical planarization CMP to complete TSV through hole filling;
s4, coating photoresist on the back of the wafer, and making a wafer copper Pillar bump Cu Pillar at the corresponding TSV through hole on the back of the wafer through an ECP process;
s5, performing chemical electroplating on the surface of the wafer copper Pillar bump Cu Pillar to form a Ni/Pd/Au metal laminated MetaStack, and completing TSV through hole communication;
s6, manufacturing TGV communication holes on the back of the glass carrier plate by a yellow light process or a Laser perforation combined etching technology;
s7, forming a Ni/Pd/Cu Seed layer on the surface of the glass carrier and on the side wall and bottom of the TGV via holes by chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and then filling Cu into the TGV communication holes by using electrode electroplating to form a copper column bump Cu Pillar;
s9, forming a RDL circuit pattern on the back of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni/Pd/Cu Seed layer outside the Cu Pillar covering area of the copper Pillar bump on the back of the glass carrier;
s11, performing electrodeless chemical plating on the surface of the copper Pillar bump Cu Pillar of the glass carrier plate to form Ni/Pd/Au metal lamination covering, and completing TGV through hole communication;
and S12, after the TSV and TGV communication hole connecting lines are manufactured, respectively welding the TSV and TGV communication hole connecting lines with clips or boards, and finishing the 3D framework with high integration degree and low time delay conduction.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (4)
1. A thinning wafer packaging process utilizing TSV and TGV is characterized by comprising the following steps:
s1, performing RDL wiring on the front side of the wafer through a yellow light process, then bonding the front side of the wafer with a glass carrier plate to finish back side thinning, and manufacturing TSV communication holes on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV through hole;
s3, filling Cu into the TSV through holes by using electrode electroplating, and polishing the back of the wafer by chemical mechanical planarization CMP to complete TSV through hole filling;
s4, coating photoresist on the back of the wafer, and making a wafer copper Pillar bump Cu Pillar at the corresponding TSV through hole on the back of the wafer through an ECP process;
s5, performing chemical electroplating on the surface of the wafer copper Pillar bump Cu Pillar to form a Ni/Pd/Au metal laminated MetaStack, and completing TSV through hole communication;
s6, manufacturing TGV communication holes on the back of the glass carrier plate by a yellow light process or a Laser perforation combined etching technology;
s7, forming a Ni/Pd/Cu Seed layer on the surface of the glass carrier and on the side wall and bottom of the TGV via holes by chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and then filling Cu into the TGV communication holes by using electrode electroplating to form a copper column bump CuPillar;
s9, forming a RDL circuit pattern on the back of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni/Pd/Cu Seed layer outside the Cu Pillar covering area of the copper Pillar bump on the back of the glass carrier;
s11, performing electrodeless chemical plating on the surface of the copper Pillar bump Cu Pillar of the glass carrier plate to form Ni/Pd/Au metal lamination covering, and completing TGV through hole communication;
and S12, after the TSV and TGV communication hole connecting lines are manufactured, respectively welding the TSV and TGV communication hole connecting lines with clips or boards, and finishing the 3D framework with high integration degree and low time delay conduction.
2. The process of claim 1, wherein the TSV via in step S1 is connected to a metal layer of copper or aluminum on the front side of the wafer, wherein the metal layer has a sidewall insulation SidewallPassionation completed and is capable of being chemically plated.
3. The process of claim 1, wherein the TGV communication hole is connected to the PAD on the front side of the wafer in step S6.
4. The process of claim 1, wherein the Ni/Pd/Cu Seed layer thickness is less than 1 um.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010694662.9A CN111799188B (en) | 2020-07-17 | 2020-07-17 | Thinning wafer packaging technology utilizing TSV and TGV |
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| CN202010694662.9A CN111799188B (en) | 2020-07-17 | 2020-07-17 | Thinning wafer packaging technology utilizing TSV and TGV |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687618A (en) * | 2020-12-23 | 2021-04-20 | 绍兴同芯成集成电路有限公司 | Wafer packaging method and wafer packaging assembly |
| CN116454020A (en) * | 2023-03-22 | 2023-07-18 | 苏州森丸电子技术有限公司 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
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| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
| CN104867892A (en) * | 2014-02-20 | 2015-08-26 | 阿尔特拉公司 | Silicon-glass hybrid interposer circuitry |
| US20160079149A1 (en) * | 2013-05-31 | 2016-03-17 | Toppan Printing Co., Ltd. | Wiring board provided with through electrode, method for manufacturing same and semiconductor device |
-
2020
- 2020-07-17 CN CN202010694662.9A patent/CN111799188B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| US20160079149A1 (en) * | 2013-05-31 | 2016-03-17 | Toppan Printing Co., Ltd. | Wiring board provided with through electrode, method for manufacturing same and semiconductor device |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112687618A (en) * | 2020-12-23 | 2021-04-20 | 绍兴同芯成集成电路有限公司 | Wafer packaging method and wafer packaging assembly |
| CN116454020A (en) * | 2023-03-22 | 2023-07-18 | 苏州森丸电子技术有限公司 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
| CN116454020B (en) * | 2023-03-22 | 2024-02-09 | 苏州森丸电子技术有限公司 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
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| CN111799188B (en) | 2023-12-12 |
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