CN116454020B - Buried high-flatness TGV interconnection process and TGV interconnection structure - Google Patents
Buried high-flatness TGV interconnection process and TGV interconnection structure Download PDFInfo
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- CN116454020B CN116454020B CN202310285170.8A CN202310285170A CN116454020B CN 116454020 B CN116454020 B CN 116454020B CN 202310285170 A CN202310285170 A CN 202310285170A CN 116454020 B CN116454020 B CN 116454020B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000011521 glass Substances 0.000 claims abstract description 65
- 238000004891 communication Methods 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000004544 sputter deposition Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000012986 modification Methods 0.000 claims abstract description 8
- 230000004048 modification Effects 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000003486 chemical etching Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 229910004353 Ti-Cu Inorganic materials 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims 1
- 238000005429 filling process Methods 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a buried high-flatness TGV interconnection process and a TGV interconnection structure, which solve the problems of poor uniformity of the surface and the back of a glass wafer and poor interconnection reliability in a GV filling process by modifying and flattening the surface and the back of the glass wafer, improve the uniformity, embed RDL into the glass wafer, reduce the whole thickness of a device by 10 mu m, manufacture TGV communication holes and RDL rewiring layers by laser-induced modification and wet etching, and deposit conductive materials on the seed layers to form TGV and RDL by sputtering the seed layers, thereby reducing the need of twice masking, developing and etching in the traditional process, effectively simplifying the process flow and improving the working efficiency.
Description
Technical Field
The invention relates to a buried high-flatness TGV interconnection process and a TGV interconnection structure, and belongs to the technical field of semiconductor electroplating processing.
Background
In recent years, with the rising emerging fields of 5G, wearable equipment, smart phones, automotive electronics, artificial intelligence and the like, the application of integrated circuits is developed towards diversified application, and advanced three-dimensional packaging technology is also becoming an important means for realizing miniaturization, light weight and multifunction of electronic products. The application of new materials and technologies has led to the advent of package miniaturization, such as flexible substrates, through silicon via (Through Silicon Via, TSV) interposer technology, and glass via (Through Glass Via, TGV) interposer technology, as one of the hot research directions for vertical 3D interconnects.
The glass material and the ceramic material have no free moving charges, have excellent dielectric property, have a thermal expansion coefficient close to that of silicon, and the glass through hole (Through Glass Via, TGV) technology of replacing the silicon material with glass can avoid the problem of poor TSV insulation, so that the method is an ideal three-dimensional integration solution. The Glass Via (TGV) technology is considered as a key technology for the next generation of three-dimensional integration, and the core of the technology is a deep hole forming process.
The following problems exist in the current TGV filling process: the TGV device manufactured by the traditional process has poor uniformity of the surface and the back, complex production process and poor interconnection reliability.
Disclosure of Invention
The invention aims to provide a buried high-flatness TGV interconnection process which is simple, solves the problem of surface uniformity of a TGV device and improves interconnection reliability.
In order to achieve the above purpose, the present invention provides the following technical solutions: a buried high-planarity TGV interconnect process comprising the steps of:
s1, perforation manufacturing: cleaning a glass wafer, and performing laser-induced punching on the glass wafer to form a plurality of through holes;
s2, manufacturing a wiring layer, namely performing laser modification on the plane of the glass wafer to form the wiring layer used for communicating a plurality of through holes;
s3, wet etching: etching the through holes and the wiring layer by chemical etching to form TGV communication holes and RDL rerouting layers;
s4, sputtering a seed layer: sputtering a seed layer in the TGV communication hole and the RDL rerouting layer;
s5, conducting interconnection layers: electrochemically depositing a conductive material on the seed layer to a plane of the glass wafer to form TGV and RDL;
s6, flattening by CMP: and flattening the conductive material deposited on the seed layer.
Further, in step S2, the step of performing laser modification on the plane of the glass wafer to form a wiring layer for connecting the plurality of through holes includes:
modifying the surface of the glass wafer by laser to form a surface wiring layer;
the back surface of the glass wafer is modified by laser light to form a back surface wiring layer.
Further, in step S3, the chemical etching solution is hydrofluoric acid with a volume concentration of 5% -20%, and the ultrasonic device and the vibration and swing device are used in combination while etching.
Further, in step S4, the step of performing seed layer sputtering on the via hole and the rewiring layer includes: and (3) performing seed layer sputtering on the TGV communication holes, the RDL rerouting layer on the surface and the RDL rerouting layer on the back, wherein the sputtered seed layer is Ti-Cu or Tiw/Cu.
Further, in step S4, sputtering of seed layers of the TGV communication holes, the RDL rewiring layer on the front surface, and the RDL rewiring layer on the back surface is achieved by PVD sputtering.
Further, in step S4, the method further comprises immersing the glass wafer sputtered with the seed layer in a dilute sulfuric acid solution for activation.
Further, in step S5, the conductive material is a conductive metal.
Further, in step S6, the step of planarizing the conductive material deposited on the seed layer includes: and carrying out chemical mechanical planarization treatment on the conductive material on the surface and the back surface of the glass wafer until the surface of the conductive material is coplanar with the surface or the back surface of the glass wafer.
A TGV interconnection structure comprises a glass wafer, a communication hole penetrating through the glass wafer and an RDL rerouting layer which is recessed inwards from the surface of the glass wafer and is communicated with the TGV communication hole, wherein the TGV communication hole and the RDL rerouting layer are filled with TGV and RDL, and the surfaces of the TGV and the RDL are coplanar with the surface of the glass wafer.
Further, the TGV includes a seed layer sputtered within the TGV communication holes and a conductive material electrochemically deposited on the seed layer, the RDL includes a seed layer sputtered within the RDL redistribution layer and a conductive material electrochemically deposited on the seed layer, the TGV is in communication with the RDL.
The invention has the beneficial effects that: according to the invention, the surface and the back of the glass wafer are modified and flattened, so that the problems of poor uniformity and poor interconnection reliability of the surface and the back of the glass wafer in the GV filling process are solved, the uniformity is improved, RDL is embedded into the glass wafer, the overall thickness of the device is reduced by 10 mu m, meanwhile, TGV communication holes and RDL rewiring layers are manufactured by laser-induced modification and wet etching, and TGV and RDL are formed by sputtering a seed layer and depositing conductive materials on the seed layer, so that the need of performing mask, development and etching twice in the traditional process is reduced, the process flow is effectively simplified, and the working efficiency is improved.
The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
Fig. 1 is a flow chart of a buried high-planarity TGV interconnect process of the present invention.
Fig. 2 is a schematic diagram of the structure after the planarization process of the TGV interconnect structure of the present invention.
Fig. 3 is a perspective view of a TGV interconnect structure of the present invention.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
Referring to fig. 1 to 3, the present invention provides a buried high-planarization TGV interconnection process, which includes the following steps:
s1, perforation manufacturing: cleaning the glass wafer 1, and performing laser-induced punching on the glass wafer 1 to form a plurality of through holes;
s2, manufacturing a wiring layer, namely performing laser modification on the plane of the glass wafer 1 to form the wiring layer used for communicating a plurality of through holes;
s3, wet etching: etching the via holes and the wiring layer by chemical etching to form TGV communication holes 2 and RDL re-wiring layer 3;
s4, sputtering a seed layer: sputtering a seed layer in the TGV communication hole 2 and the RDL rerouting layer 3;
s5, conducting interconnection layers: electrochemically depositing a conductive material on the seed layer to the plane of the glass wafer 1 to form TGV and RDL;
s6, flattening by CMP: and flattening the conductive material deposited on the seed layer.
In this embodiment, a suitable glass wafer 1 is selected according to the need, and is cleaned by acetone, alcohol and deionized water under ultrasonic waves of a certain intensity for 8 minutes, and cleaned for 24 minutes, and the cleaned glass wafer 1 is dried by a dryer.
In this embodiment, in step S2, the step of performing laser modification on the plane of the glass wafer 1 to form the wiring layer for connecting the plurality of through holes includes: modifying the surface of the glass wafer 1 by laser to form a surface wiring layer; the back surface of the glass wafer 1 is modified by laser light to form a back surface wiring layer. Specifically, laser-induced drilling is performed on the glass wafer 1 according to the designed scheme, through holes penetrating through the front surface and the back surface are formed in the glass wafer 1, and the surface of the glass wafer 1 are modified by laser according to the designed scheme to manufacture the wiring layer for accommodating the RDL.
In this embodiment, in step S3, the chemical etching solution is hydrofluoric acid with a volume concentration of 5% -20%, and the ultrasonic device and the vibration and swing device are used in combination while etching. Specifically, the glass wafer 1 with the punched holes and the wiring layer manufactured is cleaned by a surfactant, ethanol and the like under ultrasonic conditions, and is dried again after cleaning, then the punched holes and the wiring layer are corroded by hydrofluoric acid with the volume concentration of 5% -20%, so that the diameters of the punched holes are enlarged to be about 20 μm to form TGV communication holes 2, the depth of the wiring layer is enlarged to be about 5 μm to form RDL rewiring layers 3, and corrosion can be assisted by a certain ultrasonic field and vibration swing to ensure that the corrosion is more uniform and explosion and other conditions are avoided while corrosion is performed.
In this embodiment, in step S4, the step of performing seed layer sputtering on the via hole and the rewiring layer includes: seed layer sputtering is carried out on the TGV communication holes 2, the RDL re-wiring layer 3 on the surface and the RDL re-wiring layer 3 on the back, and the sputtered seed layer is Ti-Cu or Tiw/Cu. Specifically, the seed layers of the TGV via hole 2, the RDL rewiring layer 3 on the front surface, and the RDL rewiring layer 3 on the back surface are sputtered by PVD sputtering.
In this embodiment, in step S4, the glass wafer 1 sputtered with the seed layer is further immersed in a dilute sulfuric acid solution for activation. Specifically, certain ultrasonic waves can be assisted during activation, but the size of the ultrasonic waves cannot be too large, so that the seed layer is prevented from falling off.
In this embodiment, in order to adapt the TGV device to different application environments, in step S5, the conductive material is a conductive metal, and the conductive metal is a conventional existing conductive metal, which is not specifically limited herein.
In this embodiment, in step S6, the step of planarizing the conductive material deposited on the seed layer includes: the conductive material on the surface and the back surface of the glass wafer 1 is subjected to chemical mechanical planarization treatment, respectively, until the surface of the conductive material is coplanar with the surface or the back surface of the glass wafer 1. Specifically, CMP is used to polish and planarize the surface or back surface of the glass wafer 1 until RDL is coplanar with the surface or back surface of the glass wafer 1.
The invention also provides a TGV interconnection structure manufactured by the process, which comprises a glass wafer 1, a communication hole penetrating through the glass wafer 1 and an RDL rerouting layer 3 which is inwards sunken from the surface of the glass wafer 1 and is communicated with the TGV communication hole 2, the TGV communication hole 2 and the rerouting layer are filled with TGV and RDL, the surfaces of the TGV and the RDL are coplanar with the surface of the glass wafer 1, the TGV comprises a seed layer sputtered in the TGV communication hole and a conductive material electrochemically deposited on the seed layer, the RDL comprises a seed layer sputtered in the RDL rerouting layer and a conductive material electrochemically deposited on the seed layer, and the TGV is communicated with the RDL. Specifically, the TGV and RDL on the surface of the glass wafer 1 are completely embedded into the glass wafer 1, the overall thickness of the TGV device is reduced by 10 mu m, and the arrangement space of the TGV device is saved.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. A buried high planarity TGV interconnect process comprising the steps of:
s1, perforation manufacturing: cleaning a glass wafer, and performing laser-induced punching on the glass wafer to form a plurality of through holes;
s2, manufacturing a wiring layer, namely performing laser modification on the plane of the glass wafer to form the wiring layer used for communicating a plurality of through holes;
s3, wet etching: etching the through holes and the wiring layer by chemical etching to form TGV communication holes and RDL rerouting layers;
s4, sputtering a seed layer: sputtering a seed layer in the TGV communication hole and the RDL rerouting layer;
s5, conducting interconnection layers: electrochemically depositing a conductive material on the seed layer to a plane of the glass wafer to form TGV and RDL;
s6, flattening by CMP: and carrying out planarization treatment on the conductive material deposited on the seed layer, wherein the TGV interconnection structure comprises a glass wafer, communication holes penetrating through the glass wafer and an RDL rerouting layer which is recessed inwards from the surface of the glass wafer and is communicated with the TGV communication holes, the TGV communication holes and the RDL rerouting layer are filled with TGV and RDL, and the surfaces of the TGV and the RDL are coplanar with the surface of the glass wafer.
2. The embedded high-planarity TGV interconnect process of claim 1, wherein in step S2, the step of laser modifying the plane of the glass wafer to form a wiring layer for connecting a plurality of the vias comprises:
modifying the surface of the glass wafer by laser to form a surface wiring layer;
the back surface of the glass wafer is modified by laser light to form a back surface wiring layer.
3. The process of claim 1, wherein in step S3, the chemical etching solution is hydrofluoric acid with a volume concentration of 5% -20%, and the ultrasonic device and the vibration and swing device are used in combination while etching.
4. The embedded high-planarity TGV interconnect process of claim 1, wherein in step S4, the step of seed layer sputtering the via and re-routing layer comprises: and (3) performing seed layer sputtering on the TGV communication holes, the RDL rerouting layer on the surface and the RDL rerouting layer on the back, wherein the sputtered seed layer is Ti-Cu or Tiw/Cu.
5. The buried highly planar TGV interconnect process of claim 4, wherein in step S4, sputtering of seed layers of the TGV via, the RDL re-wiring layer on the surface, and the RDL re-wiring layer on the back is achieved by PVD sputtering.
6. The buried highly planar TGV interconnect process of claim 5, further comprising, in step S4, activating by immersing the glass wafer sputtered with a seed layer in a dilute sulfuric acid solution.
7. The buried highly planar TGV interconnect process of claim 1, wherein in step S5, the conductive material is a conductive metal.
8. The buried highly planarized TGV interconnect process of claim 1, wherein planarizing the conductive material deposited on the seed layer in step S6 comprises: and carrying out chemical mechanical planarization treatment on the conductive material on the surface and the back surface of the glass wafer until the surface of the conductive material is coplanar with the surface or the back surface of the glass wafer.
9. The buried highly planar TGV interconnect process of claim 1, wherein the TGV comprises a seed layer sputtered within the TGV via and a conductive material electrochemically deposited on the seed layer, the RDL comprises a seed layer sputtered within the RDL redistribution layer and a conductive material electrochemically deposited on the seed layer, the TGV in communication with the RDL.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310285170.8A CN116454020B (en) | 2023-03-22 | 2023-03-22 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
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| CN202310285170.8A CN116454020B (en) | 2023-03-22 | 2023-03-22 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005098861A (en) * | 2003-09-25 | 2005-04-14 | Kyocera Corp | Micro space wiring board and manufacturing method thereof |
| CN102723306A (en) * | 2012-06-28 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof |
| CN105405838A (en) * | 2015-09-01 | 2016-03-16 | 苏州含光微纳科技有限公司 | Novel TSV switch board and manufacturing method |
| CN106409758A (en) * | 2016-10-09 | 2017-02-15 | 华进半导体封装先导技术研发中心有限公司 | Through glass via metallic fabrication method |
| CN106795044A (en) * | 2014-10-03 | 2017-05-31 | 日本板硝子株式会社 | Manufacture method and glass substrate with through electrode glass substrate |
| CN111477588A (en) * | 2020-05-29 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | Vertical interconnection wafer level packaging method and structure |
| CN111799188A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Thinning wafer packaging process utilizing TSV and TGV |
| JP2022151790A (en) * | 2021-03-26 | 2022-10-07 | 凸版印刷株式会社 | Method for manufacturing wiring board and wiring board |
| CN115666002A (en) * | 2022-10-21 | 2023-01-31 | 中国电子科技集团公司第十四研究所 | TGV substrate surface processing and wiring method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7517798B2 (en) * | 2005-09-01 | 2009-04-14 | Micron Technology, Inc. | Methods for forming through-wafer interconnects and structures resulting therefrom |
-
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- 2023-03-22 CN CN202310285170.8A patent/CN116454020B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005098861A (en) * | 2003-09-25 | 2005-04-14 | Kyocera Corp | Micro space wiring board and manufacturing method thereof |
| CN102723306A (en) * | 2012-06-28 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof |
| CN106795044A (en) * | 2014-10-03 | 2017-05-31 | 日本板硝子株式会社 | Manufacture method and glass substrate with through electrode glass substrate |
| CN105405838A (en) * | 2015-09-01 | 2016-03-16 | 苏州含光微纳科技有限公司 | Novel TSV switch board and manufacturing method |
| CN106409758A (en) * | 2016-10-09 | 2017-02-15 | 华进半导体封装先导技术研发中心有限公司 | Through glass via metallic fabrication method |
| CN111477588A (en) * | 2020-05-29 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | Vertical interconnection wafer level packaging method and structure |
| CN111799188A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Thinning wafer packaging process utilizing TSV and TGV |
| JP2022151790A (en) * | 2021-03-26 | 2022-10-07 | 凸版印刷株式会社 | Method for manufacturing wiring board and wiring board |
| CN115666002A (en) * | 2022-10-21 | 2023-01-31 | 中国电子科技集团公司第十四研究所 | TGV substrate surface processing and wiring method |
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