JP2011258803A - Silicon substrate with plating layer having through holes - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon substrate having a plurality of fine through holes which has metal film with a superior adhesion property formed in the inside of through holes and on the flat portion of the substrate by a simple technology not dependent on a semiconductor process, making the substrate suitable for high-density packaging uses.SOLUTION: A clean silicon surface is exposed on the flat portion and in the inside of through holes of a silicon substrate by subjecting the substrate to a pre-plating process. Nickel displacement plating and electroless copper plating are applied in that order (S4), and thereby the whole surface of the inside walls of all through holes and the whole surface or part of the principal surface of the silicon substrate are directly covered. This way, a silicon substrate including metal film which exhibits a superior adhesion property and good conductivity is produced.

Description

  The present invention relates to a silicon substrate having a through hole for mounting an electronic component.

In the technical field of electronic component mounting, due to the increase in the number of terminals of a semiconductor LSI chip and the miniaturization of the pitch between terminals, the conventional LSI package technology cannot cope with the fine pitch and the number of terminals.
In order to integrate semiconductor chips with high density, a technique for mounting them on both surfaces of a mounting circuit board or three-dimensionally stacking semiconductor chips at a package level and a chip level has been studied. In particular, as a chip level stacking technique, a three-dimensional LSI stacking technique using a through silicon connection via (TSV / Through Silicon Via) in which a through-hole is formed in a substrate and filled with a conductor is attracting attention.
Further, a new three-dimensional LSI stacking technique that actively uses an interposer that has been used to increase the inter-terminal pitch between the mounting circuit board and the semiconductor chip is being studied. When classifying from the viewpoint of the material used, there are two types of interposer manufacturing technologies: a resin interposer based on a printed circuit board manufacturing technology and a silicon interposer based on a silicon semiconductor device manufacturing technology. The latter is a manufacturing process with excellent fine workability and flatness, and can cope with a finer inter-terminal pitch than the former.
Useful effects by using an interposer are (1) conversion of pitch between terminals, (2) addition of rewiring layer, (2) high-density mounting, (3) support for high frequency and high-speed signals, (4) Improvement of heat dissipation performance, (5) matching of thermal expansion coefficients (improvement of mechanical reliability), (6) embedding of passive components and active components are considered.
The resin interposer only supports (1) to (3), but the silicon interposer can have all the effects (1) to (6).

As described briefly above, the main reason why silicon interposers are attracting attention is the limit of miniaturization in semiconductor chips. Semiconductor chips have been miniaturized for more than 40 years in accordance with Moore's Law (eg, the number of transistors per chip doubles in 2 years). The merit of miniaturization is not only that a large number of transistors can be loaded, but also the speed can be increased by miniaturization of elements and wiring, and a more complicated device can be made. Based on this miniaturization technology, SoC (System on Chip; hereinafter referred to as SoC) in which devices having different functions are integrated in one semiconductor chip is widely used in electronic and electrical devices. Since a plurality of functions are integrated in one chip, it is possible to pack functions at a very high density and to connect different devices at high speed (see, for example, Patent Document 2).
However, as the line width in the semiconductor process has been reduced to less than 30 nm, the physical limit has recently been seen in the miniaturization. Even in a semiconductor chip having a relatively simple configuration such as a memory, it is not a situation where high integration can be achieved by further miniaturization to a line width of about 20 nm or less. Further, miniaturization does not necessarily lead to an increase in speed, and heat generation from LSI has become a level that cannot be ignored. Since such semiconductor processes have also become complicated and expensive, there are cases where SoC in which various LSIs are packed in one chip is not necessarily the best solution for cost performance in order to realize a certain function. Yes.
One problem with SoC is that it is necessary to redesign the entire chip or remanufacture the original when it is desired to improve some of the functions within the chip. The SoC is not manufactured in a large quantity with a single chip like a general-purpose CPU or DRAM. Therefore, it is not always easy to improve and redesign frequently and quickly from the viewpoint of cost performance.

  Widely in electronic devices, useful functions are realized by mounting a large number of various semiconductor LSI chips on a printed circuit board. However, compared with the signal transmission speed in the semiconductor chip, the processing transmission speed in the printed circuit board is 1/10 or less, which is not sufficient. In order to improve the speed in the printed circuit board, it is necessary to create a high-density transmission line under impedance control, but this is difficult to realize with a printed circuit board manufacturing technique.

In view of such a problem, a silicon interposer that is not as dense as a semiconductor chip but can be mounted at a higher density than a normal printed circuit board and can be connected between semiconductor chips as fast as possible has come to attract attention. (For example, refer to Patent Document 1 and Patent Document 2 as having a through electrode, and refer to Patent Document 4 for not having a through electrode, for example). Each chip needs only to be replaced with a high-performance chip according to the progress and purpose of the improvement, so that the function can be improved quickly. Further, the wiring length between chips can be shortened as much as possible to increase the speed of transmission between chips. Furthermore, it is also intended to achieve both high-density mounting and high speed by arranging chips on both sides of the interposer and using a three-dimensional stack of chips together (for example, see Patent Document 3). The reason why silicon interposers are attracting attention is that, as described above, functions beyond the pitch conversion between terminals are expected.
In semiconductor memories, it is considered to increase the memory capacity by stacking a plurality of chips and connecting them with wiring. A plurality of proposals such as wire bonding using TSV (Through Silicon Via) and wire bonding have been proposed. By integrating such a three-dimensional laminated chip on a silicon interposer, both higher speed and higher functionality can be achieved.
These technologies are summarized into the words “More Moore” for further miniaturization and “More than Moore” for higher density and higher functionality by methods other than miniaturization.

As described above, the silicon interposer is expected as a method for realizing high functionality and high cost performance without depending only on miniaturization of the semiconductor process. However, since the function to be realized varies depending on the purpose, customization according to the application is required, and naturally there are not many applications that require a large quantity for one function. The silicon interposer has both sides as an extension of the semiconductor device and as an extension of densification of the high-density mounting printed circuit board.
In manufacturing a silicon interposer, if many semiconductor processes are used for miniaturization and high density, the cost becomes high, but miniaturization of 10 μm or less cannot be easily performed by the same process as a printed circuit board. Coexistence of cost and function similar to that of SoC is a major problem in the silicon interposer.

JP 2005-33153 A JP 2006-228834 A JP 2003-309121 A JP 2007-123753 A JP 2005-293778 A

There are several reasons why the process cost of a silicon interposer for mounting semiconductor chips densely increases. As already described, there are many methods to be applied to semiconductor processes. In addition, there is also a point of using semiconductor level technology infrastructure including materials.
As an example, FIG. 5 shows a case where the inside of a silicon via (a blind hole; hereinafter referred to as “via”) is filled with copper. Via formation (S102) is performed by patterning (S101) by an exposure process, and D-RIE (Deep Reactive Ion Etching; commonly called Bosch method). After the resist used for patterning is peeled off (S103), in order to fill the via with copper to form a through wiring, a film is formed by plasma CVD (S104) of about three layers in the via (oxide film / barrier film). / Seed film), and then the inside of the via is filled with copper from the bottom by electroplating (S105). Thereafter, the back surface is precisely ground (S106), and the via is penetrated to form TSV (Through Silicon Via), and the surface is thinned until the copper filling layer is exposed on the back surface. Depending on the application, film formation / wiring (S107) is also performed on the back surface, or the copper surface is smoothed. As described above, the interposer manufacturing process mainly uses a material for a semiconductor device and mainly includes a dry process using an apparatus common to the semiconductor process. Since the number of processes is large and many expensive devices are used, it is inevitable that the cost will increase in comparison with printed circuit boards. In the conventional method, it is necessary to perform preliminary film formation (oxide film / barrier film / seed film) in the via by plasma CVD. For example, it is not easy to completely form a preliminary film in a via having a high aspect ratio (substrate thickness: via diameter ratio) of 10 or more.

  The present invention has been made in view of the problems of the silicon interposer as described above, and an object of the present invention is to make it possible to realize an equivalent function by a simple technique that does not depend on a semiconductor process as much as possible. .

  The present invention is characterized in that a silicon interposer is directly formed on silicon by a wet method. That is, according to one aspect of the present invention, a nickel film and a copper film are formed in this order on a whole inner wall and all or a part of a main surface of all through holes of a silicon substrate in this order by displacement plating or electroless plating. It is a manufacturing method of the silicon substrate with a plating layer including the process to form into a film. Another aspect of the present invention is a silicon substrate having two or more through-holes, and the entire inner wall and all or some of the main surfaces of all the through-holes are formed from the substrate side with a nickel film, a copper film. It is a silicon substrate with a plating layer coated in this order.

  The present invention uses a silicon substrate having a purity lower than that of a semiconductor grade (11N or higher), and has been a major problem in conventional silicon interposers. The problem is solved and improved, and a silicon substrate suitable for a silicon interposer is provided. Further, film formation on both sides of the substrate, which has conventionally been performed by a multistage process, can be performed only by a plating apparatus (electroless / replacement).

It is typical sectional drawing of the multilayer wiring circuit board containing the interposer which is one use aspect of the silicon substrate of this invention. It is a flowchart which shows the one aspect | mode of the manufacturing process of the silicon interposer of this invention. (A) Whole cross section showing an aspect of direct deposition of Ni nucleation film on Si substrate, (b) Whole cross section with changed contrast of (a), (c) Through hole central portion Q part of (a) It is a SEM image of. (A) Whole cross section, (b) P-portion vicinity of through-hole opening in (a), (c) Through-hole in (a) showing one aspect of wet deposition of Ni nucleation film and Cu film on Si through-hole It is a SEM image of the hole center part Q part. It is a flowchart which shows the one aspect | mode of the manufacturing process of the conventional silicon interposer.

Hereinafter, in order to solve the above-mentioned problems, the contents of the present invention will be described in detail.
The same members are denoted by the same reference numerals. In addition, this invention is not restrict | limited to the form demonstrated below. It will be readily appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention.
FIG. 1 shows a schematic cross-sectional view of a multilayer wiring circuit board including an interposer, which is a preferred application of the silicon substrate with a plating layer of the present invention. In the multilayer printed circuit board 1 shown in FIG. 1, the interposer 3 is inserted between the MPU 5 and the RF device 7. Solder balls 9 are provided at both ends of the interposer and can be electrically connected to a printed circuit board (not shown). In FIG. 1, the logic LSI 11, the memory 13, and the sensor / MEMS 15 are sequentially stacked on the RF device 7, but it is naturally not limited to this layer configuration.
FIG. 2 shows an example of a manufacturing process of the silicon substrate with a plating layer of the present invention. In the present invention, after patterning (S1) as in the prior art, TSV is formed in the silicon substrate (S2) by the Bosch method or other methods, and the resist used for patterning is peeled off (S3). Thereafter, a nickel film is first formed by displacement plating on the silicon substrate by plating (S4-1), and then a copper film is formed thereon by electroless plating (S4-2). Therefore, in the conventional method, the film deposition process on both sides, which had to be performed in multiple stages using a plasma CVD apparatus, electroplating apparatus, precision grinding machine, and sputtering apparatus, can be performed only by the plating apparatus (electroless / replacement). It becomes possible.
In the present invention, a TSV is formed in advance, and the inside of the TSV is directly formed by a wet method. In this case, the ion species of plating to be formed are supplied from both sides of the substrate, and if the flow of the plating solution (liquid circulation, substrate rotation, etc.) is taken into consideration, the TSV with a much higher aspect ratio than the conventional method is completely completed. It becomes possible to coat.
The silicon substrate used in the present invention does not need to be a high-purity wafer used for semiconductor device fabrication. Since a substrate that can be plated is sufficient, a purity of 99.9999% or more (6N or more) is sufficient. Of course, it is needless to say that a silicon material having a semiconductor level of 11N or more can be used. What is necessary is just to select the thing of purity as needed, such as a case where a certain device is produced on a silicon interposer.
Using a silicon substrate having a purity of 6N or more, a conductive metal film is formed on all surfaces of the silicon substrate having a plurality of through holes only by a wet plating method, and used for high-density mounting applications such as an interposer. A silicon substrate is provided.
The silicon substrate used in the present invention has a purity of 99.9999% or more (6N or more). A silicon substrate having a purity of less than 6N has an obstacle in performing TSV processing and film formation because a plurality of μm-sized defects and insoluble precipitates having a size larger than that exist on the substrate surface and in the substrate. Therefore, a purity of 6N or higher is necessary.
A high-purity silicon substrate of 11N or higher used for semiconductors is naturally suitable for the process of this application. However, in the case of an interposer, the electrical characteristics of the silicon substrate are not necessarily used except when a device is formed on the substrate or when wiring is performed from the first layer. Therefore, a silicon substrate having a purity suitable for the purpose may be used.

In order to open a plurality of TSVs on the substrate, it is necessary to perform patterning (S1) first. Patterning includes various methods such as a printing method (screen method, gravure method, letterpress method, ink jet method, etc.), nanoimprint method, and light exposure method (photolithography method). Furthermore, TSV processing with a diameter of 100 μm or less is possible by physical methods such as drilling and laser processing. Among these, the finest and most accurate patterning is possible by the photoexposure method (mainly used in semiconductor processes). Even in the nanoimprint method, fine patterning of several tens of nm or less has been studied. For example, it has been attempted to produce a magnetic dot of 20 nm or less by the nanoimprint method, which is difficult for HDD applications even by a photolithography method.
Since the size of TSV used for a silicon interposer is generally 10 μm or more, it is not always necessary to use the light exposure method. An optimum method may be selected from the above methods depending on the TSV size and pattern.
The density of TSV is not particularly limited, but can be 50 μm pitch or more.

A common method for micro-hole processing (S2) of TSV is D-RIE (Deep Reactive Ion Etching; commonly called Bosch method). The Bosch method is a general technique for producing a high aspect ratio Via while sequentially switching the gas type SF6 for isotropic etching and the gas type C4F8 for surface coating of the inner wall of Via. It is widely used in the production of MEMS, and this method can also be used in TSV processing of a silicon interposer. The Bosch method is the most reliable method at the present time capable of machining deep holes with a diameter of several μm with high accuracy. Of course, a wet method or the like can be selected depending on the via diameter and the type of pattern.
Next, resist stripping (S3) is performed as in the conventional method.

For TSV obtained by micro-hole processing, prior to nickel film formation on the inner wall surface by the wet method described later, for removal of surface contamination, oxide film, silicon degradation layer, etc.,
For example, it is desirable to perform the pretreatment by etching with a surfactant such as a nonionic surfactant (for example, NCW), an alkali such as hydrogen fluoride, NaOH, or KOH.

In the present invention, what is decisively different from the conventional method is that film formation (S4) is performed only on the wet method without forming any dry film on silicon having TSV, that is, on the flat surface and the inner wall surface of TSV. It is. It is difficult to place a copper film on silicon with good adhesion by plating. As already described, a preliminary film is usually formed by a dry method. However, in the present invention, a nickel film is first formed on silicon by displacement plating.
The film thickness of the nickel film can be set to, for example, 50 nm to 500 nm.
The present inventors have devised and filed an application that nickel displacement plating can form a film with good adhesion on a silicon flat surface without reacting with silicon (Patent Document 5). However, the nickel displacement plating in the TSV may not be sufficiently supplied with ionic species unlike the flat surface. In particular, when the via diameter of TSV is reduced and the aspect ratio is increased, the flow of the plating solution is remarkably hindered, so that the ion species are deficient and the film thickness differs greatly between the flat surface and the TSV, or in the worst case in the TSV. In particular, it is conceivable that a nickel film cannot be formed at the center. However, in the present invention, a nickel film can be formed by displacement plating in the same manner as on a flat surface if appropriate pretreatment of hydrophilization with a surfactant on the silicon surface in TSV and activation by alkali etching is performed. I understood. FIG. 4 shows the film formation state of the nickel film 33 on the surface of the silicon substrate 31 having a thickness of 0.1 μm. The film is formed with a small film thickness difference between the flat surface and the TSV 32 having a diameter of 50 μm. Furthermore, a copper film can be continuously formed on the nickel film with good adhesion by electroless plating. The copper film could be similarly formed not only on the silicon flat surface but also on the nickel film in the TSV. The reducing agent for electroless copper plating includes formaldehyde, hypophosphorous acid, glyoxylic acid and the like, and is not particularly limited to one reducing agent. In order to perform good plating film formation, metal ions need to be sufficiently supplied to the silicon surface portion. Therefore, not only the plating solution conditions but also the plating solution flow must be optimized. The rotation of the silicon substrate is effective as one method for generating a plating solution flow inside the flat portion or the through hole. Since there is no big difference between displacement plating and electroless plating on the flat surface and in TSV, and even if the aspect ratio is large, the difference is not necessarily large. It is thought that it depends not only on ion diffusion in the plating solution. For this reason, it will be possible to form a film in a deep hole having an aspect ratio of 10 or more. When the via diameter of the TSV is reduced and the aspect ratio is increased, the penetration of the plating solution into the TSV can be promoted by rotating the substrate.

The copper plating film covers both the flat surface and the TSV inner surface. Of course, it is also possible to partially shield with a resist layer or an ink layer and to form a plating film only on the opening. The film thickness of the copper plating film can be set to, for example, 500 nm to 5 μm. As a method of using the silicon interposer according to the present invention, the entire silicon substrate surface can be used as a ground layer. The copper plating layer can be finely processed (S5) and used as a wiring layer. Of course, it is possible to use the copper coating layer in the TSV as the through wiring. Furthermore, it is possible to cover the silicon surface with a desired pattern and to wire only the exposed portion by plating film formation.
Thus, by using the plating method of the present invention, it becomes possible to perform copper coating to a fine and deep hole with an aspect ratio of 10 or more by a remarkably simple process and method. It is possible to provide a substrate with high cost performance that could not be realized by a conventional silicon interposer mainly based on a dry method.

Examples 1-10
A single crystal silicon (P-type, resistance value 10 Ω · cm) substrate using polycrystalline silicon having a purity of 6N-11N as a raw material was used. The substrate thickness is 100 μm to 500 μm. The substrate surface was subjected to precision grinding (Examples 1 to 4) using a # 8000 diamond bond grindstone or CMP polishing (Examples 5 to 10) using colloidal silica as an abrasive. Silicon substrate surface in order to carry out the plating is not necessarily a mirror finished by polishing, the substrate was etched lapping after stress relief, it may be a substrate which is processed by precision grinding. There is no processing deterioration layer that can ensure the adhesion strength between the plating film and the substrate during the plating treatment, or even if the deterioration layer has a surface with a small inside and outside of 1 μm. Further, as the size of the through hole for patterning becomes smaller, it is necessary to improve the surface smoothness in proportion thereto. The substrate was patterned with each size of 10, 20, 50, and 100 μm by a general light exposure method in a semiconductor process. At this time, each pattern was not circular but rectangular. This is because the width of the cross section is reliably measured when the cross section of the substrate is cut and observed with an SEM, so that a constant width can be obtained regardless of which part is cut. Of course, the through-hole shape may be circular. Using the substrate, through-hole processing was performed by the Bosch method. The processing was performed by a general method, and isotropic etching with SF6 and sidewall coating with C4F8 were performed while periodically switching the gas species.
In order to perform the plating process on the silicon substrate subjected to the through hole processing, the flat surface and the inner surface of the through hole were sequentially pretreated with a surfactant (eg NCW) and alkali (NaOH, KOH, etc.). Each purpose is for removing dirt on the surface, removing an oxide film, and removing a silicon deteriorated layer. A nickel nucleation film was formed by displacement plating on the pretreated silicon substrate surface, and the target thickness of the nickel nucleation film was 300 nm to 400 nm. The conditions for displacement plating are as follows. Substitution plating was performed for about 10 minutes using NiSO4 as a metal species in an ammonium sulfate bath and adjusting the pH to 8-9 with ammonium hydroxide.
Subsequently, electroless plating was subsequently performed on the silicon substrate on which the nucleated nickel film was formed to form a copper film. Activation treatment with Pd and electroless plating with reducing agent formaldehyde (temperature 30 ° C x 40 min) are continuously performed. The target thickness of the copper plating film is approximately 2.0 μm regardless of the size of the through hole. It was.
The processes related to the plating film formation were performed continuously. Of course, it is possible to move to another apparatus in the middle of the process, but it is desirable to carry out the process continuously without drying the substrate surface as much as possible. In this example, the silicon substrate was not rotated.
About the silicon substrate with a plating layer in which copper was formed, a peel test was performed using a scotch tape (manufactured by 3M), but no peel was observed, and the adhesion was good. The silicon substrate with a plating layer on which the copper film was formed was cut at a through hole with a micro-dicer, and the cross section was observed with an SEM. FIG. 5 shows a state in which a nickel nucleation film / copper film is formed inside the through hole. It was found that the silicon substrate 31 / nickel nucleation film 33 / copper film 35 were stacked in this order. Copper 35 is formed in close contact with the flat portion 34 a as well as the inside 34 b of the through hole 32. When the through hole was 10 μm, it was found that the copper plating film thickness (1.24 μm) in the central part of the through hole was about 30% thinner than the film thickness of the flat part (1.78 μm). However, the thickness distribution has no problem in using the interposer. In addition, a tester terminal was applied to the front and back surfaces of the flat portion 34a, but it was confirmed that continuity was confirmed. In the present invention, it was possible to produce a substrate having a conductive film with good adhesion directly on silicon (including the inside of the through hole) only by a wet plating method.
Table 1 shows a list of silicon substrates on which the plating film of the present invention was formed.

  From Table 1, it was found that a uniform copper film was also formed inside the through hole having an aspect ratio of 20. One of the great advantages of the plating method is that the film can be formed up to a region having an aspect ratio that is difficult by the dry method.

  The silicon substrate having the conductive film of the present invention can be used by mounting electronic components at high density and inserting between a semiconductor device and a printed wiring board.

1 multilayer wiring circuit board 3 silicon interposer 5 MPU
7 RF device 9 Solder ball 11 Logic LSI
13 Memory 15 Sensor / MEMS
31 Silicon substrate 32 Through-hole 33 Nickel (nucleation) film 34a Flat portion 34b Through-hole inner wall 35 Copper plating film S1, S101 Patterning S2, S102 Silicon etching S3, S103 Resist stripping S4 Through-via non-electroplating S5, S107 Insulating layer -Wiring formation S104 Pretreatment film (insulation layer + diffusion prevention layer + seed layer)
S105 Copper electroplating in vias S106 Grinding (Back grinding)

Claims (5)

  A silicon substrate having two or more through-holes, in which the entire inner wall and all or part of the main surface of all the through-holes are coated in the order of nickel film and copper film from the substrate side. With silicon substrate.   2. The silicon substrate with a plating layer according to claim 1, wherein the nickel film and the copper film are both formed by a wet method and do not have a film structure by a dry method on the side closer to the silicon substrate surface than the copper film.   3. The silicon substrate with a plating layer according to claim 1, wherein the silicon substrate has a purity of 99.9999% or more and is used for high-density mounting of a semiconductor device or an electronic component.   4. The aspect ratio of the thickness of the silicon substrate to the circle-converted diameter of the through-hole (thickness of the silicon substrate / diameter of the diameter of the through-hole circle) is 10 or more. 5. Silicon substrate with plating layer. Providing two or more through holes in the silicon substrate;
With a plating layer including a step of forming a nickel film and a copper film in this order by displacement plating and electroless plating on the entire inner wall and all or part of the main surface of all through holes of the silicon substrate A method for manufacturing a silicon substrate.