JP2004056036A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device capable of reducing the quantity of polishing for flattening a copper film formed to fill a hole in an insulating film, and occurrence of unpolished portion, and dishing and erosion due to excessive polishing can be prevented. <P>SOLUTION: The manufacturing method for a semiconductor device comprises a first process for forming a hole 13 in an insulating film 12 on a substrate 11, a second process for forming a seed metal layer 15 on the insulating film 12 to cover an inner wall of the hole 13, a third process for removing the seed metal layer 15 formed over the insulating film 12 while leaving the seed metal layer 15 formed on the inner wall of the hole 13, a fourth process for embedding a copper film 17 in the hole 13 by selectively growing the copper film 17 on the seed metal layer 15 with plating, and a fifth process for removing the copper film 17 protruded from the hole 13 to flatten the device. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor having a process of forming wirings and vias by burying a copper film in wiring grooves and connection holes formed in an insulating film and flattening the copper film. The present invention relates to a device manufacturing method.
[0002]
[Prior art]
Due to the high integration of LSIs, internal wirings are becoming finer and multilayered, and accordingly, flattening technology at the time of forming wirings, processing of fine wirings, and securing reliability have become important issues. As one of means for solving these problems, an embedded wiring technique such as a damascene method has been studied and partially developed. In particular, attention has been paid to an embedded wiring technology using copper, which aims at high-speed operation and low power consumption, and mass production has been partially started.
[0003]
According to such an embedded wiring technique, as shown in FIG. 4A, an insulating film 12 is formed on a substrate 11 made of a silicon substrate, and a hole 13 serving as a wiring groove or a via hole is formed by dry etching or the like. Form.
Then, as shown in FIG. 4B, after the electrode layer 14 is formed on the insulating film 12 so as to cover the inner wall of the hole 13 by a sputtering method or the like, the inner wall of the hole 13 is formed by a sputtering method or the like. A seed metal layer 15 is formed so as to cover the formed electrode layer 14.
[0004]
Next, as shown in FIG. 4C, the copper film 17 is grown on the seed metal layer 15 so as to fill the hole 13 with the copper film 17 by, for example, an electrolytic plating method using a copper sulfate solution or the like. .
Then, as shown in FIG. 4D, the copper film 17 is flattened by a chemical mechanical polishing (CMP) method, and then, as shown in FIG. Excess copper film 17, seed metal layer 15, and electrode layer 14 are removed until the surface is exposed.
Thus, a wiring or a via is formed in the hole 13.
[0005]
The above-described embedded wiring technology using copper is used not only for LSI chips but also for packaging technology for packages and boards.
[0006]
[Problems to be solved by the invention]
However, when the copper film 17 is formed on the seed metal layer 15 so as to fill the hole 13 by the electrolytic plating method, the hole is also formed on the seed metal layer 15 outside the hole 13 as shown in FIG. A copper film 17 having a thickness corresponding to the depth of 13 is formed. Therefore, when the copper film 17 is planarized by the CMP method, the copper film 17 outside the hole 13 is also polished and removed, so that there is a problem that it takes time to planarize the copper film 17. Was.
In particular, when a wiring is formed by embedding the copper film 17 in the hole 13 formed in the insulating film 12 on the mounting board, the thickness of the copper film 17 to be the wiring is formed on the order of microns. The time required for flattening the film 17 was very long.
[0007]
Further, the copper film 17 in the case of filling the hole 13 tends not to have a flat surface according to the density of the arrangement pattern of the hole 13.
Therefore, as the amount of the copper film 17 to be polished increases, the unpolished residue is generated. If the unpolished residue is not generated, excessive polishing is performed, and problems such as dishing and erosion of the buried wiring have occurred.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a first step of forming a hole in an insulating film on a substrate, and a step of forming a seed on the insulating film so as to cover an inner wall of the hole. A second step of forming a metal layer, a third step of removing the seed metal layer above the insulating film while leaving the seed metal layer formed on the inner wall of the hole, and a selective step on the seed metal layer by plating. And a fifth step of growing a copper film and burying the copper film in the hole, and a fifth step of removing the copper film protruding from the hole and planarizing the copper film.
[0009]
According to such a method of manufacturing a semiconductor device, the seed metal layer is removed inside the hole, the seed metal layer above the insulating film outside the hole is removed, and a copper film is selectively formed on the seed metal layer by plating. After the copper film is embedded in the hole, the copper film protruding from the hole is removed and flattened, so that the copper film is formed even outside the hole. The polishing amount of the film can be reduced. Therefore, the time required for flattening the copper film can be reduced.
Further, since the polishing amount of the copper film can be reduced, it is possible to prevent the occurrence of unpolished residue and dishing or erosion due to excessive polishing.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(1st Embodiment)
An example of an embodiment according to a method of manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process sectional views of FIGS.
[0011]
As shown in FIG. 1A, an element is formed on a substrate 11 (for example, a silicon substrate) by a normal LSI process, and then an insulating film 12 is formed.
Although illustration is omitted here, it is assumed that a conductive layer is pattern-formed on the surface of the substrate 11.
Next, holes 13 serving as wiring grooves or via holes for connection to the conductive layer are formed by reactive etching using a resist pattern (not shown) as a mask, and the resist pattern is removed.
[0012]
Next, as shown in FIG. 1B, an electrode layer 14 is formed on the insulating film 12 so as to cover the inner wall of the hole 13. The electrode layer 14 is used as an electrode for electrolytic plating when forming a copper film in a later step.
The electrode layer 14 is made of a material that does not easily adhere to the electrode layer 14 exposed outside the hole 13 when a copper film is selectively grown on the seed metal layer 15 in the hole 13 by electrolytic plating. It is preferable that
Further, in the present embodiment, as described later, since a copper film is embedded in the hole 13 and a copper thin film is used as the seed metal layer 15, the electrode layer 14 also functions as a barrier metal for preventing diffusion of copper. There is a need.
[0013]
As such a film, for example, a compound such as tantalum, tantalum nitride, tantalum oxynitride, tantalum silicon nitride, titanium nitride, titanium oxynitride, titanium silicon nitride, tungsten nitride, tungsten oxynitride, or tungsten silicon nitride can be used. it can.
Among the above compounds, a tantalum-based compound is particularly preferable because it has a high effect of preventing copper from adhering. Here, for example, tantalum is used for the electrode layer 14.
[0014]
Next, a seed metal layer 15 made of, for example, a copper thin film is formed on the surface of the electrode layer 14 following the formation of the electrode layer 14.
Here, a copper thin film having high adhesion to copper is used as the seed metal layer 15, but the present invention is not limited to this, and a copper film to be buried in the hole 13 in a later step is likely to adhere. Just fine.
The above-described electrode layer 14 and seed metal layer 15 can be formed by, for example, a sputtering method, a chemical vapor deposition (Chemical Vapor Deposition (CVD) method), or an evaporation method.
[0015]
Next, as shown in FIG. 1C, a protective film 16 made of, for example, a resin is formed on the seed metal layer 15 so as to cover the seed metal layer 15 formed in the hole 13.
Here, in the fine hole 13, the hole 13 may be buried by the protective film 16.
The protective film 16 protects the seed metal layer 15 inside the hole 13 when the seed metal layer 15 outside the hole 13 is removed in a later step.
[0016]
Then, as shown in FIG. 1D, the protective film 16 above the insulating film 12 outside the hole 13 is removed by, for example, mechanical polishing, leaving the protective film 16 inside the hole 13.
Subsequently, the seed metal layer 15 above the insulating film 12 outside the hole 13 is polished and removed by, for example, a CMP method, so that the electrode layer 14 outside the hole 13 is exposed.
Here, the protection film 16 and the seed metal layer 15 outside the hole 13 are removed by two-stage polishing, but the protection film 16 and the seed metal layer 15 may be removed by one-stage polishing.
[0017]
Thereafter, as shown in FIG. 2E, the protective film 16 (see FIG. 1D) in the hole 13 is removed by dry etching using oxygen plasma or wet etching using a solvent, and the seed metal is removed. The layer 15 is exposed.
[0018]
Next, as shown in FIG. 2F, a copper film 17 is selectively grown on the seed metal layer 15 by an electrolytic plating method, and the copper film 17 is buried in the hole 13.
At this time, since the seed metal layer 15 is not formed outside the hole 13 and the electrode layer 14 to which the copper film 17 is not easily adhered is exposed, the copper film 17 is not formed outside the hole 13. The copper film 17 is buried only in the hole 13.
[0019]
Next, as shown in FIG. 2G, the copper film 17 protruding from the hole 13 is removed by polishing by a CMP method, and the copper film 17 is planarized.
Specifically, polishing is performed until the height of the electrode layer 14 outside the hole 13 becomes the same as that of the electrode layer 14.
[0020]
Subsequently, as shown in FIG. 2H, the copper film 17 (including the seed metal layer 15) and the electrode layer 14 are polished and removed by, for example, a CMP method until the surface of the insulating film 12 is exposed.
Here, the polishing is performed until the surface of the insulating film 12 is exposed by the CMP method. However, the present invention is not limited to this, and dry etching or wet etching may be used.
Thus, a wiring or a via made of copper is formed in the hole 13.
[0021]
According to such a method of manufacturing a semiconductor device, the seed metal layer 15 is removed outside the hole 13 while leaving the seed metal layer 15 in the hole 13, and the copper film 17 is selectively formed on the seed metal layer 15. After the copper film 17 is buried in the hole 13, the portion of the copper film 17 protruding from the hole 13 is removed, and the copper film 17 is planarized. And the time required for flattening the copper film 17 can be reduced.
Therefore, since TAT (Turn Around Time) can be shortened, productivity can be improved.
Further, since the amount of polishing of the copper film 17 can be reduced, it is possible to prevent the occurrence of unpolished residue and dishing and erosion due to excessive polishing.
[0022]
Further, as shown in FIG. 1D, since the protective film 16 is formed so as to cover the seed metal layer 15 formed in the hole 13, the case where the seed metal layer 15 outside the hole 13 is removed In addition, it is possible to protect the seed metal layer 15 in the hole 13 from being removed.
[0023]
In this embodiment, an example in which the protective film 16 is formed on the seed metal layer 15 has been described. However, the present invention is not limited to this, and the seed metal layer 15 outside the hole 13 is selectively removed. If possible, the protective film 16 need not be formed.
[0024]
In the present embodiment, the example in which the copper film 17 is embedded in the hole 13 by the electrolytic plating method has been described, but the present invention is not limited to this, and the copper film 17 may be formed by the electroless plating method.
However, when the present invention is applied to a mounting substrate, the electrolytic plating method does not require much time to embed the copper film 17 even if the thickness is on the order of microns, and the film quality is good. It is preferable because it can sufficiently cope with a thick film.
In the present embodiment, the electrode layer 14 is formed because the copper film is formed by the electrolytic plating method. However, the electrode layer 14 may not be formed by the electroless plating method. The layer 15 may be formed of a material having excellent copper adhesion and preventing copper diffusion.
[0025]
Further, in the present embodiment, an example in which wirings or vias are formed on a semiconductor substrate (substrate 11) such as a silicon substrate has been described. However, the present invention is not limited to this. It can also be used for forming wiring.
Here, FIG. 3A shows a schematic configuration diagram of a flip-chip type multi-chip module as an example used for a mounting substrate.
In the multi-chip module shown in this figure, two LSIs 22 are mounted side-by-side by flip-chip connection on a substrate 21 having a multilayer wiring layer (not shown), and are resin-sealed by an underfill 23.
A plurality of solder balls 24 serving as connection terminals are formed below the substrate 21.
[0026]
Here, as shown in an enlarged view of a main part of FIG. 3B, it is assumed that a multilayer wiring layer 32 is formed on a substrate 31 made of, for example, ceramic on the mounting substrate 21.
Although illustration is omitted here, a solder ball 24 (see FIG. 3A) is formed at a lower portion of the substrate 31, and the inside of the substrate 31 is electrically conductive with the solder ball 24. It is assumed that a wiring pattern is formed.
[0027]
When the above-mentioned multilayer wiring layer 32 is formed, a micron-order insulating film 34 is formed on the substrate 31 on which the conductive layer 33 is patterned, and wiring for connecting to the conductive layer 33 is formed on the insulating film 34. A hole 35 to be a groove or a via hole is formed.
Here, the hole 35 may be a hole 35a having a step such that a via hole is continuously formed at the bottom of the wiring groove.
[0028]
An electrode layer (not shown) and a seed metal layer (not shown) are formed in the hole 35 (including the hole 35a) as in the above-described embodiment, and the seed metal layer is formed only in the hole 35. The copper film 36 is selectively grown on the seed metal layer.
The copper film 36 has a thickness corresponding to the depth of the hole 35 formed in the insulating film 34. Since the insulating film 34 is formed on the micron order here, the copper film 36 is also on the micron order. Is formed.
[0029]
Then, after the copper film 36 protruding from the hole 35 is removed and planarized, the copper film 36 (including the seed metal layer) and the electrode layer are removed until the surface of the insulating film 34 is exposed. A wiring or a via is formed in 35.
Then, the insulating film 34 is further formed on the insulating film 34, and the step of forming wirings or vias by the same method is repeated to form the multilayer wiring layer 32.
[0030]
When the present invention is applied to the mounting substrate as described above, since the thickness of the copper film 36 is large, the polishing amount of the copper film 36 is reduced by embedding the copper film 36 only in the hole 35. Thus, the time required for planarizing the copper film 36 can be significantly reduced.
Further, when the copper film 37 is buried in the hole 35a having the step by the so-called dual damascene method, the copper film 36 is formed thicker according to the depth of the hole 35. In this case, too. According to the present invention, since the polishing amount of the copper film 36 can be reduced, the time required for flattening the copper film 36 can be reduced.
[0031]
Further, even when the substrate 31 has irregularities, the amount of polishing of the copper film 36 can be reduced, so that the occurrence of unpolished portions and dishing or erosion due to excessive polishing can be prevented, and flattening is easy.
[0032]
The present invention is effective when the multilayer wiring layer 32 is formed on a mounting board. For example, after forming such a multilayer wiring layer 32 on another substrate, only the multilayer wiring layer 32 is transferred to a circuit board and used. You can also.
[0033]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, a copper film is selectively formed on the seed metal layer in the hole, and the copper film is buried in the hole. Since the protruding copper film is removed and planarized, the amount of polishing of the copper film can be reduced, so that the time required for planarization can be reduced. As a result, the TAT can be shortened, so that productivity can be improved.
In addition, since the polishing amount of the copper film can be reduced, dishing and erosion due to generation of unpolished residue and excessive polishing can be prevented, flattening is easy, and a multilayer wiring layer can be easily formed. It is possible.
[0034]
In particular, since the copper film is formed on the order of microns on the mounting substrate, the time required for planarization can be greatly reduced by reducing the polishing amount of the copper film.
[Brief description of the drawings]
FIG. 1 is a sectional view (part 1) of a manufacturing process showing an example of an embodiment according to a method of manufacturing a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view (part 2) illustrating an example of an embodiment of the method for manufacturing a semiconductor device according to the present invention;
FIGS. 3A and 3B are a schematic configuration diagram showing an example of a case where the method for manufacturing a semiconductor device of the present invention is applied to a mounting board, and an enlarged view of a main part, respectively.
FIG. 4 is a manufacturing process sectional view showing a method of manufacturing a semiconductor device according to a conventional technique.
[Explanation of symbols]
11, 31: substrate, 12, 34: insulating film, 13, 35: hole, 14: electrode layer, 15: seed metal layer, 16: protective film, 17, 36: copper film

Claims (3)

A first step of forming a hole in the insulating film on the substrate;
A second step of forming a seed metal layer on the insulating film so as to cover an inner wall of the hole;
A third step of removing the seed metal layer above the insulating film while leaving the seed metal layer formed on the inner wall of the hole;
A fourth step of selectively growing a copper film on the seed metal layer by plating and embedding the copper film in the hole;
A step of removing the copper film protruding from the hole and planarizing the copper film. Between the second step and the third step,
After forming a protective film on the seed metal layer so as to cover the inner wall of the hole in which the seed metal layer is formed, the insulating film is formed while leaving the protective film formed on the inner wall of the hole. Performing a step of removing the upper protective film,
Between the third step and the fourth step,
2. The method according to claim 1, wherein a step of removing a protective film left in the hole is performed. Between the first step and the second step,
Performing a step of forming an electrode layer on the insulating film so as to cover the hole,
In the second step, a seed metal layer is formed on the electrode layer so as to cover an inner wall of the hole in which the electrode layer is formed,
2. The method according to claim 1, wherein, in the fourth step, a copper film is buried in the hole by electrolytic plating.

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