CN106373938A - Structure of hybrid-density package substrate and packaging method thereof - Google Patents
Structure of hybrid-density package substrate and packaging method thereof Download PDFInfo
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- CN106373938A CN106373938A CN201611015529.6A CN201611015529A CN106373938A CN 106373938 A CN106373938 A CN 106373938A CN 201611015529 A CN201611015529 A CN 201611015529A CN 106373938 A CN106373938 A CN 106373938A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to a structure of a hybrid-density package substrate and a packaging method thereof, and belongs to the technical field of semiconductor packaging. The structure comprises a common substrate (20), a super-high-density substrate (10), a high-density chip (51), a low-density chip (53), and an encapsulated layer I (310). The super-high-density substrate (10) is embedded into the encapsulated layer I (310). The super-high-density substrate (10) is in inverted connection with the high-density chip (51), and the lower surface thereof is connected with the common substrate (20) through blind holes I (130). A plurality of substrate outer metal electrodes (110) are formed outside the vertical area of the super-high-density substrate (10). The substrate outer metal electrodes (110) are connected with the common substrate (20) through blind holes II (150), and the upper surfaces thereof are in inverted connection with the low-density chip (53). Each pad II (250) is equipped with a solder bump. The packaging structure is implemented by means of wafer level packaging. Integration of a super-high-density substrate and a common substrate is realized. The packaging reliability is improved, and thus, the product yield can be improved.
Description
Technical field
The present invention relates to a kind of structure of hybrid density base plate for packaging and its method for packing, belong to semiconductor packaging neck
Domain.
Background technology
Electronic product increasingly miniaturization, lighting, multi-functional, low-power consumption and inexpensive development trend, (two-dimentional) encapsulation of 2d
Technology cannot meet requirement, and portioned product has begun to develop to 2.5d or 3d encapsulation direction.And in 2.5d or 3d encapsulation
In structure, silicon substrate pinboard is used in combination with organic substrate, is the important way realizing chip and chip, chip and substrate interconnection
Footpath.
Traditional tsv interposer substrate processing technology is: 1) prepares blind hole on substrate；2) substrate one side pecvd deposit is logical
Hole sidewall passivation layer；3) stick/diffusion impervious layer, Seed Layer metal in substrate one side magnetron sputtering deposit through-hole side wall；4) electricity
Depositing process completes via metal filling；5) via metal planarization；6) thinning expose substrate back via metal；7) make metal
Wiring, pad and its protective layer.
Traditional tsv interposer substrate preparation method also following defect or deficiency:
(1) pecvd deposit deep hole sidewall passivation layer lack of homogeneity, deep hole bottom thickness of insulating layer only about top 1/5,
Bottom insulation layer coverage rate is poor, easily produces discontinuous defect and has a strong impact on insulation effect and reliability.Which also limits
Passivation layer depositing technics depth-to-width ratio deposits ability；
(2) magnetron sputtering deposit deep hole side wall adhesion/diffusion impervious layer, Seed Layer lack of homogeneity, deep hole bottom thickness is only about
Have the 1/5 of top, deep hole bottom coverage rate is poor, easily produce discontinuous defect and lead to occur cavity during plating, serious shadow
Ring through hole reliability.At present, the deep hole depth-to-width ratio deposit ability of state-of-the-art magnetron sputtering apparatus is less than 15:1, which has limited
Tsv depth-to-width ratio deposits ability；
(3) depth-to-width ratio is the deep hole of 20:1～30:1, and realization no hole plating fill process difficulty is larger, and large aperture will
Occupy element assembling area, reduce layout area, be unfavorable for high-density packages；
(4) it is limited to above-mentioned tradition tsv interposer substrate processing technology, usual interposer substrate thickness is less than 200 μm, only can be used as turning
Connect substrate it is impossible to directly be assembled with whole machine plate；
(5) tsv keyset process costs are higher, and packaging technology is complicated, does not possess cost advantage in many encapsulation technologies；
(6) there is physical difference because of silicon and organic material substrate in tsv keyset, is embedded in organic substrate and there is reliability and ask
Topic is it is difficult to carry out structural integrity；
(7) common organic substrate can meet general density encapsulation and require, but it is (such as convex less than 55um spacing to realize VHD
Point upside-down mounting) encapsulation requirement.
Content of the invention
Shown on holding, it is an object of the invention to overcoming the shortcomings of above-mentioned tradition organic substrate and tsv switching plate technique, carry
Simple for a kind of technique for applying, it is provided simultaneously with ultra-high density structures and the hybrid density organic group of common density encapsulating structure is hardened
Structure and its method for packing.
The object of the present invention is achieved like this:
A kind of structure of hybrid density base plate for packaging, it includes common substrate, and the upper surface of described common substrate is provided with several
Pad, lower surface are provided with several pads,
Also include VHD substrate, several superchips, several low density chips and encapsulated layer, described encapsulated layer
It is arranged at the upper surface of common substrate, described VHD substrate is by some floor height density interconnection metal layer and selective spacer again
Insulating barrier therebetween is constituted, and its upper and lower surface is respectively provided with pad, two-layer or two-layer the above high density wiring metal again
Presence is selectively electrically connected with layer each other, and described VHD substrate is embedded in encapsulated layer and its upper surface and its pad
Expose encapsulated layer, the pad of upper surface of described VHD substrate is connected with described superchip upside-down mounting, its lower surface
Pad is connected with the part pad of common substrate by penetrating metal in the blind hole of encapsulated layer and its blind hole, in described superelevation
Form several substrate outer metal electrodes, the lower surface of described substrate outer metal electrode leads to outside the vertical area of density substrate
Cross metal in blind hole and its blind hole be connected with the part pad of common substrate, its upper surface and described low density chip upside-down mounting
Connect, described pad arranges solder projection.
The high density of VHD substrate of the present invention again interconnection metal layer live width/line-spacing be below 6/6um.
Alternatively, the high density of described VHD substrate again interconnection metal layer live width/line-spacing be 5/5um, 3/3um or
1.8/1.8um.
The high density of VHD substrate of the present invention again interconnection metal layer the number of plies be more than 3 layers.
Alternatively, the high density of described VHD substrate again interconnection metal layer the number of plies be 6 layers, 7 layers, 8 layers.
Present invention additionally comprises encapsulated layer, described encapsulated layer covering superchip, low density chip and high density base
Plate, encapsulated layer, the exposed part of substrate outer metal electrode.
Alternatively, present invention additionally comprises through hole, described through hole penetrates encapsulated layer and common substrate, filler metal in it, institute
The lower surface stating substrate outer metal electrode is connected with the part pad of common substrate by metal in through hole and its through hole.
A kind of method for packing of present invention hybrid density base plate for packaging, including following technical process:
Step one, the upper surface of the upper surface of VHD substrate and carrier is passed through the attachment of two-sided stripping film and fix, described super
High-density base board is formed by wiring metal technique again, its again wiring metal live width/line-spacing be below 6/6um；
Step 2, by way of vacuum pad pasting two-sided stripping film upper surface formed encapsulated layer, by VHD substrate bag
It is overlying on wherein；
Step 3, pass through common lamination process, by VHD substrate by penetrate the blind hole of encapsulated layer and its interior metal with
The part pad of common substrate connects；
Step 4, carrier of separating and two-sided stripping film, expose upper surface and its pad of VHD substrate；
Step 5, sequentially pass through laser boring technique, copper plating process, formed blind outside the vertical area of VHD substrate
Metal and substrate outer metal electrode in hole and its blind hole, the partly part of described substrate outer metal electrode and common substrate
Pad passes through metal in blind hole and its blind hole and connects；Especially, while forming blind hole, sequentially pass through laser boring
Technique, copper plating process, form metal in through hole and its through hole outside the vertical area of VHD substrate, make partly described
Substrate outer metal electrode is connected by metal in through hole and its through hole with the part pad of common substrate；
Step 6, superchip is connected with the pad upside-down mounting of VHD substrate, low density chip and substrate outer metal
Electrode upside-down mounting or attachment connect；
Step 7, pass through fill process, cover superchip, low density chip and high-density base board, encapsulating with encapsulating material
Layer, the exposed part of substrate outer metal electrode, form encapsulated layer, and the pad setting of the opposite side in common substrate
Solder projection.
The invention has the beneficial effects as follows:
1st, the hybrid density package substrate construction of the present invention adopts VHD organic substrate to replace si interposer, and embedding
Enter to common organic substrate structure, technique decrease tsv(through silicon via, silicon hole) technique, fc
(upside-down mounting) technique, underfilling(bottom filler) processing procedure such as technique, make packaging technology simpler, reduce further and produce into
This, improve production efficiency；
2nd, the hybrid density package substrate construction of the present invention provides less live width/line by quoting VHD organic substrate
Away from the number of plies of, more high density interconnection metal layer again, the multiple superchip of integration packaging and low in equal package area
Density chip, effectively not only can shorten information transmission path, and can realize more multi-functional, more power, realize more
Exit, is conducive to signal quickly to transmit, to adapt to quasiconductor ic element in aspect of performances such as high speed, high frequency and high capacities
Quick raising, further reduced simultaneously entirety package thickness, answered by spacial influence with adapting to many high-performance
With device, it is a kind of encapsulation technology with high cost benefit and motility；
3rd, the present invention takes full advantage of the flexibility characteristics of VHD substrate, improves package reliability, is conducive to product yield
Lifting.
Brief description
Fig. 1 is the schematic diagram of the flow process of the method for packing of hybrid density base plate for packaging of the present invention；
Fig. 2 is a kind of generalized section of the embodiment of encapsulating structure of present invention hybrid density base plate for packaging；
Fig. 3 a to Fig. 3 i is the partial cutaway schematic of the method for packing of hybrid density base plate for packaging of Fig. 2 embodiment；
Wherein:
VHD substrate 10
Substrate outer metal electrode 110
Blind hole 130
Blind hole 150
Through hole 170
Common substrate 20
Pad 230
Pad 250
Soldered ball 251
Encapsulated layer 310
Encapsulated layer 430
Superchip 51
Low density chip 53
Encapsulated layer 610.
Specific embodiment
Referring to Fig. 1, a kind of method for packing of present invention hybrid density base plate for packaging, comprise the technical steps that:
S1: VHD substrate is fixed on carrier；
S2: encapsulated layer coats VHD substrate；
S3: by common build up(lamination) VHD substrate is connected by technique with common substrate；
S4: carrier of separating exposes upper surface and its pad of VHD substrate；
S5: sequentially pass through laser boring technique, copper plating process, form hole and hole outside the vertical area of VHD substrate
Interior metal and substrate outer metal electrode, substrate outer metal electrode is connected by the hole metal with common substrate；
S6: superchip is connected with the pad of VHD substrate, low density chip is connected with substrate outer metal electrode；
S7: encapsulating superchip, low density chip and high-density base board, encapsulated layer, the exposed portion of substrate outer metal electrode
Point.
Embodiment
Common substrate 20 generally refers to manufacture electronics hybrid density base plate for packaging, manufactures the motherboard carrying electronic devices and components
Basic material.It has conduction, insulation and the function of supporting three aspects, and generally, substrate is exactly copper-clad laminate,
By selectively carrying out the processing such as hole machined, electroless copper, electro-coppering, etching, required circuitous pattern is obtained on substrate, and
Form several pads 230 in the upper surface of common substrate 20, lower surface forms several pads 250, as shown in Figure 2.One
As, the live width/line-spacing of the metal level of common substrate 20 is 40/40um, 20/20um, 8/8um, limiting case can accomplish live width/
Line-spacing 10/10um.The structure of the hybrid density base plate for packaging of the present invention, it is arranged above common substrate 20 has flexible spy
The VHD substrate 10 of point.Interconnection metal layer and selective spacer be therebetween again by several floor height density for this VHD substrate 10
Insulating barrier constitute, interconnection metal layer exists and is selectively electrically connected with high density more than two-layer or two-layer each other again, and
Upper and lower surface in VHD substrate 10 is respectively provided with pad, and it possesses light, thin, resistance to fall and shape-plastic height etc. is flexible special
Point.Using wiring metal technique again, the live width/line-spacing of the high density of VHD substrate 10 interconnection metal layer again be 6/6um with
Under, typically in (3-5)/(3-5) um, live width/line-spacing minimum can reach 1/1um to live width/line-spacing.Its metal line number of plies is at 3 layers
More than, generally 4-6 layer, at most can reach 8 layers.Live width/line-spacing can be defined in detail according to specific product design with the number of plies.
High density interconnection metal layer again live width/line-spacing in below 6/6um, such as live width/line-spacing is 5/5um, 3/3um, 1.8/1.8um
Deng with the increase of the high density number of plies of interconnection metal layer again, its technology difficulty is in that saltatory is incremented by.It follows that with common
Substrate 20 is compared, and the live width/line-spacing of VHD substrate 10 is less, the number of plies of high density interconnection metal layer again is more, unit plane
Long-pending interconnection metal layer again is closeer, therefore referred to as VHD substrate 10, and its gross thickness is less than 100um, is conducive to reducing overall
Package thickness.Meanwhile, VHD substrate 10 has flexibility characteristics, and the entirety that can lift hybrid density base plate for packaging can
By property.
The upper surface setting encapsulated layer 310 of common substrate 20, this VHD substrate 10 is embedded in encapsulated layer 310 and
Its upper surface and its pad expose encapsulated layer 310.The material of this encapsulated layer 310 can use the normal packet of organic substrate industry
Sealing film material, including but not limited to epoxiess encapsulating resin, such as abf film.
Pad by the upper surface in VHD substrate 10 for superchip 51 upside-down mounting.Superchip 51 be often referred to r,
C, l etc. are applied to require high accuracy, the little passive element of size, and its encapsulation feature is that its chip metal convex number is many, chip
Metal salient point spacing each other is little.The number of superchip 51 can single it is also possible to multiple, as shown in Fig. 2 highly dense
Degree chip 511, superchip 513 model can identical it is also possible to different.
The pad of the lower surface of VHD substrate 10 is by penetrating blind hole 130 and its blind hole Endothelium corneum of encapsulated layer 310
Belong to and being connected with the part pad 230 of common substrate 20.Formed outside several substrates outside the vertical area of VHD substrate 10
Layer metal electrode 110.The lower surface of this substrate outer metal electrode 110 by penetrate encapsulated layer 310 blind hole 150 and its
In blind hole, metal is connected with the part pad 230 of common substrate 20.Or according to actual needs, make part substrate outer layer metal electricity
The lower surface of pole 110 is by penetrating metal and common substrate in the through hole 170 of encapsulated layer 310 and common substrate 20 and its through hole
20 part pad 250 connects.
Low density chip 53 refers to that its chip metal convex number is few, chip metal convex spacing each other is not little
Chip.The upper surface of substrate outer metal electrode 110 is connected with low density chip 53.As shown in Figure 2.Low density chip 531,
Low density chip 535 is connected with the upper surface attachment of substrate outer metal electrode 110, and low density chip 537 passes through soldered ball and base
The upper surface upside-down mounting of plate outer layer metal electrode 110 connects.The lower surface of substrate outer metal electrode 110 pass through blind hole 150 and
In its blind hole, metal is connected it is also possible to by penetrating encapsulated layer 310 and common substrate with the part pad 230 of common substrate 20
Metal in 20 through hole 170 and its through hole, makes the part pad of part substrate outer layer metal electrode 110 and common substrate 20
250 realize connecting.
The encapsulating material that material includes but is not limited to abf film covers superchip 51, low density chip 53 and high density base
Plate 10, encapsulated layer 310, the exposed part of substrate outer metal electrode 110, form encapsulated layer 610.This encapsulated layer 610
Material and the material of encapsulated layer 310 can be identicals it is also possible to different.
The solder projections such as soldered ball 251, welding block can be set at pad 250, the electrical information of whole encapsulating structure is carried out
Input and output.
When in use, the signal of telecommunication of superchip 511 passes through VHD substrate 10, blind hole 130 and its blind hole
Interior metal and common substrate 20 are realized being electrically connected with, as shown in Figure 2.Low density chip 53 can also be by substrate outer metal electricity
Metal or electricity is realized by metal in through hole 170 and its through hole and common substrate 20 in pole 110, blind hole 150 and its blind hole
Property connect.
The encapsulating structure of the hybrid density base plate for packaging of the present invention, can be with thinning hybrid density with VHD substrate 10
A series of overall package thickness of base plate for packaging, it is to avoid defects and work that the tsv deep hole that conventional package exists is brought
Skill problem；Meanwhile, the reduction of overall package thickness, to adapt to many high-performance but to be subject to the application device of spacial influence, is a kind of
There is the encapsulation technology of high cost benefit and motility.
The method for packing of the encapsulating structure of hybrid density base plate for packaging of above-described embodiment, referring to Fig. 3 a to Fig. 3 i.Its work
Skill process is specific as follows:
Step one, two-sided stripping film t1 is sticked on carrier 700, this two-sided stripping film t1 can be uv film or hot stripping film, carry
N alignment mark is had on body 700, by test for pass(qualified) VHD substrate 10 mount on two-sided stripping film t1,
And make the upper surface of the upper surface of VHD substrate 10 downwardly carrier 700.
This VHD substrate 10 is formed by wiring metal technique again, the live width/line of its high density interconnection metal layer again
Away from minimum 1/1um, general live width/line-spacing is (3-5) um/(3-5) um, it is fixed in detail to carry out according to specific product design
Justice, the number of plies of its middle-high density interconnection metal layer again is 8 layers to the maximum, the high density wiring metal again of usual VHD substrate 10
The number of plies of layer is 4-6 layer；As shown in Figure 3 a and Figure 3 b shows, wherein Fig. 3 b is the profile of the local i amplification of Fig. 3 a.
Step 2, stick encapsulated layer 310 in the upper surface of two-sided stripping film t1 by way of vacuum pad pasting, by superelevation
Density substrate 10 is coated on wherein, and this encapsulated layer 310 can adopt organic substrate industry common wrap film material, such as abf
Film；As shown in Figure 3 c.
Step 3, by common build up(lamination) technique, by VHD substrate 10 by penetrating encapsulated layer 310
Blind hole 130 and its interior metal be connected with the pad 230 of common substrate 20；In the process, core can be increased as needed
Plate, to increase the intensity of whole electric hybrid board, as shown in Figure 3 d.
Step 4, the encapsulating structure in step 3 is spun upside down 180 degree, by corresponding separating technology, by carrier 700
Separate with two-sided stripping film t1 and VHD substrate 10, expose the upper surface of high-density base board VHD substrate 10.Due to
The material of two-sided stripping film t1 is uv film or hot stripping film, and therefore separating technology usually carries out uv illumination again or enters baking oven
Heating；As shown in Figure 3 e.
Step 5, sequentially using laser boring technique, copper plating process, in the vertical area profile of VHD substrate 10
Becoming to penetrate metal in the blind hole 150 of encapsulated layer 310 and its blind hole, to form substrate outer metal by copper plating process electric simultaneously
Pole 110, substrate outer metal electrode 110 is vertically connected with by metal in blind hole with common substrate 20.In addition, according to actual need
Will, can make in through hole 170 and its through hole penetrating encapsulated layer 310 and common substrate 20 while making blind hole 150
Metal, substrate outer metal electrode 110 is vertically connected with by metal in through hole with common substrate 20, and its processing procedure can also be sequentially
Using laser boring technique, copper plating process.As illustrated in figure 3f.
Step 6, pass through fc(upside-down mounting) technique, by superchips such as superchip 511, superchip 513 51 with
The pad of VHD substrate 10 connects, by fc(upside-down mounting) technique, low density chip 537 grade low density chip 53 is passed through weldering
Ball is connected with substrate outer metal electrode 110, or is mounted by smt() technique, by low density chip 531, low density chip
535 grade low density chips 53 are connected with substrate outer metal electrode 110.As shown in figure 3g.
Step 7, pass through fill process, cover superchip 51, low density chip 53 and high density base with encapsulating material
Plate 10, encapsulated layer 310, the exposed part of substrate outer metal electrode 110, form encapsulated layer 610.And common substrate 20
The pad 250 setting solder projection of opposite side, such as soldered ball 251.As shown in Fig. 3 h and 3i.
Above-mentioned processing procedure, all using wafer level processing technique, is not required to the tsv technique using very complicated, avoids Deep hole electroplating
A series of problems, such as technique, reduce production cost, improve production efficiency, and apply the VHD substrate 10 with flexibility
Improve package reliability, be conducive to the lifting of product yield.
It is pointed out that any change that one skilled in the art is done to the specific embodiment of the present invention
Scope all without departing from claims of the present invention.Correspondingly, the scope of the claim of the present invention is also not merely limited to
In previous embodiment.
Claims (10)
1. a kind of structure of hybrid density base plate for packaging, it includes common substrate (20), the upper surface of described common substrate (20)
It is provided with several pads (230), lower surface is provided with several pads (250),
It is characterized in that: also include VHD substrate (10), several superchips (51), several low density chips
(53) and encapsulated layer (310), described encapsulated layer (310) is arranged at the upper surface of common substrate (20), described VHD base
By some floor height density, interconnection metal layer and selective spacer insulating barrier therebetween is constituted plate (10) again, and its upper and lower surface is equal
Setting pad, interconnection metal layer exists each other and is selectively electrically connected with again for two-layer or the above high density of two-layer, described
VHD substrate (10) is embedded in encapsulated layer (310) and its upper surface and its pad expose encapsulated layer (310), described superelevation
The pad of upper surface of density substrate (10) is connected with described superchip (51) upside-down mounting, the pad of its lower surface passes through to penetrate
In the blind hole (130) of encapsulated layer (310) and its blind hole, metal is connected with the part pad (230) of common substrate (20), in institute
Form several substrate outer metal electrodes (110), described substrate outer gold outside the vertical area stating VHD substrate (10)
The lower surface belonging to electrode (110) passes through the part pad of metal and common substrate (20) in blind hole (150) and its blind hole
(230) connect, its upper surface is connected with described low density chip (53) upside-down mounting, described pad (250) arranges solder projection.
2. a kind of hybrid density base plate for packaging according to claim 1 structure it is characterised in that: described VHD base
The high density of plate (10) again interconnection metal layer live width/line-spacing be below 6/6um.
3. a kind of hybrid density base plate for packaging according to claim 2 structure it is characterised in that: described VHD base
The high density of plate (10) again interconnection metal layer live width/line-spacing be 5/5um, 3/3um or 1.8/1.8um.
4. a kind of hybrid density base plate for packaging according to claim 1 structure it is characterised in that: described VHD base
The high density of plate (10) again interconnection metal layer the number of plies be more than 3 layers.
5. a kind of hybrid density base plate for packaging according to claim 4 structure it is characterised in that: described VHD base
The high density of plate (10) again interconnection metal layer the number of plies be 6 layers, 7 layers, 8 layers.
6. a kind of hybrid density base plate for packaging according to claim 1 structure it is characterised in that: also include encapsulated layer
(610), described encapsulated layer (610) covers superchip (51), low density chip (53) and high-density base board (10), encapsulating
Layer (310), the exposed part of substrate outer metal electrode (110).
7. a kind of hybrid density base plate for packaging according to any one of claim 1 to 6 structure it is characterised in that: also
Including through hole (170), described through hole (170) penetrates encapsulated layer (310) and common substrate (20), filler metal in it, described base
The lower surface of plate outer layer metal electrode (110) passes through metal and the part of common substrate (20) in through hole (170) and its through hole and welds
Disk (250) connects.
8. a kind of method for packing of hybrid density base plate for packaging, including following technical process:
Step one, by the upper surface of the upper surface of VHD substrate (10) and carrier (700) pass through two-sided stripping film (t1) paste
Dress is fixed；
Step 2, by way of vacuum pad pasting two-sided stripping film (t1) upper surface formed encapsulated layer (310), by superelevation
Density substrate (10) is coated on wherein；
Step 3, pass through common lamination process, by VHD substrate (10) by penetrating the blind hole of encapsulated layer (310)
And its interior metal is connected with the part pad (230) of common substrate (20) (130)；
Step 4, carrier of separating (700) and two-sided stripping film (t1), expose upper surface and its weldering of VHD substrate (10)
Disk；
Step 5, sequentially pass through laser boring technique, copper plating process, in the profile of the vertical area of VHD substrate (10)
Become metal and substrate outer metal electrode (110) in blind hole (150) and its blind hole, partly described substrate outer metal electrode
(110) it is connected by metal in blind hole (150) and its blind hole with the part pad (230) of common substrate (20)；
Step 6, superchip (51) is connected with the pad upside-down mounting of VHD substrate (10), low density chip (53) with
(110) upside-down mounting of substrate outer metal electrode or attachment connect；
Step 7, pass through fill process, cover superchip (51), low density chip (53) and high density base with encapsulating material
Plate (10), encapsulated layer (310), the exposed part of substrate outer metal electrode (110), form encapsulated layer (610), and general
Pad (250) the setting solder projection of the opposite side of logical substrate (20).
9. a kind of hybrid density base plate for packaging according to claim 8 method for packing it is characterised in that: in step one
In, also include forming, by wiring metal technique again, the VHD substrate (10) that live width/line-spacing is below 6/6um.
10. a kind of hybrid density base plate for packaging according to claim 9 method for packing it is characterised in that: in step 5
In, sequentially pass through laser boring technique, copper plating process, form through hole outside the vertical area of VHD substrate (10)
(170) metal and its in through hole, the partly part pad of described substrate outer metal electrode (110) and common substrate (20)
(250) pass through metal in through hole (170) and its through hole to connect.
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| CN111554656A (en) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | Semiconductor packaging device |
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