CN106373938B - A kind of structure and its packaging method of hybrid density package substrate - Google Patents
A kind of structure and its packaging method of hybrid density package substrate Download PDFInfo
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- CN106373938B CN106373938B CN201611015529.6A CN201611015529A CN106373938B CN 106373938 B CN106373938 B CN 106373938B CN 201611015529 A CN201611015529 A CN 201611015529A CN 106373938 B CN106373938 B CN 106373938B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention relates to the structures and its packaging method of a kind of hybrid density package substrate, belong to technical field of semiconductor encapsulation.It includes common substrate (20), ultra high density substrate (10), superchip (51), low density chip (53) and encapsulated layer I (310), ultra high density substrate (10) is in encapsulated layer I (310), ultra high density substrate (10) is connect with superchip (51) upside-down mounting, its lower surface is connect by blind hole I (130) with common substrate (20), several substrate outer metal electrodes (110) are formed outside the vertical area of ultra high density substrate (10), substrate outer metal electrode (110) is connect by blind hole II (150) with common substrate (20), its upper surface is connect with low density chip (53) upside-down mounting, solder projection is arranged in pad II (250).The encapsulating structure is realized using wafer-level encapsulation method, is realized the integrated of ultra high density substrate and common substrate, is improved package reliability, be conducive to the promotion of product yield.
Description
Technical field
The present invention relates to the structures and its packaging method of a kind of hybrid density package substrate, belong to semiconductor packaging neck
Domain.
Background technique
Electronic product increasingly minimizes, lighting, multi-functional, low-power consumption and inexpensive development trend, 2D (two dimension) are encapsulated
Technology can no longer meet requirement, and portioned product, which has begun to 2.5D or 3D encapsulation direction, to be developed.And it is encapsulated in 2.5D or 3D
In structure, silicon substrate pinboard is used in combination with organic substrate, is the important way for realizing chip and chip, chip and substrate interconnection
Diameter.
Traditional TSV interposer substrate manufacture craft are as follows: 1) blind hole is prepared on substrate；2) substrate single side PECVD deposit is logical
Hole sidewall passivation layer；3) stick/diffusion barrier layer, seed layer metal in substrate single side magnetron sputtering deposit through-hole side wall；4) electric
Depositing process completes via metal filling；5) via metal planarizes；6) it is thinned and exposes substrate back via metal；7) metal is made
Wiring, pad and its protective layer.
There are also following defect or deficiencies for traditional TSV interposer substrate preparation method:
(1) PECVD deposit deep hole sidewall passivation layer uniformity it is poor, deep hole bottom thickness of insulating layer only about top
1/5, bottom insulation layer coverage rate is poor, is easy to produce discontinuous defect and seriously affects insulation effect and reliability.This is also limited
Passivation layer depositing technics depth-to-width ratio deposit ability is made；
(2) magnetron sputtering deposit deep hole side wall adherency/diffusion barrier layer, seed layer uniformity are poor, and deep hole bottom thickness is big
About there was only the 1/5 of top, deep hole bottom coverage rate is poor, is easy to produce discontinuous defect and leads to occur when plating cavity, sternly
Ghost image rings through-hole reliability.Currently, the deep hole depth-to-width ratio deposit ability of state-of-the-art magnetron sputtering apparatus is less than 15:1, this limitation
TSV depth-to-width ratio deposits ability；
(3) depth-to-width ratio is the deep hole of 20:1~30:1, and realization is larger without hole plating fill process difficulty, and macropore
Diameter will occupy element assembling area, reduce layout area, be unfavorable for high-density packages；
(4) it is limited to above-mentioned tradition TSV interposer substrate manufacture craft, usual interposer substrate thickness only can be used less than 200 μm
Make interposer substrate, can not directly be assembled with complete machine plate；
(5) TSV pinboard high process cost, and packaging technology is complicated, and it is excellent not have cost in many encapsulation technologies
Gesture；
(6) TSV pinboard is because silicon and organic material substrate are there are physical difference, is embedded in organic substrate that there are reliabilities
Problem, it is difficult to carry out structural integrity；
(7) common organic substrate can meet general density encapsulation and require, but cannot achieve ultra high density (as lower than between 55um
Away from salient point upside-down mounting) encapsulation requirement.
Summary of the invention
Shown on holding, it is an object of the invention to overcome the shortcomings of above-mentioned traditional organic substrate and TSV switching plate technique, mention
Simple for a kind of technique for applying, the hybrid density organic group for being provided simultaneously with ultra-high density structures and common density encapsulating structure is hardened
Structure and its packaging method.
The object of the present invention is achieved like this:
A kind of structure of hybrid density package substrate comprising common substrate, if the upper surface of the common substrate is equipped with
Dry pad I, lower surface are equipped with several pads II,
It further include ultra high density substrate, several superchips, several low density chips and encapsulated layer I, the packet
Sealing I is set to the upper surface of common substrate, and the ultra high density substrate is by interconnection metal layer and the selection again of several layers high density
Property interval insulating layer therebetween constitute, and its upper and lower surface is respectively provided with pad, two layers or two layers high density described above cloth again
Line metal layer exists each other to be selectively electrically connected with, the ultra high density substrate in the encapsulated layer I and its upper surface and
Its pad exposes encapsulated layer I, and the pad of the upper surface of the ultra high density substrate connect with the superchip upside-down mounting, under it
The part pad I of metal and common substrate connects in blind hole I and its blind hole of the pad on surface by penetrating encapsulated layer I, in institute
It states and forms several substrate outer metal electrodes outside the vertical area of ultra high density substrate, under the substrate outer metal electrode
Surface passes through the connection of the part pad I of metal and common substrate, its upper surface and the low-density core in blind hole II and its blind hole
Solder projection is arranged in piece upside-down mounting connection, the pad II.
The high density of ultra high density substrate of the present invention again interconnection metal layer line width/line-spacing be 6/6um or less.
Optionally, the high density of the ultra high density substrate again interconnection metal layer line width/line-spacing be 5/5um, 3/3um or
1.8/1.8um。
The high density of ultra high density substrate of the present invention again interconnection metal layer the number of plies be 3 layers or more.
Optionally, the high density of the ultra high density substrate again interconnection metal layer the number of plies be 6 layers, 7 layers, 8 layers.
The invention also includes encapsulated layer II, the encapsulated layer II covers superchip, low density chip and high density base
Plate, encapsulated layer I, substrate outer metal electrode exposed part.
Optionally, the invention also includes through-hole, the through-hole penetrates encapsulated layer I and common substrate, interior to fill metal, institute
The lower surface for stating substrate outer metal electrode passes through the part pad II of metal and common substrate connection in through-hole and its through-hole.
A kind of packaging method of hybrid density package substrate of the present invention, including following technical process:
Step 1: the upper surface of ultra high density substrate and the upper surface of carrier are fixed by the attachment of two-sided stripping film, institute
It states ultra high density substrate to be formed by wiring metal technique again, then line width/line-spacing of wiring metal is 6/6um or less；
Step 2: encapsulated layer I is formed in the upper surface of two-sided stripping film by way of vacuum pad pasting, by ultra high density base
Plate is coated on wherein；
Step 3: by common lamination process, by ultra high density substrate by penetrate encapsulated layer I blind hole I and its interior gold
Category is connect with the part pad I of common substrate；
Step 4: carrier of separating and two-sided stripping film, expose upper surface and its pad of ultra high density substrate；
Step 5: laser boring technique, copper plating process are sequentially passed through, in the shape of the vertical area of ultra high density substrate
At metal in blind hole II and its blind hole and substrate outer metal electrode, the part substrate outer metal electrode and common substrate
Part pad I passes through metal connection in blind hole II and its blind hole；Particularly, while forming blind hole II, laser is sequentially passed through
Drilling technology, copper plating process form metal in through-hole and its through-hole except the vertical area of ultra high density substrate, make part
The part pad II of the substrate outer metal electrode and common substrate passes through metal connection in through-hole and its through-hole；
Step 6: by pad upside-down mounting connection, low density chip and the substrate outer of superchip and ultra high density substrate
Metal electrode upside-down mounting or attachment connection；
Step 7: by fill process, with encapsulating material covering superchip, low density chip and high-density base board,
The exposed part of encapsulated layer I, substrate outer metal electrode forms encapsulated layer II, and in the pad of the other side of common substrate II
Solder projection is set.
The beneficial effects of the present invention are:
1, hybrid density package substrate construction of the invention replaces Si Interposer using ultra high density organic substrate,
And be embedded in common organic substrate structure, TSV(Through Silicon Via, through silicon via are reduced in technique) technique,
FC(upside-down mounting) technique, the bottom underfilling(filler) processing procedures such as technique, keep packaging technology simpler, further reduced production
Cost improves production efficiency；
2, hybrid density package substrate construction of the invention by reference ultra high density organic substrate provide smaller line width/
The number of plies of line-spacing, more high density interconnection metal layer again, in same package area the multiple superchips of integration packaging and
Low density chip, can not only effectively shorten information transmission path, but also more multi-functional, higher power may be implemented, and realize more
More exits are conducive to signal and quickly transmit, to adapt to semiconducter IC element in performances sides such as high speed, high frequency and high capacities
The quick raising in face, while whole package thickness has been further reduced, to adapt to many high-performance but by spacial influence
Application device is a kind of encapsulation technology with high cost-effectiveness and flexibility；
3, the present invention takes full advantage of the flexibility characteristics of ultra high density substrate, improves package reliability, is conducive to product
The promotion of yield.
Detailed description of the invention
Fig. 1 is the schematic diagram of the process of the packaging method of hybrid density package substrate of the invention；
Fig. 2 is a kind of diagrammatic cross-section of the embodiment of the encapsulating structure of hybrid density package substrate of the present invention；
Fig. 3 A to Fig. 3 I is the partial cutaway schematic of the packaging method of the hybrid density package substrate of Fig. 2 embodiment；
Wherein:
Ultra high density substrate 10
Substrate outer metal electrode 110
Blind hole I 130
Blind hole II 150
Through-hole 170
Common substrate 20
Pad I 230
Pad II 250
Soldered ball 251
Encapsulated layer I 310
Encapsulated layer II 430
Superchip 51
Low density chip 53
Encapsulated layer II 610.
Specific embodiment
Referring to Fig. 1, a kind of packaging method of hybrid density package substrate of the present invention is comprised the technical steps that:
S1: ultra high density substrate is fixed on carrier；
S2: encapsulated layer I coats ultra high density substrate；
S3: passing through common Build up(lamination) ultra high density substrate connect by technique with common substrate；
S4: carrier of separating exposes upper surface and its pad of ultra high density substrate；
S5: sequentially passing through laser boring technique, copper plating process, forms hole except the vertical area of ultra high density substrate
And metal and substrate outer metal electrode in hole, substrate outer metal electrode are connect with metal in common substrate through hole；
S6: superchip is connect with the pad of ultra high density substrate, low density chip and substrate outer metal electrode
Connection；
S7: encapsulating superchip, low density chip and high-density base board, encapsulated layer I, substrate outer metal electrode it is naked
Reveal part.
Embodiment
Common substrate 20 generally refers to manufacture electronics hybrid density package substrate, manufactures the motherboard for carrying electronic component
Basic material.It has the function of three aspects of conductive, insulation and support, and under normal circumstances, substrate is exactly copper-clad laminate,
It is processed by selectively carrying out hole machined, electroless copper, electro-coppering, etching etc., required circuitous pattern is obtained on substrate, and
The upper surface of common substrate 20 forms several pads I 230, lower surface forms several pads II 250, as shown in Figure 2.One
As, line width/line-spacing of the metal layer of common substrate 20 is 40/40um, 20/20um, 8/8um, limiting case can accomplish line width/
Line-spacing 10/10um.The structure of hybrid density package substrate of the invention, in the top of common substrate 20, setting has flexible special
The ultra high density substrate 10 of point.Interconnection metal layer and selective spacer be therebetween again by several layers of high density for the ultra high density substrate 10
Insulating layer constitute, two layers or two layers or more of high density again interconnection metal layer each other exist be selectively electrically connected with, and
It is respectively provided with pad in the upper and lower surface of ultra high density substrate 10, has light, thin, resistance to fall and shape-plastic height etc. is flexible special
Point.Using wiring metal technique again, line width/line-spacing of the high density of ultra high density substrate 10 interconnection metal layer again be 6/6um with
Under, for line width/line-spacing generally in (3-5)/(3-5) um, line width/line-spacing minimum can reach 1/1um.Its metal line number of plies is at 3 layers
More than, it generally 4-6 layers, at most can be up to 8 layers.Line width/line-spacing can be designed according to specific product with the number of plies and is defined in detail.
High density interconnection metal layer again line width/line-spacing in 6/6um hereinafter, if line width/line-spacing is 5/5um, 3/3um, 1.8/1.8um
Deng with the increase of the high density number of plies of interconnection metal layer again, technology difficulty is incremented by great-jump-forward.It follows that with common
Substrate 20 is compared, and line width/line-spacing of ultra high density substrate 10 is smaller, the number of plies of high density interconnection metal layer again is more, unit plane
Interconnection metal layer is closeer again for product, therefore referred to as ultra high density substrate 10, and overall thickness is no more than 100um, is conducive to reduce whole
Package thickness.Meanwhile ultra high density substrate 10 has flexibility characteristics, the entirety that can promote hybrid density package substrate can
By property.
Encapsulated layer I 310 is arranged in the upper surface of common substrate 20, by the ultra high density substrate 10 in encapsulated layer I 310 and
Its upper surface and its pad expose encapsulated layer I 310.The normal packet of organic substrate industry can be used in the material of the encapsulated layer I 310
Sealing film material, including but not limited to epoxies encapsulating resin, such as ABF film.
By 51 upside-down mounting of superchip in the pad of the upper surface of ultra high density substrate 10.Superchip 51 be often referred to R,
C, L etc. is applied to require high-precision, the small passive element of size, and encapsulation feature is that its chip metal convex number is more, chip
Spacing between metal salient point is small.The number of superchip 51 can be single, can also be multiple, as shown in Fig. 2, highly dense
Spend chip 511, the model of superchip 513 may be the same or different.
It is golden in blind hole I 130 and its blind hole of the pad of the lower surface of ultra high density substrate 10 by penetrating encapsulated layer I 310
Category is connect with the part pad I 230 of common substrate 20.It is formed outside the vertical area of ultra high density substrate 10 outside several substrates
Layer metal electrode 110.The lower surface of the substrate outer metal electrode 110 by penetrate encapsulated layer I 310 blind hole II 150 and its
Metal is connect with the part pad I 230 of common substrate 20 in blind hole.Or according to actual needs, make part substrate outer layer metal electric
Metal and common substrate in through-hole 170 and its through-hole of the lower surface of pole 110 by penetrating encapsulated layer I 310 and common substrate 20
20 part pad II 250 connects.
Low density chip 53 refers to that the spacing of its chip metal convex number seldom, between chip metal convex is not small
Chip.The upper surface of substrate outer metal electrode 110 is connect with low density chip 53.As shown in Figure 2.Low density chip 531,
The upper surface of low density chip 535 and substrate outer metal electrode 110, which mounts, to be connected, and low density chip 537 passes through soldered ball and base
The upper surface upside-down mounting of plate outer layer metal electrode 110 connects.The lower surface of substrate outer metal electrode 110 by blind hole II 150 and
Metal is connect with the part pad I 230 of common substrate 20 in its blind hole, can also be by penetrating encapsulated layer I 310 and common substrate
Metal in 20 through-hole 170 and its through-hole makes the part pad II of part substrate outer layer metal electrode 110 Yu common substrate 20
250 realize connection.
Material includes but is not limited to encapsulating material covering superchip 51, low density chip 53 and the high density base of ABF film
Plate 10, encapsulated layer I 310, substrate outer metal electrode 110 exposed part, formed encapsulated layer II 610.The encapsulated layer II 610
Material and the material of encapsulated layer I 310 can be identical, can also be different.
The solder projections such as soldered ball 251, welding block can be set at pad II 250, the power information of entire encapsulating structure is carried out
Input and output.
When in use, the electric signal of superchip 511 passes through ultra high density substrate 10, blind hole I 130 and its blind hole
Interior metal and common substrate 20, which are realized, to be electrically connected, as shown in Figure 2.Low density chip 53 can also pass through substrate outer metal electricity
Metal or electricity is realized by metal in through-hole 170 and its through-hole and common substrate 20 in pole 110, blind hole II 150 and its blind hole
Property connection.
Hybrid density can be thinned with ultra high density substrate 10 in the encapsulating structure of hybrid density package substrate of the invention
The overall package thickness of package substrate avoids a series of defects and work brought by TSV deep hole existing for conventional package
Skill problem；Meanwhile the reduction of overall package thickness is a kind of to adapt to many high-performance but by the application device of spacial influence
Encapsulation technology with high cost-effectiveness and flexibility.
The packaging method of the encapsulating structure of the hybrid density package substrate of above-described embodiment, referring to Fig. 3 A to Fig. 3 I.Its work
Skill process is specific as follows:
Step 1: stick two-sided stripping film T1 on carrier 700, the two-sided stripping film T1 can be UV film or hot soarfing from
Film has N number of alignment mark on carrier 700, will test as Pass(qualification) the attachment of ultra high density substrate 10 to two-sided stripping film
On T1, and make the upper surface of the upper surface of ultra high density substrate 10 downwardly carrier 700.
The ultra high density substrate 10 is formed by wiring metal technique again, line width/line of high density interconnection metal layer again
Away from minimum 1/1um, general line width/line-spacing is (3-5) um/(3-5) um, it is fixed in detail progress can be designed according to specific product
Justice, the number of plies of middle-high density interconnection metal layer again are up to 8 layers, the high density of usual ultra high density substrate 10 wiring metal again
The number of plies of layer is 4-6 layers；As shown in Figure 3A and Figure 3B, wherein Fig. 3 B be Fig. 3 A local I amplification sectional view.
Step 2: encapsulated layer I 310 is sticked in the upper surface of two-sided stripping film T1 by way of vacuum pad pasting, by superelevation
Density substrate 10 is coated on wherein, which can use the common wrap film material of organic substrate industry, such as ABF
Film；As shown in Figure 3 C.
Step 3: passing through common Build up(lamination) technique, by ultra high density substrate 10 by penetrating encapsulated layer I 310
Blind hole I 130 and its interior metal connect with the pad I 230 of common substrate 20；In the process, it can according to need increase core
Plate, to increase the intensity of entire electric hybrid board, as shown in Figure 3D.
Step 4: the encapsulating structure in step 3 is spun upside down 180 degree, by corresponding separating technology, by carrier 700
It is separated with two-sided stripping film T1 and ultra high density substrate 10, exposes the upper surface of high-density base board ultra high density substrate 10.Due to
The material of two-sided stripping film T1 is UV film or hot stripping film, therefore separating technology usually carries out UV illumination again or enters baking oven
Heating；As shown in FIGURE 3 E.
Step 5: laser boring technique, copper plating process are sequentially used, in the vertical area shape of ultra high density substrate 10
Substrate outer metal electricity is formed at metal in the blind hole II 150 and its blind hole for penetrating encapsulated layer I 310 while by copper plating process
Pole 110, substrate outer metal electrode 110 are vertically connected with common substrate 20 by metal in blind hole.In addition, according to practical need
It wants, can be made while making blind hole II 150 in the through-hole 170 and its through-hole that penetrate encapsulated layer I 310 and common substrate 20
Metal, substrate outer metal electrode 110 are vertically connected with common substrate 20 by metal in through-hole, and processing procedure is also possible to sequentially
Use laser boring technique, copper plating process.As illustrated in Figure 3 F.
Step 6: pass through FC(upside-down mounting) technique, by the superchips 51 such as superchip 511, superchip 513 with
The pad of ultra high density substrate 10 connects, and passes through FC(upside-down mounting) technique, the low density chips 53 such as low density chip 537 are passed through into weldering
Ball is connect with substrate outer metal electrode 110, or is mounted by SMT() technique, by low density chip 531, low density chip
535 equal low density chips 53 are connect with substrate outer metal electrode 110.As shown in Figure 3 G.
Step 7: by fill process, with encapsulating material covering superchip 51, low density chip 53 and high density base
Plate 10, encapsulated layer I 310, substrate outer metal electrode 110 exposed part, formed encapsulated layer II 610.And common substrate 20
Solder projection is arranged in the pad II 250 of the other side, such as soldered ball 251.As shown in Fig. 3 H and 3I.
Above-mentioned processing procedure is all made of wafer level processing technology, is not required to the TSV technique using very complicated, avoids Deep hole electroplating
A series of problems, such as technique, reduces production cost, improves production efficiency, and applying has ultra high density substrate 10 flexible
Package reliability is improved, the promotion of product yield is conducive to.
It should be pointed out that any change that one skilled in the art does a specific embodiment of the invention
All without departing from the range of claims of the present invention.Correspondingly, the scope of the claims of the invention is also not merely limited to
In previous embodiment.
Claims (3)
1. a kind of packaging method of hybrid density package substrate, including following technical process:
Step 1: the upper surface of the upper surface of ultra high density substrate (10) and carrier (700) is pasted by two-sided stripping film (T1)
Dress is fixed；
Step 2: encapsulated layer I (310) are formed in the upper surface of two-sided stripping film (T1) by way of vacuum pad pasting, by superelevation
Density substrate (10) is coated on wherein；
Step 3: by common lamination process, by ultra high density substrate (10) by penetrating the blind hole I of encapsulated layer I (310)
(130) and its interior metal is connect with the part pad I (230) of common substrate (20)；
Step 4: carrier of separating (700) and two-sided stripping film (T1), expose upper surface and its weldering of ultra high density substrate (10)
Disk；
Step 5: laser boring technique, copper plating process are sequentially passed through, in the shape of the vertical area of ultra high density substrate (10)
At metal in blind hole II (150) and its blind hole and substrate outer metal electrode (110), the part substrate outer metal electrode
(110) it is connect with the part pad I (230) of common substrate (20) by metal in blind hole II (150) and its blind hole；
Step 6: by the pad upside-down mounting connection of superchip (51) and ultra high density substrate (10), low density chip (53) with
(110) upside-down mounting of substrate outer metal electrode or attachment connection；
Step 7: by fill process, with encapsulating material covering superchip (51), low density chip (53) and high density base
Plate (10), encapsulated layer I (310), substrate outer metal electrode (110) exposed part, formed encapsulated layer II (610), and general
Solder projection is arranged in the pad II (250) of the other side of logical substrate (20).
2. a kind of packaging method of hybrid density package substrate according to claim 1, it is characterised in that: in step 1
In, it further include forming line width/line-spacing by wiring metal technique again as 6/6um ultra high density substrate (10) below.
3. a kind of packaging method of hybrid density package substrate according to claim 2, it is characterised in that: in step 5
In, laser boring technique, copper plating process are sequentially passed through, forms through-hole except the vertical area of ultra high density substrate (10)
(170) metal, the part pad II of part the substrate outer metal electrode (110) and common substrate (20) and its in through-hole
(250) pass through metal connection in through-hole (170) and its through-hole.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593644B2 (en) * | 2001-04-19 | 2003-07-15 | International Business Machines Corporation | System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face |
| CN102386104A (en) * | 2010-09-01 | 2012-03-21 | 群成科技股份有限公司 | Quadrilateral flat pin-free encapsulation method |
| CN103050487A (en) * | 2011-10-11 | 2013-04-17 | 台湾积体电路制造股份有限公司 | Integrated circuit structure having dies with connectors of different sizes |
| CN104427761A (en) * | 2013-09-02 | 2015-03-18 | 欣兴电子股份有限公司 | Flexible and hard circuit board module and manufacturing method thereof |
| CN104795380A (en) * | 2015-03-27 | 2015-07-22 | 江阴长电先进封装有限公司 | Three-dimensional packaging structure |
| CN105575889A (en) * | 2014-10-29 | 2016-05-11 | 巨擘科技股份有限公司 | Method for manufacturing three-dimensional integrated circuit |
| CN206225357U (en) * | 2016-11-18 | 2017-06-06 | 江阴长电先进封装有限公司 | A kind of structure of hybrid density package substrate |
Family Cites Families (1)
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593644B2 (en) * | 2001-04-19 | 2003-07-15 | International Business Machines Corporation | System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face |
| CN102386104A (en) * | 2010-09-01 | 2012-03-21 | 群成科技股份有限公司 | Quadrilateral flat pin-free encapsulation method |
| CN103050487A (en) * | 2011-10-11 | 2013-04-17 | 台湾积体电路制造股份有限公司 | Integrated circuit structure having dies with connectors of different sizes |
| CN104427761A (en) * | 2013-09-02 | 2015-03-18 | 欣兴电子股份有限公司 | Flexible and hard circuit board module and manufacturing method thereof |
| CN105575889A (en) * | 2014-10-29 | 2016-05-11 | 巨擘科技股份有限公司 | Method for manufacturing three-dimensional integrated circuit |
| CN104795380A (en) * | 2015-03-27 | 2015-07-22 | 江阴长电先进封装有限公司 | Three-dimensional packaging structure |
| CN206225357U (en) * | 2016-11-18 | 2017-06-06 | 江阴长电先进封装有限公司 | A kind of structure of hybrid density package substrate |
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