TWM531651U - Substrate-free interposer and semiconductor device using same - Google Patents

Description

Substrate without interposer and application of semiconductor device

The present invention belongs to the field of interposer technology of a semiconductor device, and specifically refers to a substrate-free interposer structure that does not use a pre-formed wafer, glass or organic layer substrate, thereby being able to satisfy the thinning and more of the interposer. The need for multiple signal pins reduces unnecessary processing timing while improving the yield and cost of the semiconductor device.

According to the booming development of the electronics industry, electronic products tend to be light, thin, and short. Therefore, the semiconductor devices used in their applications are gradually becoming more and more high-performance, high-function, and high-speed research and development, and thus semiconductors. The semiconductor wafer on the device is continuously miniaturized. Usually, the most direct method of miniaturization of semiconductor wafers relies on the advancement of lithography. However, lithography has gradually approached its physical limit, so the solution has to be shifted from horizontal to vertical. In addition, multi-function electronic products such as mobile phones. It is composed of various key modules. Therefore, in terms of product design, it is necessary not only to improve the single component, but also to consider the heterogeneous integration of components and the overall performance, so that there is a three-dimensional semiconductor device (3D IC). development of.

At the same time, as the circuit pattern of the semiconductor wafer is reduced to a size of several tens of nanometers, the fabricated die integrates more computing functions and a larger number of transistor components, resulting in the number of signal pins (I/O). Also eagerly multiplying, and also The traditional die packaging technology encounters extremely severe challenges.

The ideal 3D IC, each module will be packaged in a stacked type, the vertical connection can also reduce the length of the conduction channel, which increases the efficiency. This process tests the process technology and the heterogeneous integration between components. On the road to 3D ICs, there is also the development of 2.5D ICs in the current transition period, regardless of the development of 3D ICs or 2.5D ICs, mainly through an interposer to connect printed circuit boards or The electrical signal between the package substrate and the semiconductor wafer. This interposer acts as a channel connecting the nanometer and millimeter worlds and increases the packing density of the product. Common interposers are such as Si Interposer and Glass Interposer. ) and organic interposer (Organic Interposer) and the like.

The structure of the interposer is formed by forming a perforation on a pre-formed substrate (矽, glass, organic layer, ...), such as Through-Silicon Via (TSV), Through-Glass Via (TGV), or organic a through-hole via (TOV), and a redistribution layer (RDL) disposed on the perforated substrate, such that the bottom end of the substrate is covered by a conductive pad with a larger pitch a solder pad, and the uppermost layer of the circuit redistribution layer has an electrode pad for electrically connecting the signal pins (I/O pins) of the semiconductor wafer with a small pitch by solder bumps, thereby forming an encapsulant, The package substrate can be combined with a semiconductor crystal device having a high wiring density electrical connection pad to achieve the purpose of integrating a high wiring density semiconductor wafer. Such a structure is widely used in the industry, such as the invention patents No. 093132237, No. 099143617, and Chinese invention patents No. 200910130333.5 and 201210592167.2.

The structure of the existing interposer structure is as shown in the first figure, taking the structure of the interposer (100) of the perforation as an example, which is based on a pre-formed wafer base. A hole (102) is formed on the plate (101) by a drilling technique such as etching or laser, for filling a conductive material to form a conductive path (103), and the wafer substrate (101) is adhered to a carrier plate (200). The wafer substrate (101) is thinned by a chemical mechanical polishing method, and then the wafer substrate (101) and the carrier (200) are separated after forming the wiring redistribution layer (105) and the electrode via (106). And forming an interposer (100).

Due to the influence of the miniaturization of the semiconductor wafer and the increase in the number of contacts, the future demand for the interposer in the industry includes the thinner the better, the higher the density of the pins (the smaller the Pitch, the better), and the finer the wires, the better. (Line/Space is as small as possible). Since the existing interposer structure needs to be drilled on the pre-formed wafer substrate, the difficulty is higher, and the hole diameter, the hole pitch and the hole position precision and the hole shape are completed. Sex is faced with great challenges. Furthermore, the existing drilling process may cause structural damage and cracks of the wafer substrate, and the wafer substrate may be broken by heating or pressurization in a subsequent process, resulting in an increase in the defect rate. Furthermore, in order to make the wafer substrate having a thickness of about 600 to 700 μm satisfy the thickness requirement of the interposer structure of the semiconductor device, the back surface of the wafer substrate is polished by chemical mechanical polishing to reduce the thickness thereof. Up to 25~200 microns, it takes a long time to remove a wafer substrate of a considerable thickness; and it may also cause defects in the wafer substrate after polishing, which may cause partial or overall thickness unevenness, or Problems such as damage to the edge of the wafer cause a decrease in the yield rate of the product. In addition, since the pre-formed wafer substrate is warped and thinned, warpage occurs. Therefore, it is relatively difficult to process the thinned wafer substrate in the future, and the probability of wafer substrate fragmentation increases. .

Although the current interposer will use Temporary Bonding technology before thinning and polishing, through the adhesive (such as UV Tape, UV light) The cured film, the UV-curable liquid adhesive, or the electrostatic adsorption method, the wafer substrate is attached to the carrier and processed, so that the wafer substrate can be supported by the carrier to provide sufficient support. Even so, if the thickness of the wafer substrate after polishing is too thin, it is still easy to break in subsequent dissociation or process. Moreover, since the adhesive used can withstand only a temperature of about 200 degrees Celsius, it cannot be processed in a high temperature furnace tube, and a high temperature tempering process cannot be performed. In addition, the wafer substrate and the carrier which are adhered to each other are not integrally formed, and bursting is likely to occur in a high temperature environment, and the subsequent flip chip bonding process is likely to become difficult.

It can be seen that the above-mentioned conventional interposer using the pre-formed substrate is obviously inconvenient and defective in terms of manufacturing, structure and use, and further improvement in structure is required. In view of this, the creator is in-depth discussion on the problems faced by the existing intermediaries in the structure, and through years of experience in research and development and manufacturing of related industries, through continuous efforts to improve and test, finally succeeded in developing a non-use The substrate-free interposer of the pre-molded substrate and the semiconductor device to which the substrate is applied can effectively solve the inconvenience and trouble caused by the use of the perforated substrate.

Therefore, the main purpose of the present invention is to provide a substrate-free interposer, so that it is not necessary to use a pre-formed substrate, and it is not necessary to use a substrate drilling and substrate thinning process as in the fabrication of the existing interposer, so that not only The conductive channels of the interposer are made finer and the number and density of the pins are greatly increased.

Moreover, another main purpose of the present invention is to provide a substrateless interposer which can directly control the thickness of the interposer to meet the manufacturer's requirements for the thickness of the interposer and avoid the occurrence of thinning and thinning processes such as the intermediate interposer. Crack marks in the The concentration is concentrated, and the intermediate layer is damaged by the pressurization or heating in the subsequent processing, which can effectively improve the overall yield.

In addition, another main object of the present invention is to provide a semiconductor device using a substrateless interposer, which can increase the number and density of pins, and further improve the high performance, high function, and high speed of the semiconductor device.

Based on this, the present invention mainly achieves the foregoing objects and effects through the following technical means, which are formed by a plurality of connected conductive paths formed in a non-conductive layer formed by a deposition or coating technique, each of which is formed. The two ends are exposed by the upper and lower surfaces of the non-conductive layer, and each of the conductive paths forms a conductive pad on a surface of the non-conductive layer; and the surface of the non-conductive layer has one or more layers stacked on each other. a layer, each of the circuit redistribution layers may be electrically connected to an adjacent conductive path or a line redistribution layer; further, wherein the outermost layer of the non-conductive layer has a plurality of electrode paths formed on the redistribution layer, each of which The electrode vias are electrically connected to adjacent circuit redistribution layers, and each of the electrode vias forms an electrode pad on the surface of the adjacent circuit redistribution layer.

Therefore, through the realization of the above specific technical means, the substrateless interposer provided by the present invention can make the conductive channel more precise and finer, and greatly increase the number and density of the pins, so as not to cause drilling or the like. Thinning processing increases the workmanship, and can increase the production speed of the interposer, and can avoid structural damage and cracks caused by drilling or thinning of the interposer, which can effectively improve the yield and make the subsequent process more It can adapt to the environment of pressurization and heating, and can meet the different product requirements of manufacturers.

In order to enable the review board to further understand the composition, characteristics and purpose of the creation, the following is a preferred embodiment of the creation, and the detailed description of the creation is as follows, and at the same time, those skilled in the art can follow the instructions. Specific implementation.

(10) ‧‧‧No substrate interposer

(30)‧‧‧Electrical path

(31)‧‧‧Electrical mat

(32) ‧ ‧ inner conductor

(40)‧‧‧ Non-conductive layer

(50) ‧‧‧Line redistribution

(51)‧‧‧Wire pattern

(52) ‧‧‧Dielectric layer

(53) ‧‧‧ gap

(60) ‧‧‧electrode channel

(61)‧‧‧electrode pads

(80)‧‧‧Printed circuit boards

(81)‧‧‧Flip solder pads

(85)‧‧‧Metal solder balls

(90)‧‧‧Semiconductor wafer

(91)‧‧‧Signal pins

(95)‧‧‧Metal solder balls

(500)‧‧‧ semiconductor devices

(501)‧‧‧Package

(505)‧‧‧Metal solder balls

(A) ‧‧‧ Carrier Board

(B) ‧‧‧buffer layer

(100) ‧‧‧Intermediary

(101)‧‧‧ Wafer Substrate

(102)‧‧‧Perforation

(103)‧‧‧ conductive channels

(105) ‧‧‧Line redistribution

(106)‧‧‧Electrode pathway

(200)‧‧‧ Carrier Board

First figure: Schematic diagram of the cross-sectional structure of the existing interposer structure during the forming process.

The second figure is a schematic diagram of the cross-sectional structure of the substrate-free interposer in this creation, illustrating its composition and its relative relationship.

The third to fifth figures are schematic diagrams of the cross-sectional structure of the substrate-free interposer in the manufacturing process.

Fig. 6 is a schematic cross-sectional view showing another embodiment of the present substrateless substrate.

Figure 7 is a schematic cross-sectional view of a semiconductor device using the substrateless interposer.

Figure 8 is a cross-sectional structural view showing still another embodiment of the semiconductor device without the substrate interposer.

The present invention is a substrateless interposer and a semiconductor device for use thereof, and the specific embodiments of the present invention and its components are illustrated with reference to the accompanying drawings, all of which relate to front and rear, left and right, top and bottom, upper and lower, and horizontal. The reference to the vertical is for convenience of description only, and does not limit the creation, nor restricts its components to any position or spatial orientation. The dimensions specified in the schema and the manual, when not available Within the scope of the patent application of the present invention, changes are made in accordance with the design and needs of the specific embodiments of the present invention.

In the structure of the present invention, as disclosed in the second and sixth figures, the substrate-free interposer (10, 10A) having no substrate such as a wafer, glass or organic layer is deposited or coated. The non-conductive layer (40) formed by the technology has a plurality of conductive vias (30) connected to the upper and lower surfaces, and the surface of the non-conductive layer (40) has at least one line redistribution layer (50), each of the lines The redistribution layer (50) has at least one wire pattern (51), and wherein the outermost layer redistribution layer (50) different from the non-conductive layer (40) is formed with a plurality of electrode vias (60), each of the electrode vias ( 60) and electrically connecting the conductive pattern (30) of the non-conductive layer (40) through the wire pattern (51) of the line redistribution layer (50), so that the substrate-free interposer (10) can be electrically non-conductive The conductive path (30) of the layer (40) is electrically coupled to the package substrate of the larger pitch or the flip chip (81) of the printed circuit board (80), and electrically connected to the semiconductor having a small pitch through the electrode via (60). The signal pin (91) of the chip (90) is further formed into a semiconductor crystal device (500) through the encapsulant [as shown in the seventh and eighth figures]; as shown in the present invention, there is no substrate. The detailed configuration of one of the preferred embodiments is as shown in the third to fifth figures. First, a light-transmissive carrier (A) that can be selectively dissociated from the non-conductive layer (40) of the present invention is prepared in advance. The surface of the transparent carrier (A) is adapted to form a buffer layer (B). In a preferred embodiment of the present invention, the transparent carrier (A) may be quartz glass, borosilicate glass or sodium strontium. Made up of glass or sapphire glass. In some embodiments of the present invention, the material of the buffer layer (B) may be a ceramic optical film, a metal film, or a non-metal film that can be dissociated by laser; As shown in the third figure, a plurality of conductive paths (30) are formed on the surface of the buffer layer (B) of the transparent carrier (A), and each of the conductive paths (30) has a conductive pad (31) and a wire (32) formed on the upper surface of the conductive pad (31), and using a deposition, coating technique on the surface of the buffer layer (B) of the transparent carrier (A) and between adjacent conductive paths (30) Solidifying to form the non-conductive layer (40), and exposing the top and bottom end surfaces of the conductive via (30) to the upper and lower surfaces of the non-conductive layer (40), so that each of the conductive vias (30) can communicate with the non-conductive layer (40) Upper and lower surfaces. In some embodiments, the material of the non-conductive layer (40) and related processes may be varied according to the needs of the manufacturer. For example, a dielectric material, an insulating material, or a semiconductor material may be selected to form the non-conductive layer (40). In some embodiments, the non-conductive layer (40) can be deposited from a tantalum material. In another embodiment, the non-conductive layer (40) can be coated from a glass material. In another embodiment, the non-conductive layer (40) may be coated with an organic material; and, as shown in the fourth figure, a non-conductive layer is used by a technique of a redistribution layer (RDL). Forming one or more stacked circuit redistribution layers (50), each of the circuit redistribution layers (50) comprising a wire pattern (51) electrically connected to the conductive vias (30) and a cover pattern (51) And a dielectric layer (52) on the surface of the non-conductive layer (40), the process dielectric layer (52) has a plurality of inner notches (53) exposed to the partial conductor pattern (51), and the power supply links the adjacent lines. The redistribution layer (50) wire pattern (51) or the aforementioned electrode channel (60) [shown in Figures 4 and 5]. The dielectric layer (52) of the line redistribution layer (50) closest to the electrode channel (60) may be a dielectric protective material. In some embodiments, a three-layer line redistribution layer (50) can be stacked on the non-conductive layer (40) [as shown in the second figure]. In addition, in some embodiments, the non-conductive layer (40) can be stacked A layer of circuit redistribution layer (50) is formed, and an electrode via (60) is formed directly on the circuit redistribution layer (50) [as shown in the sixth figure]. In particular, the number of line redistribution layers (50) described above can be adjusted as needed. A plurality of circuit redistribution layers (50) may be formed with different package specifications; further, as shown in the fifth figure, the electrode channels (60) formed on the surface of the uppermost circuit redistribution layer (50) are plural The electrode pad (61) of the part of the wire pattern (51) is electrically connected to the notch (53) in the line redistribution layer (50). Finally, according to the material of the buffer layer (B), the corresponding dissociation technology is selected, for example, the buffer layer (B) is dissipated by laser irradiation, so that the carrier (A) can be combined with the non-conductive layer (40) and the conductive path (30). The lower surface of the conductive pad (31) is separated to form a substrateless interposer (10, 10A) [second and sixth figures].

Furthermore, as shown in the seventh figure, the substrateless interposer (10) of the present invention can be applied to the package structure (501) of a subsequent semiconductor device (500), the substrate without the semiconductor device (500). The electrode pads (61) of the electrode channels (60) of the interposer (10) can be electrically coupled to the signal pins (91) of the semiconductor wafers (90) having a smaller pitch by a plurality of metal solder balls (95), respectively. In some embodiments, the semiconductor device (500) can further electrically couple the conductive pads (31) of the conductive vias (30) of the substrateless interposer (10) to the pitch by a plurality of metal solder balls (85). On the overlying solder pad (81) of the larger package substrate (80). The purpose of integrating semiconductor wafers with high wiring density is achieved.

Moreover, as shown in the eighth figure, in some embodiments, the package structure (505) of the semiconductor device (500) may further be an electrode pad of the electrode channel (60) of the substrate interposer (10). (61) The substrateless interposer (10A) can be electrically coupled to at least one upper layer by a plurality of metal solder balls (505), respectively. The layer (10) and the substrateless interposer (10A) of each of the upper layers can be layer-by-layer electrically combined with semiconductor wafers (90, 90A) of different functions for further integration of semiconductor wafers having a high wiring density.

In summary, the substrate-free interposer provided by the present invention can make the conductive channel more precise and finer, and greatly increase the number and density of the pins, without increasing the drilling or thinning process as in the conventional method. Working hours can improve the production speed of the interposer and avoid structural damage caused by drilling or thinning processing, which can effectively improve the yield and meet the thickness requirements of the manufacturer, thus effectively increasing the added value of the product. To effectively improve its economic efficiency.

In summary, it can be understood that this creation is a creative and excellent new creation. In addition to effectively solving the problems faced by the practitioners, the effect is greatly enhanced, and the same or similar product creation is not seen in the same technical field. Or public use, and at the same time have an improvement in efficacy, so this creation has met the requirements of "newness" and "progressiveness" of the new patent, and is applying for a new type of patent according to law.

(10) ‧‧‧No substrate interposer

(30)‧‧‧Electrical path

(31)‧‧‧Electrical mat

(32) ‧ ‧ inner conductor

(40)‧‧‧ Non-conductive layer

(50) ‧‧‧Line redistribution

(51)‧‧‧Wire pattern

(52) ‧‧‧Dielectric layer

(60) ‧‧‧electrode channel

(61)‧‧‧electrode pads

Claims (9)

A substrate-free interposer is formed in a non-conductive layer formed by a technique of deposition or coating, and a plurality of connected conductive paths are formed, and both ends of the conductive path are exposed by upper and lower surfaces of the non-conductive layer, and Each of the conductive paths is formed with a conductive pad on a surface of one side of the non-conductive layer; and one side of the surface of the non-conductive layer has one or more layer redistribution layers stacked on each other, and each of the circuit redistribution layers can be adjacent to the conductive path or The circuit redistribution layer is electrically connected; further, wherein the outermost layer of the non-conductive layer is formed with a plurality of electrode vias on the redistribution layer, and each of the electrode vias is electrically connected to the adjacent circuit redistribution layer. And each of the electrode paths forms an electrode pad on the surface of the adjacent circuit redistribution layer. The substrate-free interposer of claim 1, wherein the non-conductive layer is selected from a dielectric material, an insulating material, or a semiconductor material. The substrate-free interposer of claim 1, wherein the non-conductive layer can be deposited from a tantalum material. The substrate-free interposer of claim 1, wherein the non-conductive layer is coated with a glass material. The substrate-free interposer of claim 1, wherein the non-conductive layer is coated with an organic material. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically bond at least one semiconductor wafer and simultaneously form in a package structure. The semiconductor package The conductive path of the substrateless interposer can be selectively electrically coupled to a printed circuit board. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically bond at least one semiconductor wafer, and the conductive via of the substrateless interposer can be electrically The device is bonded to a package substrate and simultaneously formed in a package structure, so that the semiconductor device can be selectively electrically coupled to a printed circuit board by using the package substrate. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically combine at least one semiconductor wafer and at least one upper substrateless interposer, wherein The electrode via substrate of the upper substrate can be electrically coupled to another semiconductor wafer and simultaneously formed in a package structure, so that the semiconductor device can be selectively electrically coupled to the conductive via of the underlying substrate-free interposer. On a printed circuit board. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically combine at least one semiconductor wafer and at least one upper substrateless interposer, wherein The electrode vias of the upper substrate-free interposer can be electrically coupled to another semiconductor wafer, and the conductive vias of the underlying substrate-free interposer can be electrically coupled to a package substrate and simultaneously formed in a package structure. The semiconductor device can be selectively electrically coupled to a printed circuit board by using the package substrate.