TW201739011A - Substrate-free intermediate layer and semiconductor device using the same forming a plurality of conductive paths communicating with an upper surface and a lower surface in an insulated isolation layer - Google Patents

Abstract

This invention relates to a substrate-free intermediate layer and a semiconductor device using the same, and particularly relates to a substrate-free intermediate layer which does not adapt substrates such as wafers, glass, organic layers which are formed in advance. A plurality of conductive paths communicating with an upper surface and a lower surface are formed in an insulated isolation layer solidified and formed by technologies such as deposition or coating, and the surface of one side of the insulated isolation layer is provided with at least one circuit redistribution layer; each of the circuit redistribution layers is provided with a dielectric layer and a plurality of conducting wire patterns. Furthermore, a plurality of electrode channels electrically connected with parts of conducting wire patterns are formed on the circuit redistribution layer on the outmost layer different from the insulated isolation layer. Therefore, the thickness of the insulated isolation layer can be effectively controlled; in addition, the conductive paths are made more precise and more micronized, the amount and density of connecting pins are greatly increased, the intermediate layer can be reduced to be suitable for the subsequent heating and pressurizing processes, and furthermore, not only can the production speed and yield of the intermediate layer be increased effectively, but also the intermediate layer can better meet the requirement of a subsequent packaging process.

Description

Substrate without interposer and application of semiconductor device

The invention belongs to the technical field of interposer of a semiconductor device, and specifically relates to a substrate-free interposer structure without using a pre-formed wafer, glass or organic layer substrate, thereby being able to satisfy the thinning and more of the interposer. The need for multiple signal pins reduces unnecessary processing timing while improving the yield and cost of the semiconductor device.

According to the booming development of the electronics industry, electronic products tend to be light, thin, and short. Therefore, the semiconductor devices used in their applications are gradually becoming more and more high-performance, high-function, and high-speed research and development, and thus semiconductors. The semiconductor wafer on the device is continuously miniaturized. Usually, the most direct method of miniaturization of semiconductor wafers relies on the advancement of lithography. However, lithography has gradually approached its physical limit, so the solution has to be shifted from horizontal to vertical. In addition, multi-function electronic products such as mobile phones. It is composed of various key modules. Therefore, in terms of product design, it is necessary not only to improve the single component, but also to consider the heterogeneous integration of components and the overall performance, so that there is a three-dimensional semiconductor device (3D IC). development of.

At the same time, as the circuit pattern of the semiconductor wafer is reduced to a size of several tens of nanometers, the fabricated die integrates more computing functions and a larger number of transistor components, resulting in the number of signal pins (I/O). It is also eager to multiply, and the traditional chip packaging technology has encountered extremely severe challenges.

The ideal 3D IC, each module will be packaged in a stacked type, the vertical connection can also reduce the length of the conduction channel, which increases the efficiency. This process tests the process technology and the heterogeneous integration between components. On the road to 3D ICs, there is also the development of 2.5D ICs in the current transition period, regardless of the development of 3D ICs or 2.5D ICs, mainly through an interposer to connect printed circuit boards or The electrical signal between the package substrate and the semiconductor wafer. This interposer acts as a channel connecting the nanometer and millimeter worlds and increases the packing density of the product. Common interposers are such as Si Interposer and Glass Interposer. ) and organic interposer (Organic Interposer) and the like.

The structure of the interposer is formed by forming a perforation on a pre-formed substrate (矽, glass, organic layer, ...), such as Through-Silicon Via (TSV), Through-Glass Via (TGV), or organic a through-hole via (TOV), and a redistribution layer (RDL) disposed on the perforated substrate, such that the bottom end of the substrate is covered by a conductive pad with a larger pitch a solder pad, and the uppermost layer of the circuit redistribution layer has an electrode pad for electrically connecting the signal pins (I/O pins) of the semiconductor wafer with a small pitch by solder bumps, thereby forming an encapsulant, The package substrate can be combined with a semiconductor crystal device having a high wiring density electrical connection pad to achieve the purpose of integrating a high wiring density semiconductor wafer. Such a structure is widely used in the industry, such as the invention patents No. 093132237, No. 099143617, and Chinese invention patents No. 200910130333.5 and 201210592167.2.

The structure of the existing interposer structure is as shown in the first figure, taking the structure of the interposer (100) of the perforated hole as an example, which is attached to a pre-formed wafer substrate (101) for etching or laser irradiation, etc. Drilling technique to form perforations (102) for filling The conductive material forms a conductive path (103), and the wafer substrate (101) is adhered to a carrier (200) for thinning the wafer substrate (101) by chemical mechanical polishing, and then redistributing the line After the layer (105) and the electrode via (106), the wafer substrate (101) and the carrier (200) are dissociated to form an interposer (100).

Due to the influence of the miniaturization of the semiconductor wafer and the increase in the number of contacts, the future demand for the interposer in the industry includes the thinner the better, the higher the density of the pins (the smaller the Pitch, the better), and the finer the wires, the better. (Line/Space is as small as possible). Since the existing interposer structure needs to be drilled on the pre-formed wafer substrate, the difficulty is higher, and the hole diameter, the hole pitch and the hole position precision and the hole shape are completed. Sex is faced with great challenges. Furthermore, the existing drilling process may cause structural damage and cracks of the wafer substrate, and the wafer substrate may be broken by heating or pressurization in a subsequent process, resulting in an increase in the defect rate. Furthermore, in order to make the wafer substrate having a thickness of about 600 to 700 μm satisfy the thickness requirement of the interposer structure of the semiconductor device, the back surface of the wafer substrate is polished by chemical mechanical polishing to reduce the thickness thereof. Up to 25~200 microns, it takes a long time to remove a wafer substrate of a considerable thickness; and it may also cause defects in the wafer substrate after polishing, which may cause partial or overall thickness unevenness, or Problems such as damage to the edge of the wafer cause a decrease in the yield rate of the product. In addition, since the pre-formed wafer substrate is warped and thinned, warpage occurs. Therefore, it is relatively difficult to process the thinned wafer substrate in the future, and the probability of wafer substrate fragmentation increases. .

Although the current interposer will use Temporary Bonding technology before thinning and polishing, through adhesive (such as UV Tape, UV curing film, UV curing liquid adhesive) or electrostatic adsorption. Way, crystal The circular substrate is attached to the carrier and processed, so that the wafer substrate can be supported by the carrier to provide sufficient support. Even so, if the thickness of the wafer substrate after polishing is too thin, it is still easy to break in subsequent dissociation or process. Moreover, since the adhesive used can withstand only a temperature of about 200 degrees Celsius, it cannot be processed in a high temperature furnace tube, and a high temperature tempering process cannot be performed. In addition, the wafer substrate and the carrier which are adhered to each other are not integrally formed, and bursting is likely to occur in a high temperature environment, and the subsequent flip chip bonding process is likely to become difficult.

It can be seen that the above-mentioned conventional interposer using the pre-formed substrate is obviously inconvenient and defective in terms of manufacturing, structure and use, and further improvement in structure is required. In view of this, the inventors have in-depth discussion on the problems faced by the existing intermediaries in the structure, and through years of experience in research and development and manufacturing of related industries, through continuous efforts to improve and test, finally succeeded in developing a non-use The substrate-free interposer of the pre-molded substrate and the semiconductor device to which the substrate is applied can effectively solve the inconvenience and trouble caused by the use of the perforated substrate.

Therefore, the main object of the present invention is to provide a substrate-free interposer, so that it is not necessary to use a pre-formed substrate, and it is not necessary to use a substrate drilling method and a substrate thinning process as in the fabrication of the existing interposer, so that not only The conductive channels of the interposer are made finer and the number and density of the pins are greatly increased.

In addition, another main object of the present invention is to provide a substrate-free interposer which can directly control the thickness of the interposer, meet the manufacturer's requirements for the thickness of the interposer, and avoid the occurrence of problems such as drilling and thinning of the intermediate interposer. Cracks or stress concentrations in the middle layer, causing the interposer to break due to pressurization or warming in subsequent processing, Can effectively improve the overall yield.

Further, another main object of the present invention is to provide a semiconductor device using a substrateless interposer, which can increase the number and density of pins, and further improve the high performance, high function, and high speed of the semiconductor device.

Based on the above, the present invention mainly achieves the foregoing objects and effects through the following technical means, which are formed by a plurality of connected conductive paths formed in an insulating isolation layer formed by a deposition or coating technique, and the conductive paths are respectively formed. The two ends are exposed by the upper and lower surfaces of the insulating isolation layer, and each of the conductive paths forms a conductive pad on one surface of the insulating isolation layer; and one side of the insulating isolation layer has one or more layers stacked on each other. In the cloth layer, each of the circuit redistribution layers can be electrically connected to the adjacent conductive path or the circuit redistribution layer; further, a plurality of electrode paths are formed on the outermost layer redistribution layer different from the insulating isolation layer, and each The electrode vias are electrically connected to adjacent circuit redistribution layers, and each of the electrode vias forms an electrode pad on a surface of the adjacent circuit redistribution layer.

Therefore, through the implementation of the above specific technical means, the substrate-free interposer provided by the invention can make the conductive channel more precise and finer, and greatly increase the number and density of the pins, so as to avoid drilling or the like. Thinning processing increases the workmanship, and can increase the production speed of the interposer, and can avoid structural damage and cracks caused by drilling or thinning of the interposer, which can effectively improve the yield and make the subsequent process more It can adapt to the environment of pressurization and heating, and can meet the different product requirements of manufacturers.

In order to enable your review board to further understand the composition of the present invention, The following is a description of the preferred embodiments of the present invention, and the detailed description of the embodiments of the present invention, as well as those skilled in the art.

(10) ‧‧‧No substrate interposer

(30)‧‧‧Electrical path

(31)‧‧‧Electrical mat

(32) ‧ ‧ inner conductor

(40) ‧‧‧Insulation barrier

(50) ‧‧‧Line redistribution

(51)‧‧‧Wire pattern

(52) ‧‧‧Dielectric layer

(53) ‧‧‧ gap

(60) ‧‧‧electrode channel

(61)‧‧‧electrode pads

(80)‧‧‧Printed circuit boards

(81)‧‧‧Flip solder pads

(85)‧‧‧Electrical connectors

(90)‧‧‧Semiconductor wafer

(91)‧‧‧Signal pins

(95)‧‧‧Electrical connectors

(500)‧‧‧ semiconductor devices

(501)‧‧‧Package

(505)‧‧‧Electrical connectors

(A) ‧‧‧ Carrier Board

(B) ‧‧‧buffer layer

(100) ‧‧‧Intermediary

(101)‧‧‧ Wafer Substrate

(102)‧‧‧Perforation

(103)‧‧‧ conductive channels

(105) ‧‧‧Line redistribution

(106)‧‧‧Electrode pathway

(200)‧‧‧ Carrier Board

First figure: Schematic diagram of the cross-sectional structure of the existing interposer structure during the forming process.

The second figure is a schematic cross-sectional structure of the substrate-free interposer of the present invention for explaining its constituent forms and their relative relationships.

The third to fifth figures are schematic cross-sectional structures of the substrate-free interposer of the present invention in the manufacturing process.

Figure 6 is a schematic cross-sectional view showing another embodiment of the substrate-free interposer of the present invention.

Figure 7 is a schematic cross-sectional view showing a semiconductor device to which the substrate-free interposer of the present invention is applied.

Figure 8 is a cross-sectional structural view showing still another embodiment of a semiconductor device without a substrate interposer of the present invention.

The present invention is a substrate-free interposer and a semiconductor device for use thereof. The technical content of the present invention will be described in the following specific embodiments, so that those skilled in the art can easily understand the advantages of the present invention by the contents disclosed in the present specification. And efficacy. The invention may be embodied or applied by other different embodiments. Therefore, with reference to the specific embodiments of the invention and the components thereof, all of the front and rear, left and right, top and bottom, upper and lower, and horizontal and vertical references are for convenience of description and are not limiting. The present invention is also not Its components are limited to any position or space orientation. The drawings and the dimensions specified in the specification may be varied in accordance with the design and needs of the specific embodiments of the present invention without departing from the scope of the invention.

For the structure of the present invention, as disclosed in the second and sixth figures, the substrate-free interposer (10, 10A) having no substrate such as a wafer, glass or organic layer is deposited or coated. The insulating isolation layer (40) formed by the technology has a plurality of conductive vias (30) connected to the upper and lower surfaces, and the insulating isolation layer (40) has at least one wiring redistribution layer (50) on each side surface thereof. The circuit redistribution layer (50) has at least one wire pattern (51), and wherein the outermost layer redistribution layer (50) different from the insulating isolation layer (40) is formed with a plurality of electrode vias (60), each of the electrode vias (60) and electrically connecting the conductive pattern (30) of the insulating spacer layer (40) through the wiring pattern (51) of the wiring redistribution layer (50), so that the substrateless intermediate layer (10) can be insulated by The conductive path (30) of the isolation layer (40) is electrically coupled to the package substrate or the printed circuit board (80) having a large pitch or the flip chip (81) of the package substrate, and electrically connected to the electrode via (60). a signal pin (91) of the smaller semiconductor chip (90), and then through the encapsulant to form a semiconductor crystal device (500) [as shown in Figures 7 and 8]; As for the substrate-free interposer of the present invention, the detailed configuration of a preferred embodiment is as shown in the third to fifth figures. First, a light-transmitting which can be selectively dissociated from the insulating spacer (40) of the present invention is prepared in advance. a carrier (A), the surface of the transparent carrier (A) is adapted to form a buffer layer (B). In a preferred embodiment of the invention, the transparent carrier (A) may be quartz glass, Boron bismuth glass, sodium bismuth glass or sapphire glass. In some embodiments of the present invention, the material of the buffer layer (B) may be a ceramic optical film, a metal film, or a non-metal thin that can be dissociated by laser. The film is formed; as shown in the third figure, a plurality of conductive paths (30) are formed on the surface of the buffer layer (B) of the transparent carrier (A), and each of the conductive paths (30) has a conductive pad (31) and a wire (32) formed on the upper surface of the conductive pad (31), and using a deposition and coating technique on the surface of the buffer layer (B) of the transparent carrier (A) and adjacent conductive paths (30) solidifying to form the insulating isolation layer (40), and exposing the top and bottom end surfaces of the conductive via (30) to the upper and lower surfaces of the insulating isolation layer (40), so that the conductive paths (30) can be insulated and insulated. The upper and lower surfaces of the isolation layer (40). In some embodiments, the material of the insulating isolation layer (40) and related processes may be varied according to the needs of the manufacturer, for example, a dielectric material (Dielectric), a passivation material, or a photosensitive insulation. An insulating spacer (40) is formed of a semiconductor material such as a photosensitive Isolation polymer. In some embodiments, the insulating isolation layer (40) can be deposited from a tantalum material. In another embodiment, the insulating spacer layer (40) may be coated with a glass material. In another embodiment, the insulating isolation layer (40) may be coated with an organic material; and, as shown in the fourth figure, the technology of the RDL (redistribution layer) is applied to the insulating isolation layer ( 40) forming one or more stacked circuit redistribution layers (50), each of the circuit redistribution layers (50) comprising a wire pattern (51) electrically connected to the conductive path (30) and a wire pattern covering the wire ( 51) and a dielectric layer (52) on the surface of the insulating spacer (40), the process dielectric layer (52) has a plurality of inner notches (53) exposed to the partial conductor pattern (51), and the power supply is connected adjacent to The line redistribution layer (50) wire pattern (51) or the aforementioned electrode channel (60) [shown in Figures 4 and 5]. Which is the closest to the electrode channel (60 The dielectric layer (52) of the circuit redistribution layer (50) may be a dielectric protective material such as Dielectric, Passivation Material or Photosensitive Isolation Polymer. ) semiconductor materials. In some embodiments, three layers of line redistribution layers (50) may be stacked on the insulating isolation layer (40) [as shown in the second figure]. In some embodiments, a layer of circuit redistribution layer (50) may be stacked on the insulating isolation layer (40), and an electrode via (60) may be formed directly on the circuit redistribution layer (50). The picture shows]. In particular, the number of line redistribution layers (50) described above can be adjusted as needed. A plurality of circuit redistribution layers (50) may be formed with different package specifications; further, as shown in the fifth figure, the electrode channels (60) formed on the surface of the uppermost circuit redistribution layer (50) are plural The electrode pad (61) of the part of the wire pattern (51) is electrically connected to the notch (53) in the line redistribution layer (50). Finally, according to the material of the buffer layer (B), the corresponding dissociation technology is selected, for example, the buffer layer (B) is dissipated by laser irradiation, so that the carrier (A) can be insulated from the insulating layer (40) and the conductive path (30). The lower surface of the conductive pad (31) is separated to form a substrateless interposer (10, 10A) [second and sixth figures].

Furthermore, referring to the seventh figure, the substrateless interposer (10) of the present invention can be applied to the package structure (501) of a subsequent semiconductor device (500), the substrate without the semiconductor device (500). The electrode pads (61) of the electrode channels (60) of the interposer (10) can be electrically coupled to the signal pins (91) of the semiconductor wafers (90) having a small pitch by a plurality of electrical connectors (95), respectively. The electrical connector (95) may be a conductive material such as a solder ball, a copper pillar, or a gold pillar. In some embodiments, the semiconductor device (500) can further have a substrateless interposer (10) The conductive pads (31) of the conductive vias (30) are electrically coupled to the printed circuit board (80) having a larger pitch or the flip chip (81) of the package substrate by a plurality of electrical connectors (85), respectively. The isoelectric connector (85) may be a conductive material such as a solder ball, a copper column, or a gold pillar. The purpose of integrating semiconductor wafers with high wiring density is achieved.

Moreover, as shown in the eighth figure, in some embodiments, the package structure (505) of the semiconductor device (500) may further be an electrode pad of the electrode channel (60) of the substrate interposer (10). (61) The substrate-less interposer (10A) of at least one upper layer may be electrically coupled to each other by a plurality of electrical connectors (505), and the electrical connectors (505) may be solder balls, copper pillars, gold pillars, etc. a conductive material for allowing the substrateless interposer (10) and each of the upper substrateless interposer (10A) to be layered and electrically combined with different functions of the semiconductor wafer (90, 90A) for further integration of high wiring density Semiconductor wafer. Moreover, in some embodiments, the semiconductor device (500) has an IC carrier (IC carrier) for electrically connecting to the printed circuit board through the IC carrier.

In summary, the substrate-free interposer provided by the invention can make the conductive channel more precise and finer, and greatly increase the number and density of the pins, without increasing the drilling or thinning process as in the conventional method. Working hours can improve the production speed of the interposer and avoid structural damage caused by drilling or thinning processing, which can effectively improve the yield and meet the thickness requirements of the manufacturer, thus effectively increasing the added value of the product. To effectively improve its economic efficiency.

In this way, it can be understood that the present invention is an excellent creation, in addition to effectively solving the problems faced by the practitioners, and greatly improving the efficiency, and the same or similar product creation or public use is not seen in the same technical field. At the same time, it has an improvement in efficacy, so the invention has met the "novelty" and "progressiveness" of the invention patent. The requirement is to apply for an invention patent in accordance with the law.

(10) ‧‧‧No substrate interposer

(30)‧‧‧Electrical path

(31)‧‧‧Electrical mat

(32) ‧ ‧ inner conductor

(40) ‧‧‧Insulation barrier

(50) ‧‧‧Line redistribution

(51)‧‧‧Wire pattern

(52) ‧‧‧Dielectric layer

(60) ‧‧‧electrode channel

(61)‧‧‧electrode pads

Claims (9)

A substrate-free interposer is formed in a plurality of interconnected conductive vias formed in a dielectric isolation layer formed by a deposition or coating technique, and both ends of the conductive vias are exposed by upper and lower surfaces of the insulating spacer layer, and Each of the conductive vias has a conductive pad formed on one surface of the insulating isolation layer; and one side of the insulating isolation layer has one or more layer redistribution layers stacked on each other, and each of the circuit redistribution layers and the adjacent conductive path Or the circuit redistribution layer is electrically connected; further, wherein the outermost circuit redistribution layer different from the insulating isolation layer is formed with a plurality of electrode paths, and each of the electrode paths is electrically connected to the adjacent circuit redistribution layer And each of the electrode paths forms an electrode pad on a surface of the adjacent circuit redistribution layer. The substrate-free interposer of claim 1, wherein the insulating spacer layer is selected from the group consisting of a dielectric material, an insulating material, or a semiconductor material. The substrate-free interposer of claim 1, wherein the insulating spacer layer can be deposited from a tantalum material. The substrate-free interposer of claim 1, wherein the insulating spacer layer is coated with a glass material. The substrate-free interposer of claim 1, wherein the insulating spacer is coated with an organic material. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically bond at least one semiconductor wafer and simultaneously form in a package structure. The semiconductor package The conductive path of the substrateless interposer can be selectively electrically coupled to a printed circuit board. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically bond at least one semiconductor wafer, and the conductive via of the substrateless interposer can be electrically The device is bonded to a package substrate and simultaneously formed in a package structure, so that the semiconductor device can be selectively electrically coupled to a printed circuit board by using the package substrate. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically combine at least one semiconductor wafer and at least one upper substrateless interposer, wherein The electrode via substrate of the upper substrate can be electrically coupled to another semiconductor wafer and simultaneously formed in a package structure, so that the semiconductor device can be selectively electrically coupled to the conductive via of the underlying substrate-free interposer. On a printed circuit board. A semiconductor device having no substrate interposer according to any one of claims 1 to 5, wherein the electrode via of the substrateless interposer can electrically combine at least one semiconductor wafer and at least one upper substrateless interposer, wherein The electrode vias of the upper substrate-free interposer can be electrically coupled to another semiconductor wafer, and the conductive vias of the underlying substrate-free interposer can be electrically coupled to a package substrate and simultaneously formed in a package structure. The semiconductor device can be selectively electrically coupled to a printed circuit board by using the package substrate.