CN111554656A - Semiconductor packaging device - Google Patents

Semiconductor packaging device Download PDF

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Publication number
CN111554656A
CN111554656A CN202010367784.7A CN202010367784A CN111554656A CN 111554656 A CN111554656 A CN 111554656A CN 202010367784 A CN202010367784 A CN 202010367784A CN 111554656 A CN111554656 A CN 111554656A
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CN
China
Prior art keywords
chip
signal transmission
electrically connected
semiconductor package
packaging substrate
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Pending
Application number
CN202010367784.7A
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Chinese (zh)
Inventor
李骏
戴颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN202010367784.7A priority Critical patent/CN111554656A/en
Publication of CN111554656A publication Critical patent/CN111554656A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application discloses semiconductor package device, this semiconductor package device includes: the packaging structure comprises a packaging substrate, an electric connection structure, a connection chip, a first chip and a second chip, wherein the first chip and the second chip are arranged on one side of the packaging substrate at the same layer, functional surfaces of the first chip and the second chip face the packaging substrate, signal transmission areas on the functional surfaces of the first chip and the second chip are arranged close to each other, and the signal transmission areas are far away from the packaging substrate relative to non-signal transmission areas on the functional surfaces; the electric connection structure is positioned between the packaging substrate and the non-signal transmission area and is electrically connected with the packaging substrate and the non-signal transmission area; the connecting chip is positioned between the signal transmission areas of the first chip and the second chip and the packaging substrate, and the functional surface of the connecting chip faces the signal transmission areas and is electrically connected with the signal transmission areas. By means of the mode, the packaging cost can be reduced, and the performance of the semiconductor packaging device is improved.

Description

Semiconductor packaging device
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor package device.
Background
In a semiconductor package device packaged by the existing chip packaging technology, a chip is generally connected with a substrate through a silicon interposer, the semiconductor package device has excellent electrical performance and thermal conductivity, but the semiconductor package device has high cost, and the silicon interposer has high brittleness, so that the stability of the package device is low. Therefore, there is a need to combine the advantages of the existing packaging technology to develop a new packaging technology to form a new semiconductor package device, which can reduce the cost and has excellent performance.
Disclosure of Invention
The technical problem that this application mainly solved provides a semiconductor package device, can reduce the encapsulation cost, improves semiconductor package device's performance.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: the chip package comprises a package substrate, an electric connection structure, a connection chip, a first chip and a second chip; the first chip and the second chip are arranged on one side of the packaging substrate in the same layer, functional surfaces of the first chip and the second chip face the packaging substrate, signal transmission areas on the functional surfaces of the first chip and the second chip are arranged close to each other, and the signal transmission areas are far away from the packaging substrate relative to non-signal transmission areas on the functional surfaces; the electric connection structure is positioned between the packaging substrate and the non-signal transmission area and is electrically connected with the packaging substrate and the non-signal transmission area; and the connecting chip is positioned between the signal transmission areas of the first chip and the second chip and the packaging substrate, and the functional surface of the connecting chip faces the signal transmission areas and is electrically connected with the signal transmission areas.
Wherein the semiconductor package device further comprises: and the first conductive columns are respectively arranged on the connecting bonding pads of the functional surfaces of the connecting chip, and two ends of each first conductive column are respectively electrically connected with the signal transmission area and the connecting bonding pads.
Wherein the semiconductor package device further comprises: the first underfill covers the functional surface of the connecting chip and faces one side of the signal transmission area, and the first conductive column is located in the first underfill.
Wherein the electrical connection structure includes: the second conductive columns are respectively positioned on the bonding pads of the non-signal transmission area and are electrically connected with the bonding pads of the non-signal transmission area; and the first solder balls are respectively positioned at the end parts of the second conductive columns facing the packaging substrate, and the first solder balls, the second conductive columns and the packaging substrate are electrically connected.
Wherein the electrical connection structure includes: the first rewiring layer is positioned on the surface of the non-signal transmission area and is electrically connected with the bonding pad of the non-signal transmission area; and a plurality of second solder balls located between the first redistribution layer and the package substrate, wherein one end of each second solder ball is electrically connected with the first redistribution layer, and the other end of each second solder ball is electrically connected with the package substrate.
Wherein, the electric connection structure includes: the second rewiring layer is positioned on the surface, facing the non-signal transmission area, of the packaging substrate and is electrically connected with the packaging substrate; and a plurality of third solder balls located between the second re-wiring layer and the non-signal transmission region, one end of each third solder ball being electrically connected to the second re-wiring layer, and the other end of each third solder ball being electrically connected to the non-signal transmission region.
Wherein the semiconductor package device further comprises: and the second underfill continuously covers the side surfaces of the electric connection structure.
The first surface of the packaging substrate facing the first chip and the second chip is flat, and a gap or direct contact is formed between the non-functional surface of the connecting chip and the first surface.
Wherein, the first surface of the packaging substrate facing the first chip and the second chip is provided with a groove, and at least part of the connecting chip is positioned in the groove.
Wherein the semiconductor package device further comprises: and the plastic packaging layer continuously covers the side surfaces of the first chip and the second chip.
The beneficial effect of this application is: the application provides a semiconductor package device, its signal transmission district and the non-signal transmission district of main chip adopt different connected mode: the signal transmission area is connected with the first chip and the second chip through the connecting chip, so that the signal transmission rate between the first chip and the second chip is improved, and the performance of a packaged device is improved; the non-signal transmission area is connected with the packaging substrate through the electric connection structure, so that the packaging cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of a semiconductor package device according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application;
FIG. 3 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application;
FIG. 4 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;
FIG. 5 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;
fig. 6 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor package device 100 according to the present application, including: package substrate 10, connection chip 12, electrical connection structure 20, first chip 22 and second chip 24. Wherein the connecting chip 12 includes a functional surface and a non-functional surface that are opposite to each other, the first chip 22 includes a functional surface 220 and a non-functional surface 222 that are opposite to each other, the second chip 24 includes a functional surface 240 and a non-functional surface 242 that are opposite to each other, the first chip 22 and the second chip 24 are disposed on the same layer on one side of the package substrate 10, the functional surfaces of the first chip 22 and the second chip 24 face the package substrate 10, the signal transmission regions 30 on the functional surfaces of the first chip 22 and the second chip 24 are disposed close to each other, the signal transmission regions 30 are far away from the package substrate 10 relative to the non-signal transmission regions 40 on the functional surfaces, the electrical connection structure 20 is located between the package substrate 10 and the non-signal transmission regions 40, and is electrically connected to the package substrate 10 and the non-signal transmission region 40, the connection chip 12 is located between the signal transmission regions 30 of the first chip 22 and the second chip 24 and the package substrate 10, and the functional surface 120 of the connection chip 12 faces the signal transmission region 30 and is electrically connected to the signal transmission region 30.
In a specific application scenario, the first chip 22 is a CPU chip, the second chip 24 is a GPU chip, the connection chip 12 is a silicon bridge, and the electrical connection structure 20 is a copper pillar, so that the signal transmission region 30 between the CPU chip and the GPU chip performs signal transmission through the silicon bridge, thereby improving the signal transmission performance, and the non-signal transmission region 40 between the CPU chip and the GPU chip is electrically connected to the package substrate 10 through the copper pillar, thereby reducing the package product.
In addition, the above-mentioned one first chip 22 may be electrically connected with at least one second chip 24 through the connection chip 12. For example, the bonding pads (not shown) of the signal transmission region 30 are disposed at four corners of the first chip 22, and the number of the second chips 24 corresponding to one first chip 22 may be four, and the chip types of the four second chips 24 may be the same or different.
In the semiconductor package device 100 provided by the present application, the signal transmission region 30 and the non-signal transmission region 40 of the main chip are connected in different ways: the signal transmission region 30 is connected with the first chip 22 and the second chip 24 through the connection chip 12, so that the signal transmission rate between the first chip 22 and the second chip 24 is improved, and the performance of the packaged device is improved; the non-signal transmission region 40 is connected to the package substrate 10 through the electrical connection structure 20, so that the package cost can be reduced.
Further, referring to fig. 1, the semiconductor package device 100 further includes a plurality of first conductive pillars 14 respectively disposed on the connection pads of the functional surface 120 of the connection chip 12, and two ends of the first conductive pillars 14 are electrically connected to the signal transmission region 30 and the connection pads respectively. The first conductive pillar 14 is made of at least one metal material selected from copper, nickel, gold, and silver. Since the bonding pad on the signal transmission region 30 is a smaller bonding pad on the signal transmission region 30, and the connection bonding pad is also a smaller bonding pad on the functional surface 120 of the connection chip 12, the formation of the first conductive pillar 14 on the connection bonding pad is beneficial to more fully and firmly connecting the connection chip 12 and the signal transmission region 30.
Further, referring to fig. 1, the semiconductor package device 100 further includes a first underfill 16, the first underfill 16 covers the functional surface 120 of the connection chip 12 facing the signal transmission region 30, and the first conductive pillars 14 are located in the first underfill 16. The first underfill 16 continuously covers the side surfaces of the plurality of first conductive pillars 14, so as to fill the gap between the signal transmission area 30 and the functional surface 120 of the connection chip 12, thereby further fixing the position of the connection chip 12, and reducing the probability of the connection chip 12 tilting in the subsequent process, and the first underfill 16 can protect the corresponding circuit structure on the functional surface 120 of the connection chip 12, protect the corresponding circuit structure on the signal transmission area 30, and reduce the probability of the short circuit of the circuit structure.
Further, referring to fig. 1, the semiconductor package device 100 further includes a second underfill 26, and the second underfill 26 continuously covers the side surfaces of the electrical connection structures 20, so as to enhance the reliability of the connection between the non-signal transmission regions 40 of the first chip 22 and the second chip 24 and the package substrate 10, protect the corresponding circuit structures on the non-signal transmission regions 40 and/or the corresponding circuit structures on the package substrate 10, and reduce the probability of short circuit of the circuit structures.
In one embodiment, with reference to fig. 1, the electrical connection structure 20 includes a plurality of second conductive pillars 32 and a plurality of first solder balls 34, the plurality of second conductive pillars 32 are respectively disposed on the pads (not shown) of the non-signal transmission region 40, and electrically connected to the bonding pads of the non-signal transmission region 40, the plurality of first solder balls 34 are respectively located at the end portions of the second conductive pillars 32 facing the package substrate 10, the first solder balls 34, the second conductive pillars 32 are electrically connected to the package substrate 10, the non-signal transmission region 40 is electrically connected to the package substrate 10 through the first solder balls 34 and the second conductive pillars 32, and the heights of the first solder balls 34 and the second conductive pillars 32 can be adjusted appropriately, so as to adjust the distance between the non-functional surface 122 of the connecting chip 12 and the package substrate 10, and the distance between the non-signal transmission region 40 and the package substrate 10 is maintained to facilitate heat dissipation of the first chip 22 and the second chip 24. In addition, the pad on the non-signal transmission region 40 is a smaller solder joint on the non-signal transmission region 40, and the solder joint on the package substrate 10 is a smaller point on the package substrate 10, so that the second conductive pillar 32 and the first conductive pillar 34 are beneficial to more fully and firmly connecting the non-signal transmission region 40 and the package substrate 10, and the second underfill 26 continuously covers the side surfaces of the first conductive pillar 34 and the second conductive pillar 32 and protects the corresponding circuit structure on the non-signal transmission region 40 and the corresponding circuit structure on the package substrate 10.
In another embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application, and the semiconductor package device 200 in fig. 2 has a structure similar to that of the semiconductor package device 100 in fig. 1, and also includes: package substrate 10, connection chip 12, first chip 22, second chip 24, and the like. The difference is that the electrical connection structure 20a includes a first redistribution layer 42 and a plurality of second solder balls 44, the first redistribution layer 42 is disposed on the surface of the non-signal transmission region 40 and electrically connected to the pads of the non-signal transmission region 40, and the plurality of second solder balls 44 are disposed between the first redistribution layer 42 and the package substrate 10, one end of each of the second redistribution layers is electrically connected to the first redistribution layer 42, and the other end of each of the second redistribution layers is electrically connected to the package substrate 10. The patterned first redistribution layer 42 may be disposed according to actual needs and electrically connected to some or all of the pads of the non-signal transmission region 40, and further electrically connected to the second solder balls 44, and the height of the second solder balls 44 may be adjusted appropriately to adjust the distance between the non-functional surface 122 of the connection chip 12 and the package substrate 10, and maintain the distance between the non-signal transmission region 40 and the package substrate 10, so as to facilitate heat dissipation of the first chip 22 and the second chip 24. In addition, the pads on the non-signal transmission region 40 are smaller pads on the non-signal transmission region 40, and the pads on the package substrate 10 are smaller points on the package substrate 10, so that the first redistribution layer 42 and the second solder balls 44 facilitate a more sufficient and firm connection between the non-signal transmission region 40 and the package substrate 10.
Optionally, a first passivation layer 46 is further included between the first redistribution layer 42 and the non-signal transmission region 40, a second passivation layer 48 is further included on two sides of the second solder ball 44, a first opening (not shown) is formed on the first passivation layer 46 corresponding to the pad of the non-signal transmission region 40, the first redistribution layer 42 is electrically connected to the pad of the signal transmission region 30 through the first opening, the first passivation layer 46 may separate the first redistribution layer 42, and protect the circuits in the signal transmission region 30, a second opening (not shown) is formed in the second passivation layer 4848 corresponding to the first redistribution layer 42, one end of the second solder ball 44 is electrically connected to the first redistribution layer 42 through the second opening, the other end of the second solder ball 44 is electrically connected to the package substrate 10, the second passivation layer 48 can further fix the position of the second solder ball 44, and the second underfill 26 continuously covers the side surface of the second solder ball 44 and protects the corresponding circuit structure on the package substrate 10.
In another embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor package device according to another embodiment of the present application, and the semiconductor package device 300 in fig. 3 has a structure similar to the semiconductor package device 100 in fig. 1, and also includes: package substrate 10, connection chip 12, first chip 22, second chip 24, and the like. The difference is that the electrical connection structure 20b includes a second redistribution layer 52 and a plurality of third solder balls 54, the second redistribution layer 52 is located on the surface of the package substrate 10 facing the non-signal transmission region 40 and electrically connected to the package substrate 10, and the plurality of third solder balls 54 are located between the second redistribution layer 52 and the non-signal transmission region 40, one end of each of the third solder balls is electrically connected to the second redistribution layer 52, and the other end of each of the third solder balls is electrically connected to the non-signal transmission region 40. The patterned second redistribution layer 52 may be disposed on the surface of the package substrate 10 according to actual requirements, and electrically connected to some or all of the pads on the package substrate 10, and further electrically connected to the third solder balls 54, wherein the height of the third solder balls 54 may be appropriately adjusted to adjust the distance between the non-functional surface 122 of the connection chip 12 and the package substrate 10, and maintain the distance between the non-signal transmission region 40 and the package substrate 10, so as to facilitate heat dissipation of the first chip 22 and the second chip 24. In addition, the pads on the non-signal transmission region 40 are smaller pads on the non-signal transmission region 40, and the pads on the package substrate 10 are smaller points on the package substrate 10, so that the second redistribution layer 52 and the third solder balls 54 are beneficial to more sufficiently and firmly connecting the non-signal transmission region 40 and the package substrate 10.
Optionally, both sides of the second redistribution layer 52 and one end away from the package substrate 10 further include a third passivation layer 56, a third opening (not shown) is disposed at a position of the third passivation layer 56 corresponding to the second redistribution layer 52, one end of the third solder ball 54 is electrically connected to the package substrate 10 through the third opening, the other end of the third solder ball 54 is electrically connected to the pad of the non-signal transmission region 40, the third passivation layer 56 may space the second redistribution layer 52 and further fix the position of the third solder ball 54, and the second underfill 26 continuously covers the side surface of the third solder ball 54 and protects the corresponding circuit structure on the non-signal transmission region 40.
Further, referring to fig. 1 again, the package substrate 10 has a first surface 102 facing the first chip 22 and the second chip 24.
In one embodiment, with continued reference to fig. 1, the first surface 102 of the package substrate 10 facing the first chip 22 and the second chip 24 is flat, a gap is formed between the non-functional surface 122 of the connection chip 12 and the first surface 102, and the second underfill 26 fills the gap, so as to better dissipate heat from the first chip 22 and the second chip 24.
In another embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of a semiconductor package device according to another embodiment of the present invention, in the semiconductor package device 400, the first surface 102a of the package substrate 10a facing the first chip 22a and the second chip 22a is flat, the non-functional surface 122a of the connection chip 12a directly contacts the first surface 102a, the second underfill 26a is disposed on two sides of the connection chip 12a, and when there is no gap between the connection chip 12a and the package substrate 10a, the connection between the connection chip 12a and the package substrate 10a is more stable, so as to be suitable for application scenarios with higher requirements on structural stability, such as devices used in vehicle-mounted products.
In another embodiment, referring to fig. 5, fig. 5 is a schematic structural diagram of a semiconductor package device 500 according to another embodiment of the present invention, in which a first surface 102b of a package substrate 10b facing a first chip 22b and a second chip 22b has a groove (not shown), an inactive surface 122b of a connecting chip 12b is adhered to the surface of the groove, at least a portion of the connecting chip 12b is located in the groove, and second underfill 26b is disposed on two sides of the connecting chip 12b, so that when there is no gap between the inactive surface 122b of the connecting chip 12b and the package substrate 10b, the connection between the connecting chip 12b and the package substrate 10b is more stable, and the semiconductor package device is suitable for application scenarios with very high requirements on structural stability, such as outdoor scenarios with harsh environments.
Optionally, referring to fig. 6, fig. 6 is a schematic structural diagram of a semiconductor package device according to still another embodiment of the present application, and the semiconductor package device 600 in fig. 6 has a structure similar to that of the semiconductor package device 100 in fig. 1, and also includes: package substrate 10, connection chip 12, first chip 22, second chip 24, and the like. The semiconductor package device 600 further includes a molding compound layer 60, the molding compound layer 60 continuously covering the side surfaces of the first chip 22 and the second chip 24, and the molding compound layer 60. The molding compound layer 60 can effectively fix the first chip 22 and the second chip 24, but the molding compound layer 60 does not cover the non-functional surface 222 of the first chip 22 and the non-functional surface 224 of the second chip 24, so as to dissipate heat of the first chip 22 and the second chip 24, and the material of the molding compound layer 60 may be epoxy resin or the like.
The semiconductor packaging device provided by each embodiment of the application can be applied to application scenes with different requirements on heat dissipation performance and structural stability according to different structural characteristics, so that the semiconductor packaging device provided by the application has wider applicability. In the semiconductor package device provided in the embodiments of the present application, the signal transmission regions of the first chip 22 and the second chip 24 are connected by using the connection chip 12, so that the signal transmission rate between the main chips can be increased, and the performance of the package device can be improved, and the non-signal transmission regions of the first chip 22 and the second chip 24 are connected to the package substrate by using a common conductive structure, so that the package cost can be reduced.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A semiconductor package device, comprising:
a package substrate;
the first chip and the second chip are arranged on one side of the packaging substrate in the same layer, functional surfaces of the first chip and the second chip face the packaging substrate, signal transmission areas on the functional surfaces of the first chip and the second chip are arranged close to each other, and the signal transmission areas are far away from the packaging substrate relative to non-signal transmission areas on the functional surfaces;
the electric connection structure is positioned between the packaging substrate and the non-signal transmission area and is electrically connected with the packaging substrate and the non-signal transmission area;
and the connecting chip is positioned between the signal transmission areas of the first chip and the second chip and the packaging substrate, and the functional surface of the connecting chip faces the signal transmission areas and is electrically connected with the signal transmission areas.
2. The semiconductor package device of claim 1, further comprising:
and the first conductive columns are respectively arranged on the connecting bonding pads of the functional surfaces of the connecting chip, and two ends of each first conductive column are respectively electrically connected with the signal transmission area and the connecting bonding pads.
3. The semiconductor package device of claim 2, further comprising:
the first underfill covers the functional surface of the connecting chip and faces one side of the signal transmission area, and the first conductive column is located in the first underfill.
4. The semiconductor package device of claim 1, wherein the electrical connection structure comprises:
the second conductive columns are respectively positioned on the bonding pads of the non-signal transmission area and are electrically connected with the bonding pads of the non-signal transmission area;
and the first solder balls are respectively positioned at the end parts of the second conductive columns facing the packaging substrate, and the first solder balls, the second conductive columns and the packaging substrate are electrically connected.
5. The semiconductor package device of claim 1, wherein the electrical connection structure comprises:
the first rewiring layer is positioned on the surface of the non-signal transmission area and is electrically connected with the bonding pad of the non-signal transmission area;
and a plurality of second solder balls located between the first redistribution layer and the package substrate, wherein one end of each second solder ball is electrically connected with the first redistribution layer, and the other end of each second solder ball is electrically connected with the package substrate.
6. The semiconductor package device of claim 1, wherein the electrical connection structure comprises:
the second rewiring layer is positioned on the surface, facing the non-signal transmission area, of the packaging substrate and is electrically connected with the packaging substrate;
and a plurality of third solder balls located between the second re-wiring layer and the non-signal transmission region, one end of each third solder ball being electrically connected to the second re-wiring layer, and the other end of each third solder ball being electrically connected to the non-signal transmission region.
7. The semiconductor package device of any one of claims 1-6, further comprising:
and the second underfill continuously covers the side surfaces of the electric connection structure.
8. The semiconductor package device of claim 1,
the first surface of the packaging substrate facing the first chip and the second chip is flat, and a gap or direct contact is formed between the non-functional surface of the connecting chip and the first surface.
9. The semiconductor package device of claim 1,
the first surface of the packaging substrate facing the first chip and the second chip is provided with a groove, and at least part of the connecting chip is positioned in the groove.
10. The semiconductor package device of claim 1, further comprising:
and the plastic packaging layer continuously covers the side surfaces of the first chip and the second chip.
CN202010367784.7A 2020-04-30 2020-04-30 Semiconductor packaging device Pending CN111554656A (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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