TWI825707B - Method for fabricating a semiconductor device with multi-stacking carrier structure - Google Patents

Abstract

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming an inter-dielectric layer on the substrate; forming a conductive pad in the inter-dielectric layer; forming a first tier on the inter-dielectric layer, wherein the first tier comprises a first passivation layer on the inter-dielectric layer, a first insulating layer on the first passivation layer, and a first via along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad; forming a second tier on the first tier, wherein the second tier comprises a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via along the second passivation layer and the second insulating layer, and electrically connected to the first via; and forming a third tier on the second tier, wherein the third tier comprises a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via along the third passivation layer and the third insulating layer, and electrically connected to the second via. The first tier, the second tier, and the third tier together configure a multi-stacking carrier structure.

Description

Preparation method of semiconductor device with multi-stacked carrier structure

This application claims priority to U.S. Patent Application Nos. 17/561,151 and 17/560,548 (that is, the priority date is "December 23, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of manufacturing a semiconductor device. In particular, it relates to a method for manufacturing a semiconductor device having a multi-stacked carrier structure.

Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components continue to shrink in size to meet the growing demand for computing power. However, various problems arise during the miniaturization process, and these problems are increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability, as well as reduced complexity.

The above description of "prior art" is merely to provide background technology, and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" They should not be used as any part of this case.

One aspect of the present disclosure provides a semiconductor device, including: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stacked carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the A first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a a second passivation layer, a second insulating layer located on the second passivation layer, and a second through hole, wherein the second through hole is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first through hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, a third insulating layer located on the third passivation layer, and A third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

Another aspect of the present disclosure provides a multi-stacked carrier structure, including: an etch stop layer; a first layer including a first passivation layer located on the etch stop layer, and a first passivation layer located on the first passivation layer. an insulating layer, and a first through hole, wherein the first through hole is disposed along the first passivation layer and the first insulating layer; a second layer located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is disposed along the second passivation layer and the second insulating layer, and electrically connected to the first through hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, and a third insulating layer located on the third passivation layer layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the substrate on the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first through hole, wherein the The first through hole is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second layer includes a second layer located on the first layer. a second passivation layer on the insulating layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is along the second passivation layer and the second insulating layer disposed and electrically connected to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, on the third passivation layer A third insulating layer on the second layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the plurality of The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an intermediate medium electrically layer on the substrate; forming a conductive liner in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial layer from the etch stop layer ; and thinning the substrate.

Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure can be used as a temporary carrier to assist the substrate thinning process. Therefore, no carrier is required during the thinning process of the substrate. As a result, the manufacturing cost of semiconductor elements can be reduced. In addition, after the thinning process, the multi-stacked carrier structure can provide electrical paths to the device components of the semiconductor device. Therefore, the performance of semiconductor elements can be easily analyzed in the presence of multi-stacked carrier structures.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages forming the subject of the patent claims of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following disclosure provides many different embodiments or examples for implementing various components of the disclosed embodiments. Examples of specific elements and their arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and should not limit the scope of the embodiments of the present disclosure. For example, when a description refers to a first component being formed "on" or "on" a second component, that may include embodiments in which the first component is in direct contact with the second component, or may include both. Embodiments in which other components are formed without direct contact. In addition, the present disclosure may repeat reference symbols and/or labels in different embodiments. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or structures discussed.

In addition, this article uses words related to space, such as: "below", "below", "lower", "above", "higher", and similar words for convenience. Describe the relationship between one element or component and another element or component shown in the drawings. These spatial relative terms are intended to encompass different orientations of the component in use or operation other than the orientation depicted in the drawings. The device may be turned in different orientations (rotated 90 degrees or at other orientations) and the spatially relative adjectives used therein may be interpreted similarly.

It will be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it can be directly connected or coupled to the other element or layer, or intervening elements or layers may be present. .

It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless stated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, words such as "same," "equal," "planar," or "coplanar" when referring to orientation, arrangement, location, shape, size, quantity or other measure are not intended to be used herein. does not necessarily mean the exact same orientation, layout, position, shape, size, quantity or other measurement, but is intended to cover substantially the same orientation, layout, position, shape, within acceptable variations, such as due to the manufacturing process. Size, quantity or other measurement. The word "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or within an acceptable range of variation due, for example, to a manufacturing process. Can be identical, equal or flat.

In the present disclosure, semiconductor components generally refer to components that can function by utilizing semiconductor characteristics, and electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the category of semiconductor components.

It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of direction Z, and below or down corresponds to the arrow direction opposite to direction Z.

FIG. 1 shows a schematic cross-sectional view of a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 2 shows a close-up cross-sectional view of the first through hole 215 of the semiconductor device 1A according to an embodiment of the present disclosure. 3 to 5 show schematic cross-sectional views of semiconductor devices 1B, 1C, and 1D according to some embodiments of the present disclosure.

Referring to FIG. 1 , the semiconductor device 1A may include a substrate 101 , a plurality of device elements (not shown for clarity), an inter-dielectric layer 103 , a plurality of conductive components, and a multi-stack Carrier structure 200.

Referring to FIG. 1 , substrate 101 may include a bulk semiconductor substrate composed entirely of at least one semiconductor material. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or others. Group III-V compound semiconductors or Group II-VI compound semiconductors, or a combination of the foregoing.

In some embodiments, the thickness T0 of the substrate 101 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness T0 of the substrate 101 may be approximately 3 μm.

Referring to FIG. 1 , the device components may be formed on a bulk semiconductor substrate. Portions of the component components may be formed in the bulk semiconductor substrate. These component components may be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, and fin-shaped field-effect transistors. Transistors (fin field-effect-transistors), their analogues, or combinations of the foregoing.

Referring to FIG. 1 , an intermediate dielectric layer 103 may be disposed on the substrate 101 . In some embodiments, the intermediate dielectric layer 103 may be a stacked structure. The intermediate dielectric layer 103 may include a plurality of insulator sub-layers. Each of the insulating sublayers may have a thickness of between about 0.5 microns and about 3.0 microns. The insulator layers may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low-k dielectric materials, and the like. , or a combination of the above. The insulating sub-layers may include different materials, but are not limited thereto. Low dielectric constant dielectric materials may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. The manufacturing technology of the dielectric layers may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar technologies. A planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

It should be noted that in the description of the present disclosure, the word "about" used to modify the amounts of ingredients, components, or reactants used in the present disclosure refers, for example, to typical measurements and liquids used to prepare concentrates or solutions. Handlers may produce quantity changes. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in making the compositions or practicing the methods. On the one hand, the word "approximately" means within 10% of the reported value. On the other hand, the word "approximately" means within 5% of the reported value. Also, on the other hand, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 1 , the conductive components may be disposed in the intermediate dielectric layer 103 . The conductive components may include interconnect layers (not shown for clarity), conductive vias (not shown for clarity), and a plurality of conductive pads 105 . The interconnect layers may be separated from each other and may be disposed horizontally in the dielectric layers along the direction Z. In this embodiment, the topmost interconnect layer may be designated conductive pad 105 . The top surfaces of the conductive pads 105 and the top surface of the intermediate dielectric layer 103 may be substantially coplanar. The conductive vias may connect adjacent interconnect layers, adjacent component structures and interconnect layers, and adjacent conductive pads 105 and interconnect layers along the direction Z. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive components may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide) For example, titanium nitride), transition metal aluminides, or combinations of the foregoing. The conductive features may be formed during formation of the dielectric layers.

In some embodiments, the component components and the conductive components may together constitute a functional unit of the semiconductor component 1A. In the description of the present disclosure, a functional unit generally refers to a functionally related circuit that is divided into different units for functional purposes. In some embodiments, functional units may typically be highly complex circuits, such as processor cores or accelerator units. In some other embodiments, the complexity and functionality of the functional units may be more complex or less complex.

Referring to FIG. 1 , a multi-stack carrier structure 200 may be disposed on the intermediate dielectric layer 103 . The multi-stacked carrier structure 200 may include a first tier 210 , a second layer 220 , a third layer 230 , a fourth layer 240 , a fifth layer 250 , and a top passivation layer 203 . In some embodiments, the thickness TL of the multi-stack carrier structure 200 may be greater than about 500 microns. In some embodiments, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness TO of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 1 , a first layer 210 may be disposed on the intermediate dielectric layer 103 . The first layer 210 may include a first passivation layer 211 , a first insulation layer 213 , and a plurality of first vias 215 .

Referring to FIG. 1 , a first passivation layer 211 may be disposed on the intermediate dielectric layer 103 . In some embodiments, the first passivation layer 211 may include, for example, an oxide material. In some embodiments, the first passivation layer 211 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass ( fluorinated silicate glass), its similar materials, or combinations of the foregoing. In some embodiments, the thickness T1 of the first passivation layer 211 may range from about 1 μm to about 2 μm.

Referring to FIG. 1 , a first insulation layer 213 may be disposed on the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, an oxide material. In some embodiments, the first insulation layer 213 may include the same material as the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, similar materials, or combinations thereof. In some embodiments, the thickness T2 of the first insulating layer 213 may be less than about 200 μm. For example, the thickness T2 of the first insulating layer 213 may range from about 150 μm to about 190 μm.

Referring to FIGS. 1 and 2 , in some embodiments, the first through holes 215 may be provided along the first insulating layer 213 and the first passivation layer 211 , on the conductive pads 105 , and respectively and correspondingly. The ground is electrically connected to the conductive pads 105 .

For simplicity, clarity and convenience of description, only one first through hole 215 is described.

In some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W0 of the bottom surface 215BS of the first through hole 215 may be smaller than the width W1 of the top surface 215TS of the first through hole 215 . In some embodiments, the first through hole 215 may include a filler layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and an isolation layer IL.

It should be noted that in the description of the present disclosure, the surface of an element (or component) located at the highest vertical level along direction Z is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along direction Z is called the bottom surface of the element (or component).

It should be noted that in the description of the present disclosure, "width" means measured from one side surface of an element (e.g., layer, plug, trench, hole, opening, etc.) to an opposing surface in a cross-sectional perspective view Component size. Where indicated, the word "thickness" may be substituted for "width".

The filler layer FL may be disposed along the first insulation layer 213 and the first passivation layer 211 and on the conductive pad 105 . In some embodiments, the filler layer FL may have an aspect ratio between about 1:2 and about 1:35 or between about 1:10 and about 1:25. The filler layer FL may include, for example, doped polycrystalline silicon, tungsten, copper, carbon nanotubes, or solder alloy.

Referring to FIG. 2 , in some embodiments, the seed layer SL may have a U-shaped cross-sectional profile. The seed layer SL may be disposed between the filler layer FL and the first insulating layer 213 , between the filler layer FL and the first passivation layer 211 , and between the filler layer FL and the conductive pad 105 . In some embodiments, the seed layer SL may have a thickness of between approximately 10 nm and approximately 40 nm. In some embodiments, the seed layer SL may include copper, for example. The seed layer SL can reduce the resistivity of the opening during the formation of the filler layer FL.

In some embodiments, the adhesion layer AL may have a U-shaped cross-sectional profile. The adhesion layer AL may be disposed between the seed layer SL and the first insulating layer 213 , between the seed layer SL and the first passivation layer 211 , and between the seed layer SL and the conductive pad 105 . The seed layer SL may include, for example, titanium, tantalum, titanium, tungsten, or manganese nitride. The adhesion layer AL can improve the adhesion between the seed layer SL and the barrier layer BL.

In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be located between the adhesion layer AL and the first insulating layer 213 , between the adhesion layer AL and the first passivation layer 211 , and between the adhesion layer AL and the conductive pad 105 . The barrier layer BL may include, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bilayer. The barrier layer BL can inhibit the conductive material of the filler layer FL from diffusing into the first insulating layer 213 , the first passivation layer 211 , or the intermediate dielectric layer 103 .

In some embodiments, the isolation layer IL may be disposed between the barrier layer BL and the first insulating layer 213, and between the barrier layer BL and the first passivation layer 211. In some embodiments, the isolation layer IL may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The isolation layer IL may have a thickness of between approximately 50 nm and approximately 200 nm. In some embodiments, the isolation layer IL may include, for example, parylene, epoxy resin, or poly(p-xylene). The isolation layer IL may have a thickness of between about 1 μm and about 5 μm. The isolation layer IL can ensure that the filler layer FL is electrically isolated between the first insulating layer 213 and the first passivation layer 211 .

Referring to FIG. 1 , a second layer 220 may be disposed on the first layer 210 . The second layer 220 may include a second passivation layer 221, a second insulation layer 223, and a plurality of second through holes 225. The second passivation layer 221 may be disposed on the first insulation layer 213 . The second insulation layer 223 may be disposed on the second passivation layer 221. The second through holes 225 may be disposed along the second insulating layer 223 and the second passivation layer 221 , disposed on the first through holes 215 , and electrically connected to the first through holes 215 respectively and correspondingly. . The second passivation layer 221 , the second insulation layer 223 , and the second through holes 225 may respectively and correspondingly include the same material as the first passivation layer 211 , the first insulation layer 213 , and the first through holes 215 , whose description will not be repeated here.

Referring to FIG. 1 , the width W2 of the top surface 225TS of the second through hole 225 may be greater than the width W1 of the top surface 215TS of the first through hole 215 .

Referring to FIG. 1 , a third layer 230 may be disposed on the second layer 220 . The third layer 230 may include a third passivation layer 231, a third insulation layer 233, and a plurality of third through holes 235. The third passivation layer 231 may be disposed on the second insulation layer 223. The third insulation layer 233 may be disposed on the third passivation layer 231. The third through holes 235 may be disposed along the third insulating layer 233 and the third passivation layer 231 , disposed on the second through holes 225 , and electrically connected to the second through holes 225 respectively and correspondingly. . The third passivation layer 231 , the third insulating layer 233 , and the third through holes 235 may respectively and correspondingly include the same material as the first passivation layer 211 , the first insulating layer 213 , and the first through holes 215 , whose description will not be repeated here.

Referring to FIG. 1 , the width W3 of the top surface 235TS of the third through hole 235 may be greater than the width W2 of the top surface 225TS of the second through hole 225 .

Referring to FIG. 1 , the fourth layer 240 may be disposed on the third layer 230 . The fourth layer 240 may include a fourth passivation layer 241, a fourth insulation layer 243, and a plurality of fourth through holes 245. The fourth passivation layer 241 may be disposed on the third insulation layer 233. The fourth insulation layer 243 may be disposed on the fourth passivation layer 241. The fourth through holes 245 may be disposed along the fourth insulating layer 243 and the fourth passivation layer 241 , disposed on the third through holes 235 , and electrically connected to the third through holes respectively and correspondingly. 235. The fourth passivation layer 241, the fourth insulating layer 243, and the fourth through holes 245 may respectively and correspondingly include the same material as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , whose description will not be repeated here.

Referring to FIG. 1 , the width W4 of the top surface 245TS of the fourth through hole 245 may be greater than the width W3 of the top surface 235TS of the third through hole 235 .

Referring to FIG. 1 , the fifth layer 250 may be disposed on the fourth layer 240 . The fifth layer 250 may include a fifth passivation layer 251, a fifth insulation layer 253, and a plurality of fifth through holes 255. The fifth passivation layer 251 may be disposed on the fourth insulation layer 243. The fifth insulation layer 253 may be disposed on the fifth passivation layer 251. The fifth through holes 255 may be disposed along the fifth insulating layer 253 and the fifth passivation layer 251 , disposed on the fourth through holes 245 , and electrically connected to the fourth through holes respectively and correspondingly. 245. The fifth passivation layer 251 , the fifth insulating layer 253 , and the fifth through holes 255 may respectively and correspondingly include the same material as the first passivation layer 211 , the first insulating layer 213 , and the first through holes 215 , whose description will not be repeated here.

Referring to FIG. 1 , the width W5 of the top surface 255TS of the fifth through hole 255 may be greater than the width W4 of the top surface 245TS of the fourth through hole 245 .

It should be noted that in the description of the present disclosure, the number of layers of the multi-stacked carrier structure 200 is for illustration purposes only. In other words, the number of layers of the multi-stack carrier structure 200 may be more or less than five layers.

Referring to FIG. 1 , the top passivation layer 203 may be disposed on the topmost insulating layer (ie, the fifth insulating layer 253 of the fifth layer 250 ). The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, or solder resist film. , or similar materials, or a combination of the foregoing. In some other embodiments, top passivation layer 203 may be a dielectric layer. The dielectric layer may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations of the foregoing.

It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen and nitrogen, in which the proportion of nitrogen is greater than the proportion of oxygen.

Referring to FIG. 1 , a plurality of first top openings 203O may be disposed along the top passivation layer 203 to expose the fifth through holes 255 respectively and correspondingly. The exposed fifth via 255 may be electrically coupled to a probe for electrical characteristic testing.

During the thinning process of the substrate 101, the multi-layer stacked carrier structure 200 may serve as a temporary carrier. With the aid of the multilayer stacked carrier structure 200, the performance of the semiconductor component 1A including a substrate 101 smaller than 10 μm can be analyzed. In contrast, conventional semiconductor devices including substrates smaller than 10 μm are covered by carriers, so their performance cannot be easily analyzed.

Referring to FIG. 3 , the structure of the semiconductor element 1B may be similar to the structure shown in FIG. 1 . Components in FIG. 3 that are the same as or similar to those in FIG. 1 are marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 3 , a plurality of redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the fifth through holes 255 , and electrically connected to the fifth through holes 255 respectively and correspondingly. The redistribution layers 205 can re-route the fifth vias 255 to provide a more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

Referring to FIG. 4 , the structure of the semiconductor element 1C may be similar to the structure shown in FIG. 1 . Components in FIG. 4 that are the same as or similar to those in FIG. 1 are marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 4 , the fifth layer 250 , the fourth layer 240 , the third layer 230 , the second layer 220 , and the first layer 210 may be disposed on the intermediate dielectric in the reverse order of the multi-stacked carrier structure 200 shown in FIG. 1 on layer 103. For example, the fifth insulating layer 253 is disposed on the intermediate dielectric layer 103 , the fifth passivation layer 251 is disposed on the fifth insulating layer 253 , the fourth insulating layer 243 is disposed on the fifth passivation layer 251 , and the fourth passivation layer 241 disposed on the fourth insulating layer 243.

Referring to FIG. 4 , in some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W7 of the bottom surface 215BS of the first through hole 215 may be greater than the width W6 of the top surface 215TS of the first through hole 215 .

Referring to FIG. 4 , in some embodiments, an etch stop layer 207 may be disposed on the first insulation layer 213 of the first layer 210 . In some embodiments, etch stop layer 207 may preferably include a dielectric material whose etch selectivity differs from the etch selectivity of adjacent layers. For example, the etch stop layer 207 may include silicon nitride, silicon carbonitride, silicon oxycarb, similar materials, or combinations thereof. A plurality of second top openings 207O may be provided along the etch stop layer 207 to expose the first vias 215 . The exposed first through hole 215 may be electrically coupled to a probe for electrical characteristic testing.

Referring to FIG. 5 , the structure of the semiconductor element 1D may be similar to the structure shown in FIG. 4 . Components in FIG. 5 that are the same as or similar to those in FIG. 4 have been marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 5 , a top passivation layer 203 may be disposed on the first insulation layer 213 of the first layer 210 . The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto build-up film, solder photoresist film, or similar materials, or combinations thereof. . In some other embodiments, top passivation layer 203 may be a dielectric layer. The dielectric layer may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitride such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations of the foregoing.

Referring to FIG. 5 , the redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the first through holes 215 , and electrically connected to the first through holes 215 respectively and correspondingly. The redistribution layers 205 can reroute the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

It should be noted that the words "forming," "formed," and "form" may mean and include creating, building, patterning, implanting, or depositing elements, doping debris, or materials in any way. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

It should be noted that in the description of the present disclosure, the functions or steps mentioned herein may occur in an order different from that mentioned in the drawings. For example, two figures shown in succession may actually occur substantially concurrently or sometimes in the reverse order, depending on the functions or steps involved.

FIG. 6 shows a method 10 for manufacturing a semiconductor device 1A in the form of a flow chart according to an embodiment of the present disclosure. 7 to 21 are schematic cross-sectional views showing a manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIGS. 6 and 7 , in step S11 , a substrate 101 may be provided, and an intermediate dielectric layer 103 may be formed on the substrate 101 .

Referring to FIG. 7 , the material of the substrate 101 is as shown in FIG. 1 , and its description will not be repeated here. In some embodiments, substrate 101 may include a semiconductor-on-insulator structure that includes, from bottom to top, a processing substrate, an insulating layer, and a topmost layer of semiconductor material. The handle substrate and the topmost semiconductor material layer may include the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and/or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulating layer may include a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness of between approximately 10 nm and approximately 200 nm. It should be noted that at this stage, the thickness T0 of the substrate 101 may be greater than 700 μm or greater than 500 μm.

Referring to FIG. 7 , the manufacturing technology for forming the intermediate dielectric layer 103 on the substrate 101 may include a deposition process such as chemical vapor deposition. Planarization processes such as chemical mechanical polishing can be performed to provide a substantially flat surface for subsequent process steps. Component features (not shown for clarity) and conductive features (not shown for clarity) may be formed during formation of intermediate dielectric layer 103 . The manufacturing technology for forming the conductive pads 105 in the intermediate dielectric layer 103 may include, for example, a damascene process. The top surfaces of the conductive pads 105 and the top surface of the intermediate dielectric layer 103 may be substantially coplanar.

Referring to FIG. 6 and FIG. 8 to FIG. 19 , in step S13 , a multi-stack carrier structure 200 may be formed on the intermediate dielectric layer 103 .

Referring to FIG. 8 , the first passivation layer 211 may be formed on the intermediate dielectric layer 103 , and the manufacturing technology of the third passivation layer 231 may include, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, or other applicable depositions. process. In some embodiments, an oxide bonding process may be performed to form the first insulating layer 213 on the first passivation layer 211 . The material of the first passivation layer 211 is shown in FIG. 1 , and its description will not be repeated here.

Referring to FIG. 9 , a first mask layer 510 can be formed on the first insulating layer 213 . The first mask layer 510 may include a plurality of first patterned openings 510O, which define the locations of the first through holes 215 . The first patterned opening 510O may have a width W8. The width W8 of the first patterned opening 510O may be larger than the width WC of the conductive pad 105 .

Referring to FIG. 10 , an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and a portion of the first passivation layer 211 and simultaneously form a plurality of first via openings. 215O. In some embodiments, sidewalls of the first through hole openings 215O may be tapered. After the oxide etching process, the first mask layer 510 can be removed.

Referring to FIG. 11 , the manufacturing technology for forming the first through holes 215 in the first through hole openings 215O may include, for example, chemical vapor deposition, physical vapor deposition, evaporation, sputtering, electroplating, or a combination of the foregoing. Planarization processes such as chemical mechanical polishing can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The materials and structures of the first through holes 215 are shown in Figures 1 and 2, and their description will not be repeated here. The first passivation layer 211, the first insulation layer 213, and the first through holes 215 together form the first layer 210.

Referring to FIG. 12 , a second passivation layer 221 may be formed on the first insulating layer 213 , a second insulating layer 223 may be formed on the second passivation layer 221 , and a second mask layer 520 may be formed on the second insulating layer 223 . The materials of the second passivation layer 221 and the second insulation layer 223 are as shown in FIG. 1 , and their description will not be repeated here. The second passivation layer 221, the second insulation layer 223, and the second mask layer 520 can be formed through steps similar to the first layer 210 shown in FIGS. 8 to 11, and their description will not be repeated here. The second mask layer 520 may include a plurality of second patterned openings 520O, which define the locations of the second through holes 225 . The width W9 of the second patterned opening 520O may be greater than the width W8 of the first patterned opening 510O.

Referring to FIG. 13 , an oxide etching process may be performed using the second mask layer 520 as a pattern guide to remove a portion of the second insulating layer 223 and a portion of the second passivation layer 221 and simultaneously form a plurality of second via openings. 225O. In some embodiments, sidewalls of the second through hole openings 225O may be tapered. After the oxide etching process, the second mask layer 520 can be removed.

Referring to FIG. 14 , the second through holes 225 can be formed in the second through hole openings 225O through a process similar to the first through holes 215 , and the description thereof will not be repeated here. Planarization processes such as chemical mechanical polishing can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The second passivation layer 221, the second insulation layer 223, and the second through holes 225 together form the second layer 220.

The greater width of the second patterned opening 520O may be transferred to the second via opening 225O and then inherited by the second via 225. The larger width of the second through hole 225 can provide a larger tolerance window for subsequent lithography processes (eg, the lithography process of the third through hole 235 ). As a result, the productivity of the semiconductor element 1A can be improved.

Referring to FIG. 15 , a third passivation layer 231 may be formed on the second insulating layer 223 , a third insulating layer 233 may be formed on the third passivation layer 231 , and a third mask layer 530 may be formed on the third insulating layer 233 . . The materials of the third passivation layer 231 and the third insulation layer 233 are as shown in FIG. 1 , and their description will not be repeated here. The third passivation layer 231, the third insulation layer 233, and the third mask layer 530 can be formed through steps similar to the first layer 210 shown in FIGS. 8 to 11, and their description will not be repeated here. The third mask layer 530 may include a plurality of third patterned openings 530O, which define the positions of the third through holes 235 . The width W10 of the third patterned opening 530O may be greater than the width W9 of the second patterned opening 520O.

Referring to FIG. 16 , an oxide etching process may be performed using the third mask layer 530 as a pattern guide to remove a portion of the third insulating layer 233 and a portion of the third passivation layer 231 and simultaneously form a plurality of third via openings. 235O. In some embodiments, sidewalls of the third through hole openings 235O may be tapered. After the oxide etching process, the third mask layer 530 may be removed.

Referring to FIG. 17 , the third through holes 235 can be formed in the third through hole openings 235O through steps similar to the first through holes 215 , and the description thereof will not be repeated here. Planarization processes such as chemical mechanical polishing can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The third passivation layer 231, the third insulation layer 233, and the third through holes 235 together form the third layer 230.

It should be noted that the third via 235 appears to be offset from the second via 225 in direction Z to emphasize the benefit of the larger tolerance window of the lithography process obtained through the wider width of the second via 225 . That is to say, even if the alignment of the lithography process is offset, the through holes 225 and 235 can still be electrically connected normally.

Referring to FIG. 18 , the fourth layer 240 and the fifth layer 250 can be formed through steps similar to the first layer 210 shown in FIGS. 8 to 11 , and their description will not be repeated here.

Referring to FIG. 19 , a top passivation layer 203 may be formed on the fifth layer 250 . The fabrication technique of the top passivation layer 203 may include, for example, spin coating, lamination, deposition, or similar techniques. Deposition may include chemical vapor deposition. The material of the top passivation layer 203 is shown in Figure 1, and its description will not be repeated here. The layers 210, 220, 230, 240, 250 and the top passivation layer 203 together form the multi-stack carrier structure 200.

In some embodiments, before the thinning process of the substrate 101, a thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1:, or between about Between 1:1 and about 7:5.

Referring to FIGS. 6 , 20 , and 21 , in step S15 , the substrate 101 may be thinned and a plurality of first top openings 203O may be formed along the top passivation layer 203 of the multi-stack carrier structure 200 .

Referring to FIG. 20 , the substrate may be thinned by using wafer grinding, mechanical abrasion, polishing, or similar techniques, or by using a chemical removal thinning process such as wet etching. 101. It should be noted that no carrier is required during the thinning process. The multi-stack carrier structure 200 may be used as a temporary carrier to assist in the thinning process of the substrate 101 .

Referring to FIG. 20 , after the thinning process, the thickness ratio of the thickness TL of the multilayer stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 21 , the first top openings 203O may be formed along the top passivation layer 203 to expose the fifth through holes 255 respectively and correspondingly. The exposed fifth via 255 may be electrically coupled to a probe for electrical characteristic testing. That is, the performance of the semiconductor element 1A after the substrate is thinned can be easily analyzed.

FIG. 22 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIG. 22 , the structure of the semiconductor element 1B may be similar to the structure shown in FIG. 21 . Components in FIG. 22 that are the same as or similar to those in FIG. 21 have been marked with similar reference symbols and repeated descriptions will be omitted.

In the semiconductor device 1B, the redistribution layers 205 can be formed on the fifth through holes 255 respectively and correspondingly. In some embodiments, formation of the redistribution layers 205 may include forming one or more insulating layers (i.e., top passivation layers) using any suitable method (eg, spin coating techniques, sputtering, and similar techniques). 203) and forming conductive components (ie, the redistribution layers 205) in the insulating layer. Formation of the conductive features may include patterning the insulating layer (e.g., using lithography and/or etching processes) and forming the conductive features in the patterned insulating layer (e.g., by using a mask layer to define the shape of the conductive features and using electroless/electrochemical plating process to deposit the seed layer). For example, the first top openings 203O may define the pattern of the redistribution layers 205 . The redistribution layers 205 may be formed in the first top openings 203O.

FIG. 23 shows a method 20 for manufacturing a semiconductor device 1C in the form of a flow chart according to another embodiment of the present disclosure. 24 to 32 illustrate a schematic cross-sectional view of a manufacturing process of a semiconductor device 1C according to another embodiment of the present disclosure.

Referring to FIGS. 23 to 27 , in step S21 , a sacrificial carrier 401 may be provided, and a multi-stacked carrier structure 200 may be temporarily formed on the sacrificial carrier 401 .

Referring to FIG. 24 , an etch stop layer 207 may be formed on the sacrificial carrier 401 . Generally speaking, etch stop layer 207 can provide a mechanism to stop the etching process when forming conductive features. Etch stop layer 207 may preferably include a dielectric material whose etch selectivity differs from the etch selectivity of adjacent layers. For example, etch stop layer 207 may include silicon nitride, silicon nitride carbonitride, silicon oxycarbide, or similar materials, and may be deposited by chemical vapor deposition or plasma-assisted chemical vapor deposition.

Referring to FIG. 24 , the manufacturing technique for forming a first insulating layer 213 on the etch stop layer 207 may include, for example, a deposition process such as chemical vapor deposition or plasma-assisted chemical vapor deposition. The material of the first insulating layer 213 is shown in FIG. 1 , and its description will not be repeated here. The first mask layer 510 may be formed on the first insulation layer 213 . The first mask layer 510 may include a pattern that defines the locations of the plurality of first through holes 215 .

Referring to FIG. 25 , an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and simultaneously form the first via openings 215O. A portion of the etch stop layer 207 may be exposed through the first via openings 215O. During the oxide etching process, the etch rate ratio of the first insulating layer 213 to the etch stop layer 207 may be between about 100:1 to about 1.05:1, between about 15:1 to about 2:1, Or between about 10:1 and about 2:1. After the oxide etching process, the first mask layer 510 can be removed.

Referring to FIG. 26 , a plurality of first through holes 215 may be formed in the first through hole openings 215O. A planarization process such as chemical mechanical polishing may be performed until the top surface of the first insulating layer 213 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. The materials of the first through holes 215 are shown in FIG. 1 , and their description will not be repeated here. The first insulating layer 213 and the first through holes 215 together form the first layer 210 .

Referring to FIG. 27 , the second layer 220 , the third layer 230 , the fourth layer 240 , and the fifth layer 250 can be formed through steps similar to those shown in FIGS. 12 to 19 , and the description thereof will not be repeated here. The first layer 210, the second layer 220, the third layer 230, the fourth layer 240, the fifth layer 250, and the etch stop layer 207 together form the multi-stack carrier structure 200.

Referring to Figures 23, 28, and 29, in step S23, a substrate 101 can be provided, an intermediate dielectric layer 103 can be formed on the substrate 101, and a plurality of conductive pads 105 can be formed in the intermediate dielectric layer 103. And the multi-stack carrier structure 200 can be bonded to the intermediate dielectric layer 103 .

Referring to FIG. 28 , the substrate 101 , the intermediate dielectric layer 103 , and the conductive pads 105 can be formed through steps similar to those shown in FIGS. 1 and 7 , and their description will not be repeated here.

Referring to FIG. 29 , the multi-stack carrier structure 200 may be flipped over and bonded to the intermediate dielectric layer 103 . In some embodiments, the multi-stack carrier structure 200 can be bonded to the intermediate dielectric layer 103 through a hybrid bonding process. In some embodiments, the hybrid bonding process may include thermo-compression bonding, passivation-capping-layer assisted bonding, or surface-activated bonding. In some embodiments, the process pressure of the hybrid bonding process may range from about 100 MPa to about 150 MPa. In some embodiments, the process temperature of the hybrid bonding process may range from approximately room temperature (eg, 25°C) to approximately 400°C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase thermal treatment may be used to lower the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process. In some embodiments, hybrid bonding processes may include, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-metal bonding. -dielectric) engagement. In some embodiments, a thermal annealing process may be performed after the bonding process to enhance dielectric-to-dielectric bonding and cause thermal expansion of metal-to-metal bonding, thereby further improving bonding quality.

Referring to FIG. 30 , before the thinning process of the substrate 101 , in some embodiments, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1:1. , or between approximately 1:1 and approximately 7:5.

Referring to FIGS. 23 and 30 to 32 , in step S25 , the sacrificial carrier 401 may be separated, the substrate 101 may be thinned, and a plurality of second top openings 207O may be formed along the etch stop layer 207 of the multi-stacked carrier structure 200 .

As shown in FIG. 30 , sacrificial carrier 401 may be separated from etch stop layer 207 .

Referring to FIG. 31 , the substrate 101 may be thinned by using wafer grinding, mechanical abrasion, grinding, or similar techniques, or using a chemical removal thinning process such as wet etching. It should be noted that no carrier is required during the thinning process. The multi-stack carrier structure 200 may be used as a temporary carrier to assist in the thinning process of the substrate 101 .

Referring to FIG. 31 , after the thinning process of the substrate 101 , the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 32 , a plurality of second top openings 207O may be formed along the etch stop layer 207 to expose the first through holes 215 respectively and correspondingly. The exposed first through hole 215 may be electrically coupled to a probe for electrical characteristic testing. In other words, the performance of the semiconductor device 1C after the substrate is thinned can be easily analyzed.

FIG. 33 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIG. 33 , the structure of the semiconductor element 1D may be similar to the structure shown in FIG. 31 . The same or similar elements in FIG. 33 as those in FIG. 31 have been marked with similar reference symbols and repeated descriptions are omitted.

In the semiconductor device 1D, the etch stop layer 207 can be completely removed. The top passivation layer 203 can be formed on the first layer 210 through steps similar to those shown in FIG. 19 , and the description thereof will not be repeated here. A plurality of redistribution layers 205 may be formed along the top passivation layer 203 and formed on the first through holes 215 respectively and correspondingly. The redistribution layers 205 can reroute the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. The materials of the redistribution layers 205 are shown in Figure 3, and their description will not be repeated here.

One aspect of the present disclosure provides a semiconductor device, including: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stacked carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the A first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a a second passivation layer, a second insulating layer located on the second passivation layer, and a second through hole, wherein the second through hole is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first through hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, a third insulating layer located on the third passivation layer, and A third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

Another aspect of the present disclosure provides a multi-stacked carrier structure, including: an etch stop layer; a first layer including a first passivation layer located on the etch stop layer, and a first passivation layer located on the first passivation layer. an insulating layer, and a first through hole, wherein the first through hole is disposed along the first passivation layer and the first insulating layer; a second layer located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is disposed along the second passivation layer and the second insulating layer, and electrically connected to the first through hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, and a third insulating layer located on the third passivation layer layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the substrate on the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first through hole, wherein the The first through hole is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second layer includes a second layer located on the first layer. a second passivation layer on the insulating layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is along the second passivation layer and the second insulating layer disposed and electrically connected to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, on the third passivation layer A third insulating layer on the second layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the plurality of The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an intermediate medium electrically layer on the substrate; forming a conductive liner in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial layer from the etch stop layer ; and thinning the substrate.

Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 . Therefore, no carrier is required during the thinning process of substrate 101 . As a result, the manufacturing cost of the semiconductor element 1A can be reduced. Furthermore, after the thinning process, the multi-stack carrier structure 200 may provide an electrical path connected to the device components of the semiconductor device 1A. Therefore, the performance of the semiconductor element 1A can be easily analyzed in the presence of the multi-stacked carrier structure 200 .

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 1C: Semiconductor components 1D: Semiconductor components 10:Method 20:Method 101:Substrate 103: Intermediate dielectric layer 105:Conductive pad 200:Multi-stacked carrier structure 203:Top passivation layer 203O: First top opening 205:Redistribution layer 207: Etch stop layer 207O: Second top opening 210:First floor 211: First passivation layer 213: First insulation layer 215: First through hole 215BS: Bottom surface 215O: First through hole opening 215SW: Side wall 215TS: Top surface 220:Second floor 221: Second passivation layer 223: Second insulation layer 225: Second through hole 225O: Second through hole opening 225TS: Top surface 230:Third floor 231:Third passivation layer 233:Third insulation layer 235:Third through hole 235O: Third through hole opening 235TS: Top surface 240:Fourth floor 241: Fourth passivation layer 243:Fourth insulation layer 245:Fourth through hole 245TS: Top surface 250:Fifth floor 251:Fifth passivation layer 253:Fifth insulation layer 255:Fifth through hole 255TS: Top surface 401:Sacrificial layer 510: First veil layer 510O: First patterned opening 520:Second veil layer 520O: Second patterned opening 530:The third veil layer 530O: Third patterned opening AL: adhesion layer BL: barrier layer FL: filler layer IL: isolation layer SL: seed layer S11: Steps S13: Steps S15: Steps S21: Steps S23: Steps S25: Steps T0:Thickness T1:Thickness T2:Thickness TL:Thickness W0: Width W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width W7: Width W8:width W9: Width W10: Width WC:width Z: direction

Various aspects of this disclosure can be read in conjunction with the following diagrams and detailed descriptions for better understanding. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily exaggerated or reduced for clarity of discussion. FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 shows a close-up cross-sectional view of a first through hole for preparing a semiconductor device according to an embodiment of the present disclosure. 3 to 5 show schematic cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. FIG. 6 shows a method for manufacturing a semiconductor device in the form of a flow chart according to an embodiment of the present disclosure. 7 to 21 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 22 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure. FIG. 23 shows a method of manufacturing a semiconductor device in the form of a flow chart according to another embodiment of the present disclosure. 24 to 32 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 33 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components

101:Substrate

103: Intermediate dielectric layer

105:Conductive pad

200:Multi-stacked carrier structure

203:Top passivation layer

203O: First top opening

210:First floor

211: First passivation layer

213: First insulation layer

215: First through hole

215BS: Bottom surface

215SW: Side wall

215TS: Top surface

220:Second floor

221: Second passivation layer

223: Second insulation layer

225: Second through hole

225TS: Top surface

230:Third floor

231:Third passivation layer

233:Third insulation layer

235:Third through hole

235TS: Top surface

240:Fourth floor

241: Fourth passivation layer

243:Fourth insulation layer

245:Fourth through hole

245TS: Top surface

250:Fifth floor

251:Fifth passivation layer

253:Fifth insulation layer

255:Fifth through hole

255TS: Top surface

T0:Thickness

T1:Thickness

T2:Thickness

TL:Thickness

W0: Width

W1: Width

W2: Width

W3: Width

W4: Width

W5: Width

Z: direction

Claims (10)

A method of manufacturing a semiconductor element, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the intermediate dielectric layer, The first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first through hole, wherein the first through hole is along the The first passivation layer and the first insulating layer are disposed and electrically connected to the conductive pad; a second layer is formed on the first layer, wherein the second layer includes a second layer on the first insulating layer. passivation layer, a second insulating layer located on the second passivation layer, and a second through hole, wherein the second through hole is disposed along the second passivation layer and the second insulating layer and is electrically connected to the a first through hole; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole; wherein the first layer, the second layer , and the third layer together form a multi-stacked carrier structure. The method of manufacturing a semiconductor device as claimed in claim 1, wherein forming the first layer on the intermediate dielectric layer includes: forming the first passivation layer on the intermediate dielectric layer; forming the first insulating layer on the first passivation layer; forming a first mask layer including a first patterned opening on the first insulating layer ; Forming a first via opening along the first insulating layer and the first passivation layer to expose the conductive pad; removing the first mask layer; and forming the first via hole in the first via hole opening. The method of manufacturing a semiconductor device as claimed in claim 2 further includes forming a top passivation layer on the third layer. The method of manufacturing a semiconductor device according to claim 3, wherein the first passivation layer includes an oxide material, the first insulating layer includes an oxide material, and an oxide bonding process is performed to form the first insulating layer. on the first passivation layer. The method of manufacturing a semiconductor device according to claim 4, wherein an oxide etching process is performed to form the first via opening along the first insulating layer and the first passivation layer. The method of manufacturing a semiconductor device as claimed in claim 5, wherein a width of the first patterned opening is greater than a width of the conductive pad. The method of manufacturing a semiconductor device as claimed in claim 6 further includes forming a redistribution layer on the third layer. A method of manufacturing a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer to the sacrificial carrier; forming a multi-stack carrier structure on the etch stop layer, wherein the multi-stack carrier structure includes: a first a layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an intermediate dielectric layer on the substrate; Forming a conductive liner in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; detaching the sacrificial carrier from the etch stop layer; and thinning the substrate. The method of manufacturing a semiconductor device according to claim 8, wherein forming the multi-stacked carrier structure includes: forming the first layer on the etching stop layer, wherein the first layer includes a first layer on the etching stop layer. an insulating layer and a first through hole disposed along the first insulating layer and located on the etch stop layer; forming a second layer on the first layer, wherein the second layer includes a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second through hole along the second passivation layer and the second insulating layer; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and along the third passivation layer and A third through hole of the third insulating layer. The method for manufacturing a semiconductor device as claimed in claim 9, wherein a side wall of the first through hole is tapered and a width of a top surface of the first through hole is smaller than a width of a bottom surface of the first through hole. One width.

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