TWI825906B - Semiconductor device with redistribution plugs - Google Patents

Abstract

The present application discloses a semiconductor device. The semiconductor device includes a first chip including a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad above the first substrate; and a second chip including a dense region and a loose region adjacent to the dense region, upper pads on the first lower bonding pad and the second lower bonding pad, second redistribution layers on the upper pads, and a first redistribution plug and a second redistribution plug respectively and correspondingly on the second redistribution layers. The first redistribution plug is at the dense region and includes a first aspect ratio. The second redistribution plug is at the loose region and includes a second aspect ratio less than the first aspect ratio.

Description

Semiconductor components with rewiring plugs

This application claims priority to U.S. Patent Application Nos. 17/830,482 and 17/830,442 (that is, the priority date is "June 2, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and in particular to a semiconductor device having a rewiring plug.

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. The size of semiconductor devices continues to shrink to meet the growing demand for computing power. However, various problems arise during the downsizing process, and these problems continue to increase. Therefore, challenges remain in improving quality, yield, performance and reliability while reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" Neither should be regarded as any part of the "prior art" of this case and do not constitute prior art of this disclosure.

One aspect of the present disclosure provides a semiconductor device including a first chip and a second chip. The first chip includes: a first substrate, a first redistribution layer located above the first substrate, a first lower bonding pad located on the first redistribution layer, and a first lower bonding pad located above the first substrate and away from the first substrate. a second lower bonding pad of the first lower bonding pad. The second chip includes: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second rewiring layers located on the on the upper pad; and a first redistribution plug and a second redistribution plug, respectively located on the second redistribution layers, wherein the first redistribution plug is located in the dense area and includes a first An aspect ratio, wherein the second redistribution plug is located in the sparse region and includes a second aspect ratio that is smaller than the first aspect ratio.

Another aspect of the present disclosure provides a semiconductor device including a first chip and a second chip. The first chip includes: a first substrate, a first redistribution layer located above the first substrate, a first lower bonding pad located on the first redistribution layer, located above the first substrate and away from the A second lower bonding pad of the first lower bonding pad and a plug structure are located between the second lower bonding pad and the first substrate. The second chip includes: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second rewiring layers located on the on the upper pad; and a first redistribution plug and a second redistribution plug, respectively located on the second redistribution layers, wherein the first redistribution plug is located in the dense area, electrically coupled to the first redistribution layer and includes a first aspect ratio, wherein the second redistribution plug is located in the sparse region, electrically coupled to the plug structure and includes a first aspect ratio smaller than the first aspect ratio. Two aspect ratios.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which provides a first wafer, which includes a first substrate, a first rewiring layer located above the first substrate, and a first redistribution layer located on the first rewiring layer. A first lower bonding pad, and a second lower bonding pad located above the first substrate and away from the first lower bonding pad; a second wafer is provided, which includes: a dense area and a dense area adjacent to the dense area an adjacent sparse area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers located on the upper pads; and a first redistribution plug and a first Dual wiring plugs are respectively located on the second rewiring layers; and the second chip is bonded to the first chip in a face-to-face manner, so that the upper pads and the first lower bonding pads and the second lower bonding pad, wherein the first redistribution plug is located in the dense area and includes a first aspect ratio, and wherein the second redistribution plug is located in the sparse area and includes an aspect ratio smaller than the first aspect ratio A second aspect ratio than one.

Due to the design of the semiconductor device of the present disclosure, the first rewiring plug and the second rewiring plug with different aspect ratios can be used to fine-tune the resistance of different rewiring paths. As a result, the performance of the semiconductor device can be improved. In addition, data signals can be transmitted through the upper pad, the first lower bonding pad and the first redistribution layer without passing through the conductive features, plug structures and functional units of the first chip. As a result, the transmission distance can be shortened, thereby improving the performance of the semiconductor device. In addition, since the transmission distance is shorter, the power consumption of the semiconductor element can be reduced.

The foregoing has provided a rather broad overview of the features and technical advantages of the present disclosure in order to provide a better understanding of the detailed description of the present disclosure that follows. Additional features and advantages that form the subject of the patent claims of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure, and these are, of course, examples only and are not intended to be limiting. In the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, as well as embodiments in which the first feature and the second feature may be formed in direct contact. Additional features enable embodiments in which the first feature and the second feature are not in direct contact. In addition, repeated reference symbols and/or words may be used in various examples of the present disclosure. The purpose of repetition is for simplicity and clarity of explanation, but is not intended to limit the relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "under", "below", "under", "above", "on", etc. are used to conveniently describe the relationship between one component or feature and other components or features. Relative relationships in diagrams. These spatially relative terms are intended to cover different orientations of the component in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when a component or layer is referred to as being "connected" or "coupled" to another component or layer, it can be directly connected or coupled to the other component or layer, or intervening components or layers may be present. layer.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. Unless otherwise stated, these terms are only used to distinguish one component from another component. Thus, for example, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the present disclosure.

Unless otherwise indicated herein, terms such as "same," "identical," "planar" or "coplanar" when referring to orientation, arrangement, location, shape, size, quantity or other measure are not used herein. does not necessarily represent the exact same orientation, layout, location, shape, size, quantity or other measurement, but is intended to cover substantially the same orientation, layout, location, shape within an acceptable range of variations that may occur, for example, due to the manufacturing process , size, quantity or other measure. This article may use the term "substantially" to reflect this meaning. For example, items described as "substantially the same," "substantially identical," or "substantially planar" may be exactly the same, identical, or planar, or may be subject to changes that may occur, such as due to manufacturing processes. Accepts same, equal or flat within range.

In the present disclosure, semiconductor components generally refer to components that can function by utilizing semiconductor characteristics, and electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the category of semiconductor components.

It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of direction Z, and below or down corresponds to the arrow direction opposite to direction Z.

FIG. 1 illustrates a manufacturing method 10 of a semiconductor device 1A according to an embodiment of the present disclosure in the form of a flow chart. 2 to 6 illustrate a part of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure using cross-sectional schematic diagrams.

Referring to FIGS. 1 to 4 , in step S11 , a first substrate 111 may be provided, a first rewiring layer 131 may be formed above the first substrate 111 , and a plug structure 121 may be formed on the first substrate 111 .

Referring to FIG. 2 , in some embodiments, the first substrate 111 may include a semiconductor bulk substrate composed entirely of at least one semiconductor material, a plurality of device components (not shown for clarity), a plurality of dielectric layers ( Not shown for clarity) and a plurality of conductive components (not shown for clarity). For example, the semiconductor bulk substrate may be made of elemental semiconductors (such as silicon or germanium), compound semiconductors (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor) or a combination thereof.

In some embodiments, the first substrate 111 may further include a semiconductor-on-insulator structure, which is composed of an operating substrate, an insulating layer, and a topmost semiconductor material layer from bottom to top. The operating substrate and the topmost semiconductor material layer may be composed of The aforementioned semiconductor bulk substrate is formed of the same material. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulating layer may comprise a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride stacked in any order. The insulating layer may have a thickness of between approximately 10 nm and approximately 200 nm.

It should be noted that the term "about" used to describe quantities of ingredients, compositions or reactants of the present disclosure means changes in values that would occur, for example, through typical measurements and liquid handling processes used to make concentrates or solutions. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make the compositions or practice the methods, or the like. On the one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. On the other hand, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

The plurality of element components may be formed on the first substrate 111, and some parts of the plurality of element components may be formed on the first substrate 111. The plurality of element components may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field Field effect transistors, fin field effect transistors, similar transistors, or combinations thereof.

A plurality of dielectric layers may be formed on the first substrate 111 and cover a plurality of device components. In some embodiments, the plurality of dielectric layers may be made of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low-k dielectric materials, similar materials, or the like. formed by combination. Low-k dielectric materials may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, low-k dielectric materials may have a dielectric constant less than 2.0. The multilayer dielectric layer may be formed by a deposition process, such as a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or a similar deposition process. A planarization process may be performed after the deposition process to remove excess material and provide a generally flat surface for subsequent process steps.

The plurality of conductive components may include multiple interconnect layers, multiple conductive vias, and multiple conductive pads. The interconnect layers may be separated from each other and may be horizontally disposed along the direction Z within the plurality of dielectric layers. In this embodiment, the topmost interconnect layer serves as a conductive pad. The conductive vias can connect adjacent interconnect layers, adjacent component structures and interconnect layers, and adjacent conductive pads and interconnect layers along the direction Z. In some embodiments, conductive vias may improve heat dissipation and may provide structural support. In some embodiments, the plurality of conductive components may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen Titanium oxide), transition metal aluminides, or combinations thereof. The plurality of conductive features may be formed during the formation of the plurality of dielectric layers.

In some embodiments, a plurality of component components and a plurality of conductive components may together form multiple functional units. In the description of this disclosure, a functional unit generally refers to a circuit related to a function, which is divided into different units based on functional purposes. In some embodiments, functional units may typically be highly complex circuits, such as processor cores or accelerator units. In some other embodiments, the complexity and functionality of a functional unit may be more complex or simpler.

Referring to FIG. 2 , a bottom dielectric layer 115 may be formed on the first substrate 111 . In some embodiments, bottom dielectric layer 115 may be made of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, similar materials, or formed by its combination. The bottom dielectric layer 115 may be formed by a deposition process, such as a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or a similar deposition process. A planarization process may be performed after the deposition process to remove excess material and provide a generally flat surface for subsequent process steps.

Referring to FIG. 2 , a bottom plug 123 may be formed along the bottom dielectric layer 115 and electrically coupled to a corresponding one of the device components in the first substrate 111 . In other words, the bottom plug 123 may be combined with the functional unit within the first substrate 111 . In some embodiments, bottom plug 123 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, Titanium nitride), transition metal aluminides, or combinations thereof. In this embodiment, the bottom plug 123 may be formed of an alloy of aluminum and copper.

Referring to FIG. 2 , a contact pad 125 may be formed on the bottom plug 123 . The width W2 of the pad 125 may be greater than the width W1 of the bottom plug 123 . In some embodiments, the pads 125 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen Titanium oxide), transition metal aluminides, or combinations thereof. In some embodiments, the pads 125 may be formed by performing a blanket deposition process and subsequent patterning and etching processes.

Referring to FIG. 3 , a top dielectric layer 117 can be formed on the bottom dielectric layer 115 and covers the pads 125 . The top dielectric layer 117 may be formed of the same material as the bottom dielectric layer 115 and will not be described again here. The top dielectric layer 117 may be formed by a deposition process, such as a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or a similar deposition process. A planarization process may be performed after the deposition process to remove excess material and provide a generally flat surface for subsequent process steps. The bottom dielectric layer 115 and the top dielectric layer 117 may together form a first interlayer dielectric layer 113 .

Referring to FIG. 3 , a first redistribution layer 131 may be formed on the first interlayer dielectric layer 113 . In some embodiments, the first redistribution layer 131 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (such as titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, the first redistribution layer 131 may be formed by performing a blanket deposition process and subsequent patterning and etching processes. In some embodiments, the first redistribution layer 131 is not electrically coupled to any functional unit in the first substrate 111 .

Referring to FIG. 4 , a first bottom passivation layer 141 may be formed on the first interlayer dielectric layer 113 . In some embodiments, the first bottom passivation layer 141 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, silicon carbon nitride, or combinations thereof. In some embodiments, the bottom passivation layer 141 may be made of, for example, polyimide, polybenzoxazole, benzocyclobutene, epoxy resin, silicone resin, acrylate, nano-filled phenolic resin, siloxane , fluorinated polymers, polynorbornene, or similar materials. A planarization process may be performed until the top surface 131TS of the first redistribution layer 131 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps.

It should be noted that in the description of the present disclosure, a surface of the component (or component) located at the highest vertical height along the direction Z is called a top surface of the component (or component). The surface of a component (or component) located at the lowest vertical height along direction Z is called a bottom surface of the component (or component).

Referring to FIG. 4 , a top plug 127 may be formed along the first bottom passivation layer 141 and extends to the top dielectric layer 117 and is located on the pad 125 . The width W3 of the top plug 127 may be greater than the width W1 of the bottom plug 123 , and the width W3 of the top plug 127 may be less than the width W2 of the pad 125 . In some embodiments, the top plug 127 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, Titanium nitride), transition metal aluminides, or combinations thereof. A patterning process may be performed to cover the first redistribution layer 131 with a mask layer (not shown for the sake of clarity), thereby forming a plug opening (not shown for the sake of clarity) to expose the contact pad 125 part. A subsequent deposition process may be performed to deposit the above material to fill the plug opening. A planarization process may then be performed until the top surface 131TS of the first redistribution layer 131 is exposed to remove excess material and simultaneously form the top plug 127 . In this embodiment, top plug 127 may include tungsten.

The bottom plug 123 , the bonding pad 125 and the top plug 127 may together form a plug structure 121 , and the plug structure 121 may be electrically coupled to a corresponding one of the component components in the first substrate 111 . In other words, the plug structure 121 can be combined with the functional unit within the first substrate 111 .

Referring to Figures 1, 5 and 6, in step S13, a first lower bonding pad 151 can be formed on the first redistribution layer 131, and a second lower bonding pad 153 can be formed on the plug structure 121. To form the first wafer 100 .

Referring to FIG. 5 , a first top passivation layer 143 may be formed on the first bottom passivation layer 141 . In some embodiments, the first top passivation layer 143 may be made of, for example, polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto Build-up Film, solder mask, or the like. Made of polymeric materials. Polymeric materials such as polyimides can have many attractive properties, such as the ability to fill high aspect ratio openings, a relatively low dielectric constant (approximately 3.2), a simple deposition process, and reduced sharp features in underlying layers. or steps, and resistant to high temperatures after curing. In some embodiments, the first top passivation layer 143 may be formed by, for example, spin coating, lamination, deposition, or the like. Deposition may include chemical vapor deposition, such as plasma enhanced chemical vapor deposition. The process temperature of plasma enhanced chemical vapor deposition can be between about 350°C and about 450°C, and the process pressure of plasma enhanced chemical vapor deposition can be between about 2.0 Torr and about 2.8 Torr. The vapor deposition process time may be between about 8 seconds and about 12 seconds.

Referring to FIG. 5 , in some embodiments, a plurality of pad openings 145 and 147 may be formed along the first top passivation layer 143 , the first redistribution layer 131 may be exposed through the pad openings 145 , and the top plug 127 may be exposed through the pad openings. 147 exposed. The plurality of pad openings 145 and 147 can be formed through a photolithography process and a subsequent etching process. In some embodiments, the etching process may be an anisotropic dry etching process using argon and tetrafluoromethane as etchants. The process temperature of the etching process may be between about 120°C and about 160°C. The process of the etching process may be The pressure may be between about 0.3 Torr and about 0.4 Torr, and the etching process time may be between about 33 seconds and about 39 seconds. Alternatively, in some embodiments, the etching process may be an anisotropic dry etching process using helium and nitrogen trifluoride as etchants, and the process temperature of the etching process may be between about 80°C and about 100°C. The process pressure of the process may be between about 1.2 Torr and about 1.3 Torr, and the process time of the etching process may be between about 20 seconds and about 30 seconds.

Referring to FIG. 6 , a plurality of pad openings 145 and 147 may be filled with conductive material to form first lower bonding pads 151 and second lower bonding pads 153 respectively. In some embodiments, the conductive material may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen titanium oxide), transition metal aluminides, or combinations thereof. In some embodiments, the plurality of pad openings 145 and 147 can be sequentially filled with conductive material through sputtering or electroless plating. For example, when aluminum-copper material is used as the sputtering source and the plurality of pad openings 145 and 147 are filled by sputtering, the sputtering process temperature can be between about 100°C and about 400°C, and the sputtering process pressure Can be between approximately 1 mTorr and approximately 100 mTorr. As another example, the plurality of pad openings 145 and 147 can be filled through a plating process using a plating solution. The plating solution may contain copper sulfate, copper methanesulfonate, copper gluconate, copper sulfamate, copper nitrate, copper phosphate or copper chloride. The pH value of the electroplating solution can be between about 2 and about 6 or between about 3 and about 5, and the process temperature of the electroplating process can be maintained between about 40°C and about 75°C or between about 50°C and about 70°C. between.

Referring to FIG. 6 , a first lower bonding pad 151 may be formed in the pad opening 145 and may be electrically connected to the first redistribution layer 131 . It should be noted that the first lower bonding pad 151 is not electrically coupled to any functional unit in the first substrate 111 . The second lower bonding pad 153 can be formed in the pad opening 147 and can be electrically connected to the top plug 127 , that is, the second lower bonding pad 153 can be combined with the functional unit in the first substrate 111 through the plug structure 121 .

Referring to FIG. 6 , the first substrate 111 , the first dielectric layer 113 , the plug structure 121 , the first redistribution layer 131 , the first bottom passivation layer 141 , the first top passivation layer 143 , the first lower bonding pad 151 and The second lower bond pads 153 together form the first wafer 100 . In some embodiments, the first die 100 may be configured as a logic die. The first wafer 100 may include a front surface 100FS. It should be noted that in the description of the present disclosure, the term "front" surface refers to the technical term for the main surface of the structure on which device components and conductive features are formed. In this embodiment, the front surface 100FS of the first wafer 100 may be the top surface of the first top passivation layer 143 .

FIG. 7 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 8 is a schematic cross-sectional view along line A-A' in Fig. 7 .

Referring to Figures 1, 7 and 8, in step S15, a second substrate 311 may be provided, which includes a dense region DR and a sparse region LR. A plurality of storage units 321 may be formed above the second substrate 311, and may be formed on A plurality of lower pads 341 are formed above the storage units 321 .

Referring to FIGS. 7 and 8 , a second substrate 311 may be provided, and the second substrate 311 may include a dense region DR and a sparse region LR adjacent to the dense region DR.

Referring to FIGS. 7 and 8 , in some embodiments, the second substrate 311 may be a semiconductor bulk substrate composed entirely of at least one semiconductor material. The semiconductor bulk substrate does not include any dielectric, insulating layer or conductive features. For example, the semiconductor bulk substrate may be made of elemental semiconductors (such as silicon or germanium), compound semiconductors (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor) or a combination thereof.

In some embodiments, the second substrate 311 may include a semiconductor-on-insulator structure, which is composed of an operating substrate, an insulating layer, and a topmost semiconductor material layer from bottom to top. The operating substrate and the topmost semiconductor material layer may be composed of the same components as described above. The semiconductor bulk substrate is formed of the same material. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulating layer may comprise a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride stacked in any order. The insulating layer may have a thickness of between approximately 10 nm and 200 nm.

A plurality of device components (not shown for clarity) may be formed on the second substrate 311. Some portions of the device components may be formed on the second substrate 311. The plurality of device components may be transistors, such as complementary metal oxide Physical semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, similar transistors, or combinations thereof.

Referring to FIGS. 7 and 8 , a second bottom interlayer dielectric layer 313 may be formed on the second substrate 311 and cover a plurality of device components. In some embodiments, the second bottom interlayer dielectric layer 313 may be a stacked structure. The second bottom interlayer dielectric layer 313 may include a plurality of insulator sub-layers (not shown for clarity), and each insulator sub-layer may have a thickness between about 0.5 microns and about 3.0 microns. The plurality of insulator layers may be formed from, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low-k dielectric materials, similar materials, or combinations thereof. The plurality of insulator layers may be formed of different materials, but is not limited thereto.

A plurality of conductive features (not shown for clarity) may be formed in the second bottom interlayer dielectric layer 313 , and the plurality of conductive features may include multiple interconnect layers and multiple conductive vias. The interconnect layers may be separated from each other and may be horizontally disposed in the second bottom interlayer dielectric layer 313 along the direction Z. The conductive vias can connect adjacent interconnect layers along the direction Z and adjacent component components and interconnect layers. In some embodiments, conductive vias may improve heat dissipation and may provide structural support. In some embodiments, the plurality of conductive components may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen Titanium oxide), transition metal aluminides, or combinations thereof. A plurality of conductive features may be formed during formation of the second bottom interlayer dielectric layer 313 .

Referring to FIGS. 7 and 8 , a plurality of memory cells 321 may be formed in the second bottom interlayer dielectric layer 313 . In some embodiments, the plurality of storage cells 321 may be configured as a capacitor array. In some embodiments, the plurality of storage cells 321 may be configured as a floating array. In some embodiments, the density of the plurality of storage cells 321 above the dense region DR may be greater than the density of the plurality of storage cells 321 above the sparse region LR. The density of the plurality of storage cells 321 can be defined as the number of the plurality of storage cells 321 divided by a specific surface area containing the plurality of storage cells 321 . In some embodiments, the number of storage units 321 above the sparse region LR may be zero.

Referring to FIGS. 7 and 8 , a plurality of interconnect layers 315 may be formed in the second bottom interlayer dielectric layer 313 , and the plurality of interconnect layers 315 may be electrically coupled to the plurality of storage units 321 and the plurality of second devices respectively. component. In some embodiments, interconnect layer 315 may be considered part of a plurality of conductive features.

Referring to FIGS. 7 and 8 , a second bottom passivation layer 331 may be formed on the second bottom interlayer dielectric layer 313 . In some embodiments, the second bottom passivation layer 331 may be formed of a polymeric material such as polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto laminate film, solder mask, or similar materials. . Polymeric materials such as polyimides can have many attractive properties, such as the ability to fill high aspect ratio openings, a relatively low dielectric constant (approximately 3.2), a simple deposition process, and reduced sharp features in underlying layers. or steps, and resistant to high temperatures after curing. In some embodiments, the second bottom passivation layer 331 may be formed by, for example, spin coating, lamination, deposition, or similar methods. Deposition may include chemical vapor deposition, such as plasma enhanced chemical vapor deposition. The process temperature of plasma enhanced chemical vapor deposition can be between about 350°C and about 450°C, and the process pressure of plasma enhanced chemical vapor deposition can be between about 2.0 Torr and about 2.8 Torr. The vapor deposition process time may be between about 8 seconds and about 12 seconds.

Referring to FIGS. 7 and 8 , a plurality of lower pads 341 may be formed on a plurality of interconnect layers 315 respectively. In some embodiments, a plurality of pad openings (not shown in FIGS. 7 and 8 ) may be formed in the second bottom passivation layer 331 , and a conductive material may be formed to fill the pad openings, thereby forming a plurality of lower pads 341 . The pad openings can be formed through a photolithography process and a subsequent etching process. In some embodiments, the etching process may be an anisotropic dry etching process using argon and tetrafluoromethane as etchants. The process temperature of the etching process may be between about 120°C and about 160°C. The process of the etching process may be The pressure may be between about 0.3 Torr and about 0.4 Torr, and the etching process time may be between about 33 seconds and about 39 seconds. Alternatively, in some embodiments, the etching process may be an anisotropic dry etching process using helium and nitrogen trifluoride as etchants, and the process temperature of the etching process may be between about 80°C and about 100°C. The process pressure of the process may be between about 1.2 Torr and about 1.3 Torr, and the process time of the etching process may be between about 20 seconds and about 30 seconds. In some embodiments, the conductive material may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen titanium oxide), transition metal aluminides, or combinations thereof.

In some embodiments, the pad openings may be sequentially filled with conductive material by sputtering or electroless plating. For example, when aluminum-copper material is used as the sputtering source and the pad opening is filled by sputtering, the sputtering process temperature can be between about 100°C and about 400°C, and the sputtering process pressure can be between about 1 mTorr and approximately 100 mTorr. As another example, the pad opening may be filled by a plating process using a plating solution. The plating solution may contain copper sulfate, copper methanesulfonate, copper gluconate, copper sulfamate, copper nitrate, copper phosphate or copper chloride. The pH value of the electroplating solution can be between about 2 and about 6 or between about 3 and about 5, and the process temperature of the electroplating process can be maintained between about 40°C and about 75°C or between about 50°C and about 70°C. between.

FIG. 9 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 10 is a schematic cross-sectional view along line A-A' in Fig. 9 .

Referring to FIGS. 1, 9 and 10, in step S17, a plurality of first rewiring plugs 351 and a plurality of second rewiring plugs 353 may be formed on the plurality of lower pads 341, and a plurality of rewiring plugs 353 may be formed above the second substrate 311. The first support plug 361 and the plurality of second support plugs 363.

Referring to FIGS. 9 and 10 , a second top interlayer dielectric layer 317 may be formed on the third bottom passivation layer 331 . In some embodiments, the second top interlayer dielectric layer 317 may be made of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like. materials, or combinations thereof.

Referring to FIGS. 9 and 10 , a plurality of first redistribution plugs 351 , a plurality of second redistribution plugs 353 , a plurality of first support plugs 361 and a plurality of second support plugs 363 may be formed on the second top interlayer dielectric layer. 317, for the sake of simplicity, clarity and ease of explanation, only a first rewiring plug 351, a second rewiring plug 353, a first support plug 361 and a second support plug 363 are described.

Referring to FIGS. 9 and 10 , the first redistribution plug 351 may be formed on the lower pad 341 above the dense area DR, that is, the first redistribution plug 351 may be formed above the dense area DR. In some embodiments, the profile of the first rerouting plug 351 may be aligned with the lower pad 341 above the dense region DR. The second redistribution plug 353 may be formed on the lower pad 341 above the sparse region LR. That is, the second redistribution plug 353 may be formed above the sparse region LR. In some embodiments, the profile of the second rerouting plug 353 may be aligned with the lower pad 341 above the sparse region LR.

Referring to FIGS. 9 and 10 , in some embodiments, the first rewiring plug 351 and the second rewiring plug 353 may be formed separately. For example, the first redistribution plug 351 may be formed by electroplating and may be composed of, for example, copper, while the second redistribution plug 353 may be formed by sputtering or chemical vapor deposition and may be composed of, for example, aluminum.

In some embodiments, the width W4 of the first reroute plug 351 may be smaller than the width W5 of the second reroute plug 353 . In some embodiments, the aspect ratio of the first reroute plug 351 may be greater than the aspect ratio of the second reroute plug 353 . The aspect ratio is defined as the height of the reroute plug divided by the width of the reroute plug.

In some embodiments, the first support plug 361 and the second support plug 363 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (eg, tantalum carbide, titanium carbide, carbide Tantalum (magnesium), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. A patterning process may be performed to cover the first redistribution plug 351 and the second redistribution plug 353 with a mask layer (not shown for clarity), and then formed along the second top interlayer dielectric layer 317 Multiple plug openings (not shown for clarity). A subsequent deposition process may be performed to deposit the above material to fill the plug opening. A planarization process may then be performed until the top surface of the second top interlayer dielectric layer 317 is exposed to remove excess material and simultaneously form the first support plug 361 and the second support plug 363 .

In some embodiments, a distance D1 between a pair of adjacent first redistribution plugs 351 and first support plugs 361 above the dense area DR may be approximately the same as a distance D1 above a pair of adjacent dense areas DR. A distance D2 between a support plug 361 and a second support plug 363 above the dense area DR. In some embodiments, the distance D1 between a pair of adjacent first rewiring plugs 351 and the first support plugs 361 above the dense area DR may be different from a pair of adjacent first supports above the dense area DR. The distance D2 between the plug 361 and the second support plug 363 above the dense area DR.

In some embodiments, a distance D3 between a pair of adjacent second redistribution plugs 353 and the first support plugs 361 above the sparse region LR may be approximately the same as a distance D3 above a pair of adjacent sparse regions LR. A distance D4 between a support plug 361 and a second support plug 363 above the sparse area LR. In some embodiments, the distance D3 between an adjacent pair of second rewiring plugs 353 and the first support plugs 361 above the sparse region LR may be different from a pair of adjacent first supports above the sparse region LR. The distance D4 between the plug 361 and the second support plug 363 above the sparse area LR.

In some embodiments, a distance D1 between a pair of adjacent first redistribution plugs 351 and first support plugs 361 above the dense region DR may be approximately the same as a pair of adjacent second rewiring plugs 351 above the sparse region LR. The distance D3 between the rewiring plug 353 and the first support plug 361 is rerouted. In some embodiments, a distance D1 between a pair of adjacent first rewiring plugs 351 and first support plugs 361 above the dense region DR may be different from a pair of adjacent second rewiring plugs 351 above the sparse region LR. The distance D3 between the wiring plug 353 and the first support plug 361.

FIG. 11 is a schematic plan view illustrating a semiconductor device in an intermediate stage according to an embodiment of the present disclosure, and FIG. 12 is a cross-sectional schematic view along line A-A’ in FIG. 11 .

Referring to Figures 1, 11 and 12, in step S19, a plurality of first rewiring plugs 351, a plurality of second rewiring plugs 353, a plurality of first support plugs 361 and a plurality of second support plugs 363 can be A plurality of second rewiring layers 355 are formed.

Referring to FIGS. 11 and 12 , a plurality of second redistribution layers 355 may be formed on the second top interlayer dielectric layer 317 . For simplicity, clarity, and ease of explanation, only a second rewiring layer 355 above the dense region DR and a second rewiring layer 355 above the sparse region LR are described. The second redistribution layer 355 above the dense area DR may be formed on the first redistribution plug 351, the first support plug 361 above the dense area DR, and the second support plug 363 above the dense area DR. The first support plug 361 above the dense area DR and the second support plug 363 above the dense area DR may be floating.

The second redistribution layer 355 above the sparse region LR may be formed on the second redistribution plug 353, the first support plug 361 above the sparse region LR, and the second support plug 363 above the sparse region LR. The first support plug 361 above the sparse area LR and the second support plug 363 above the sparse area LR may be floating.

The first support plug 361 and the second support plug 363 can provide additional support during the subsequent bonding process that will be described later. The process of forming the second redistribution layer 355 may be similar to the first redistribution layer 131 and will not be described again here.

FIG. 13 is a schematic plan view illustrating a semiconductor device in an intermediate stage of an embodiment of the present disclosure, and FIG. 14 is a cross-sectional schematic view along the line A-A’ in FIG. 13 .

Referring to FIGS. 11 , 13 and 14 , in step S21 , a plurality of upper pads 343 may be formed on a plurality of second redistribution layers 355 to form a second chip 300 .

Referring to FIGS. 13 and 14 , a second top passivation layer 333 may be formed on the second top interlayer dielectric layer 317 to cover the plurality of second redistribution layers 355 . The plurality of upper pads 343 may be formed on the plurality of second redistribution layers 355 respectively. In some embodiments, a plurality of upper pads 343 may be formed above a plurality of second support plugs 363 respectively.

The second substrate 311, the second bottom interlayer dielectric layer 313, the plurality of interconnect layers 315, the second top interlayer dielectric layer 317, the plurality of memory cells 321, the second bottom passivation layer 331, the plurality of lower pads 341, the plurality of first Rewiring plugs 351, second rewiring plugs 353, first support plugs 361, second support plugs 363, second rewiring layers 355, second top passivation layers 333, and upper pads 343 Together, the second wafer 300 is formed. The second wafer 300 may include a front surface 300FS. In this embodiment, the front surface 300FS of the second wafer 300 may be the top surface of the second top passivation layer 333 .

In some embodiments, the second die 300 may be configured as a memory die, and the upper pads 343 may be configured as input/outputs of the second die 300 . The plurality of first rewiring plugs 351 , the plurality of second rewiring plugs 353 and the plurality of second rewiring layers 355 can be combined with the plurality of upper pads 343 to transmit signals of the plurality of storage units 321 to the plurality of upper pads 343 .

FIG. 15 illustrates a part of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure in a schematic cross-sectional view.

Referring to FIGS. 1 and 15 , in step S23 , the second wafer 300 may be bonded to the first wafer 100 to form the semiconductor element 1A.

Referring to FIG. 15 , the second wafer 300 can be bonded to the first wafer 100 in a face-to-face configuration through a hybrid bonding process, and the front surface 300FS of the second wafer 300 can be bonded to the front surface 100FS of the first wafer 100 . After the hybrid bonding process, the second chip 300 (configured as a memory chip) and the first chip 100 (configured as a logic chip) may together form an integrated circuit package. For example, the upper pad 343 located in the dense area DR may be disposed on the second lower bonding pad 153 , and the upper pad 343 located in the sparse area LR may be disposed on the first lower bonding pad 151 .

In some embodiments, the hybrid bonding process may be, for example, thermocompression bonding, passivation capping assisted bonding, or surface activation bonding. For example, the hybrid bonding process may include activating the exposed surfaces of the second top passivation layer 333 and the first top passivation layer 143 of the second wafer 300 (eg, during a plasma process), cleaning the second top passivation after activation. layer 333 and the first top passivation layer 143, bringing the activated surface of the second top passivation layer 333 into contact with the activated surface of the first top passivation layer 143, and performing a thermal annealing process to strengthen the connection between the second top passivation layer 333 and the first top passivation layer 333. The bond between the top passivation layer 143.

In some embodiments, the process pressure of the hybrid bonding process may be between about 100 MPa and about 150 MPa. In some embodiments, the process temperature of the hybrid bonding process may be between approximately room temperature (eg, 25°C) and approximately 400°C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor-phase heat treatment may be used to lower the process temperature or shorten the time of the hybrid bonding process.

In some embodiments, hybrid bonding processes may include dielectric-dielectric bonding, metal-metal bonding, and metal-dielectric bonding. The dielectric-dielectric bond may originate from the bond between the second top passivation layer 333 and the first top passivation layer 143 and the metal-metal bond may originate between the first lower bond pad 151 and the upper pad 343 and The bonding of the second lower bonding pad 153 and the upper pad 343 , the metal-dielectric bonding may originate between the first top passivation layer 143 and the plurality of upper pads 343 and the second top passivation layer 333 and the first lower bonding pad 151 and/or the bonding between the second lower bonding pads 153 .

In some embodiments, when the first top passivation layer 143 and the second top passivation layer 333 are formed of, for example, silicon oxide or silicon nitride, the bonding between the first top passivation layer 143 and the second top passivation layer 333 may be based on Hydrophilic conjugation mechanism. Hydrophilic surface modification may be applied to the first top passivation layer 143 and the second top passivation layer 333 prior to bonding.

In some embodiments, when the first top passivation layer 143 and the second top passivation layer 333 are formed from polymer adhesives such as polyimide, benzocyclobutene, and polybenzoxazole, the first top passivation layer The bonding between layer 143 and second top passivation layer 333 may be based on thermocompression bonding.

In some embodiments, a thermal annealing process may be performed after the bonding process to enhance the bonding between dielectrics and cause thermal expansion of metal-to-metal bonding, thereby further improving bonding quality.

The first rewiring plug 351 and the second rewiring plug 353 with different aspect ratios and/or materials can be used to fine-tune the resistance of different rewiring paths, and as a result, the performance of the semiconductor device 1A can be improved.

16 to 21 illustrate semiconductor devices 1B, 1C, 1D, 1E, 1F and 1G according to some embodiments of the present disclosure in schematic cross-sectional views.

Referring to FIG. 16 , the semiconductor element 1B may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 16 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 16 , the upper pad 343 located in the sparse region LR may be disposed on the second lower bonding pad 153 . That is, the upper pad 343 located in the sparse region LR may be combined with the functional unit of the first wafer 100 via the plug structure 121 . Signals (eg, control signals) may be transmitted from the first chip 100 to the plurality of storage units 321 via the plug structure 121 , the second lower bonding pad 153 , and the upper pad 343 located in the sparse region LR. The upper pad 343 located in the dense area DR may be disposed on the first lower bonding pad 151 . Signals (such as data signals) can be transmitted from the plurality of storage units 321 to the external reading unit via the upper pad 343 located in the dense area DR, the first lower bonding pad 151 and the first redistribution layer 131 without passing through conductive features, interposers, etc. The plug structure 121 and the functional unit of the first wafer 100.

Referring to FIG. 17 , the semiconductor element 1C may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 17 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 17 , the semiconductor device 1C may include a device disposed between the first top passivation layer 143 and the second lower bonding pad 153 , between the top plug 127 and the second lower bonding pad 153 , and between the second lower bonding pad 153 and the second lower bonding pad 153 . A first barrier layer 161 between a bottom passivation layer 141. The first barrier layer 161 may be formed of, for example, titanium, titanium nitride, or a combination thereof. The first barrier layer 161 may be formed by, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

Referring to FIG. 18 , the semiconductor element 1D may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 18 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 18 , the semiconductor device 1D may include a semiconductor device disposed between the first bottom passivation layer 141 and the top plug 127 , between the top dielectric layer 117 and the top plug 127 , and between the contact pad 125 and the top plug 127 . a second barrier layer 163. The second barrier layer 163 may be formed of, for example, titanium, titanium nitride, or a combination thereof. The second barrier layer 163 may be formed by, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

Referring to FIG. 19 , the semiconductor element 1E may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 19 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 19 , the semiconductor device 1E may include a semiconductor device disposed between the first bottom passivation layer 141 and the top plug 127 , between the top dielectric layer 117 and the top plug 127 , and between the contact pad 125 and the top plug 127 . a second barrier layer 163. In some embodiments, the second barrier layer 163 may have a U-shaped cross-sectional profile extending toward the pad 125 . The top surface of the second barrier layer 163 and the top surface of the top plug 127 may be recessed to a longitudinal height VL1 between the top surface 131TS and the bottom surface 131BS of the first redistribution layer 131 .

Referring to FIG. 19 , a third barrier layer 165 is compliantly disposed between the second lower bonding pad 153 and the top plug 127 . In some embodiments, the third barrier layer 165 may also include a U-shaped protrusion 165-1 extending toward the top plug 127, in other words, the bottom surface 165BS of the U-shaped protrusion 165-1 (i.e., the third barrier The bottom surface of the layer 165 ) may be lower than the top surface 131TS of the first redistribution layer 131 and higher than the bottom surface 131BS of the first redistribution layer 131 . Therefore, the second lower bonding pad 153 may also include a protrusion 155 extending toward the top plug 127 and disposed within the recess formed by the U-shaped protrusion 165 - 1 . In some embodiments, the bottom surface 165BS of the U-shaped protrusion 165-1 may be rounded. In some embodiments, bottom surface 165BS of U-shaped protrusion 165-1 may be generally flat.

Referring to FIG. 19 , a fourth barrier layer 167 is compliantly disposed between the first lower bonding pad 151 and the first redistribution layer 131 . The third barrier layer 165 and the fourth barrier layer 167 may be formed of the same material as the first fourth barrier layer 161 and will not be described again here.

Referring to FIG. 20 , the semiconductor element 1F may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 20 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 20 , a molding layer 611 may be formed on the first wafer 100 to cover the second wafer 300 . In some embodiments, the molding layer 611 may be formed of a molding material such as polybenzoxazole, polyimide, benzocyclobutene, epoxy resin laminate, or ammonium bifluoride, and may be formed by compression molding. , transfer molding, liquid sealant molding or the like to form the molding layer 611 . For example, the molding material can be dispensed in liquid form and then a curing process is performed to solidify the molding material. The molding material may be formed to overflow the first wafer 100 so that the molding material may completely cover the second wafer 300 . The first wafer 100, the second wafer 300 and the molding layer 611 together constitute the semiconductor element 1F.

Referring to FIG. 21 , the semiconductor element 1G may have a structure similar to that illustrated in FIG. 15 . Components in FIG. 21 that are the same as or similar to those in FIG. 15 are marked with similar numbers and repeated descriptions are omitted.

Referring to FIG. 21 , the first wafer 100 may include another set of plug structures 121 , a first redistribution layer 131 , a first lower bonding pad 151 and a second lower bonding pad 153 , as shown on the left side of the first wafer 100 . The second chip 300 can be disposed on the first chip 100 in the same manner as illustrated in FIG. 15 , which will not be described again here.

Referring to FIG. 21 , a third wafer 500 may be provided similar to the second wafer 300 illustrated in FIGS. 7 to 14 , which will not be described again here. The third wafer 500 may be bonded to the left side of the first wafer 100 in a process similar to that illustrated in FIG. 15 , which will not be described again here.

One aspect of the present disclosure provides a semiconductor device including a first chip and a second chip. The first chip includes: a first substrate, a first redistribution layer located above the first substrate, a first lower bonding pad located on the first redistribution layer, and a first lower bonding pad located above the first substrate and away from the first substrate. a second lower bonding pad of the first lower bonding pad. The second chip includes: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second rewiring layers located on the on the upper pad; and a first redistribution plug and a second redistribution plug, respectively located on the second redistribution layers, wherein the first redistribution plug is located in the dense area and includes a first Aspect ratio, wherein the second redistribution plug is located in the sparse region and includes a second aspect ratio smaller than the first aspect ratio.

Another aspect of the present disclosure provides a semiconductor device including a first chip and a second chip. The first chip includes: a first substrate, a first redistribution layer located above the first substrate, a first lower bonding pad located on the first redistribution layer, located above the first substrate and away from the A second lower bonding pad of the first lower bonding pad and a plug structure are located between the second lower bonding pad and the first substrate. The second chip includes: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second rewiring layers located on the on the upper pad; and a first redistribution plug and a second redistribution plug, respectively located on the second redistribution layers, wherein the first redistribution plug is located in the dense area, electrically coupled to the first redistribution layer and includes a first aspect ratio, wherein the second redistribution plug is located in the sparse region, electrically coupled to the plug structure and includes a first aspect ratio smaller than the first aspect ratio. Two aspect ratios.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which provides a first wafer, which includes a first substrate, a first rewiring layer located above the first substrate, and a first redistribution layer located on the first rewiring layer. A first lower bonding pad, and a second lower bonding pad located above the first substrate and away from the first lower bonding pad; a second wafer is provided, which includes: a dense area and a dense area adjacent to the dense area an adjacent sparse area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers located on the upper pads; and a first redistribution plug and a first Dual wiring plugs are respectively located on the second rewiring layers; and the second chip is bonded to the first chip in a face-to-face manner, so that the upper pads and the first lower bonding pads and the second lower bonding pad, wherein the first redistribution plug is located in the dense area and includes a first aspect ratio, and wherein the second redistribution plug is located in the sparse area and includes an aspect ratio smaller than the first aspect ratio A second aspect ratio than one.

Due to the design of the semiconductor device of the present disclosure, the first rewiring plug 351 and the second rewiring plug 353 with different aspect ratios can be used to fine-tune the resistance of different rewiring paths. As a result, the performance of the semiconductor device 1A can be improved. In addition, data signals can be transmitted through the upper pad 343 , the first lower bonding pad 151 and the first redistribution layer 131 without passing through the conductive features, plug structures 121 and functional units of the first chip 100 . As a result, the transmission distance can be shortened, thereby improving the performance of the semiconductor element 1A. In addition, since the transmission distance is shorter, the power consumption of the semiconductor element 1A can be reduced.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes discussed above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. A person of ordinary skill in the art can understand from the disclosure of this disclosure that existing or future development processes that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Machinery, manufacture, composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 1C: Semiconductor components 1D: Semiconductor components 1E: Semiconductor components 1F: Semiconductor components 1G: Semiconductor components 10:Method 100:First chip 100FS: Front surface 111: First substrate 113: First intermediate dielectric layer 115: Bottom dielectric layer 117:Top dielectric layer 121: Plug structure 123: Bottom plug 125:pad 127: Top plug 131: First rewiring layer 131TS: Top surface 131BS: Bottom surface 141: First bottom passivation layer 143: First top passivation layer 145: Pad opening 147: Pad opening 151: First lower joint pad 153: Second lower bonding pad 155:Protrusion 161: First barrier layer 163: Second barrier layer 165:Third barrier layer 165-1:U-shaped protrusion 167: The fourth barrier layer 165BS: Bottom surface 300: Second chip 300FS: Front surface 311: Second substrate 313: Second bottom interlayer dielectric layer 315: Inner wiring layer 317: Second top interlayer dielectric layer 321:Storage unit 331: Second bottom passivation layer 333: Second top passivation layer 341:Lower pad 343: Upper pad 351: First rewiring plug 353:Second rewiring plug 355: Second rewiring layer 361:First support plug 363: Second support plug 500:Third chip 611: Molding layer D1: distance D2: distance D3: distance D4: distance DR: dense area LR: sparse area VL1: vertical height W1: Width W2: Width W3: Width

Embodiments of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion. FIG. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in the form of a flow chart. 2 to 6 illustrate a part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure using cross-sectional schematic diagrams. FIG. 7 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 8 is a schematic cross-sectional view along line A-A' in Fig. 7 . FIG. 9 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 10 is a schematic cross-sectional view along line A-A' in Fig. 9 . FIG. 11 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 12 is a schematic cross-sectional view along the cross-section line A-A' in Fig. 11. FIG. 13 illustrates a schematic plan view of a semiconductor device in an intermediate stage according to an embodiment of the present disclosure. Fig. 14 is a schematic cross-sectional view along the cross-section line A-A' in Fig. 13. FIG. 15 illustrates a part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure in a schematic cross-sectional view. 16 to 21 illustrate semiconductor devices according to some embodiments of the present disclosure in cross-sectional schematic diagrams.

1A: Semiconductor components

100:First chip

100FS: Front surface

111: First substrate

113: First intermediate dielectric layer

115: Bottom dielectric layer

117:Top dielectric layer

121: Plug structure

123: Bottom plug

125:pad

127: Top plug

131: First rewiring layer

141: First bottom passivation layer

143: First top passivation layer

145: Pad opening

147: Pad opening

151: First lower joint pad

153: Second lower bonding pad

300: Second chip

311: Second substrate

313: Second bottom interlayer dielectric layer

315: Inner wiring layer

317: Second top interlayer dielectric layer

321:Storage unit

331: Second bottom passivation layer

333: Second top passivation layer

341:Lower pad

343: Upper pad

351: First rewiring plug

353:Second rewiring plug

361:First support plug

363: Second support plug

DR: dense area

LR: sparse area

Claims (20)

A semiconductor component includes: a first wafer, including a first substrate, a first rewiring layer located above the first substrate, a first lower bonding pad located on the first rewiring layer, and a first rewiring layer located above the first substrate. a second lower bonding pad above the first substrate and away from the first lower bonding pad; and a second chip including: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located On the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers are located on the upper pads; and a first redistribution plug and a second redistribution plug are respectively located on the on the second redistribution layer, wherein the first redistribution plug is located in the dense area and includes a first aspect ratio, and wherein the second redistribution plug is located in the sparse area and includes an aspect ratio smaller than the first aspect ratio. A second aspect ratio. The semiconductor device of claim 1, further comprising: a plurality of lower pads located on the first rewiring plug and the second rewiring plug; and a plug structure located on the second lower bonding pad and the second rewiring plug. between the first substrate, wherein the plug structure is electrically coupled to the first redistribution plug. The semiconductor device of claim 2, wherein the plug structure includes a bottom plug on the first substrate, a contact pad on the bottom plug, and a contact pad between the contact pad and the second bottom plug. A top plug between the bottom bonding pads. The semiconductor device of claim 3, wherein the bottom plug includes aluminum, copper, or a combination thereof, and the top plug includes tungsten. The semiconductor device of claim 4, wherein the second chip includes a plurality of storage units located above the first chip and electrically coupled to the first lower bonding pad or the second lower bonding pad, and the storage units The unit is configured as a capacitor array or a floating array, the first chip is configured as a logic chip, and the second chip is configured as a memory chip. The semiconductor device according to claim 5, further comprising: a plurality of first support plugs respectively located on the second redistribution layers, wherein the first support plugs are respectively located in the dense area and the sparse area. area; and a plurality of second support plugs are respectively located on the second redistribution layers, wherein the second support plugs are respectively located in the dense area and the sparse area. The semiconductor device of claim 6, wherein a distance between a pair of adjacent first rewiring plugs and the first support plug in the dense area is substantially the same as a distance between a pair of adjacent phase plugs in the dense area. a distance between the adjacent first support plug and the second support plug. The semiconductor device of claim 6, wherein a distance between a pair of adjacent first rewiring plugs and the first support plug in the dense area is different from a distance between a pair of adjacent first rewiring plugs in the dense area. A distance between the first support plug and the second support plug. The semiconductor device of claim 6, wherein a distance between a pair of adjacent second rewiring plugs and the first support plug in the sparse region is substantially the same as a distance between a pair of adjacent phase plugs in the sparse region. a distance between the adjacent first support plug and the second support plug. The semiconductor device of claim 6, wherein a distance between a pair of adjacent second rewiring plugs and the first support plug in the sparse region is different from a distance between a pair of adjacent second rewiring plugs in the sparse region. A distance between the first support plug and the second support plug. The semiconductor device of claim 6, wherein a distance between a pair of adjacent first rewiring plugs and the first support plug in the dense area is substantially the same as a distance between a pair of adjacent phase plugs in the sparse area. a distance between the adjacent second rewiring plug and the first support plug. The semiconductor device of claim 6, wherein a distance between a pair of adjacent first rewiring plugs and the first support plug in the dense area is different from a distance between a pair of adjacent first rewiring plugs in the sparse area. A distance between the second rewiring plug and the first support plug. The semiconductor device of claim 6, wherein the first support plugs and the second support plugs are floating. A semiconductor component includes: a first wafer, including a first substrate, a first rewiring layer located above the first substrate, a first lower bonding pad located on the first rewiring layer, and a first lower bonding pad located on the first rewiring layer. First a second lower bonding pad above the substrate and away from the first lower bonding pad, and a plug structure between the second lower bonding pad and the first substrate; and a second chip, including: a dense area and a sparse area adjacent to the dense area; a plurality of upper pads located on the first lower bonding pad and the second lower bonding pad; a plurality of second redistribution layers located on the upper pads; and a first Redistribution plugs and a second redistribution plug are respectively located on the second redistribution layers, wherein the first redistribution plug is located in the dense area and is electrically coupled to the first redistribution layer and includes a first aspect ratio, wherein the second redistribution plug is located in the sparse region, is electrically coupled to the plug structure, and includes a second aspect ratio that is smaller than the first aspect ratio. The semiconductor device of claim 14, further comprising a plurality of lower pads on the first redistribution plug and the second redistribution plug, wherein the plug structure includes a bottom plug on the first substrate. plug, a pad on the bottom plug, and a top plug between the pad and the second lower bonding pad. The semiconductor device of claim 15, wherein the bottom plug includes aluminum, copper, or a combination thereof, and the top plug includes tungsten. The semiconductor device of claim 16, wherein the second chip includes a plurality of memory cells located above the first chip and electrically coupled to the first lower bonding pad or the second lower bonding pad. Yuan. The semiconductor device of claim 17, wherein the storage cells are configured as a capacitor array or a floating array. The semiconductor device of claim 18, wherein the first chip is configured as a logic chip, and the second chip is configured as a memory chip. The semiconductor device according to claim 19, further comprising: a plurality of first support plugs respectively located on the second redistribution layers, wherein the first support plugs are respectively located in the dense area and the sparse area. area; and a plurality of second support plugs are respectively located on the second redistribution layers, wherein the second support plugs are respectively located in the dense area and the sparse area, wherein the first support plugs and the second support plugs are floating.

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