TWI803312B - Semiconductor device with multi-stacking carrier structure - Google Patents

Abstract

The present application discloses a semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Description

Semiconductor element with multi-stacked carrier structure

This application claims priority to US Patent Application Nos. 17/561,151 and 17/560,548 (ie, the priority date is "December 23, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor element with a multi-stacked carrier structure.

Semiconductor devices have been used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are still increasing. Accordingly, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reductions in complexity.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not form the prior art of this disclosure, and any description of the above "prior art" shall not form any part of this case.

One aspect of the present disclosure provides a semiconductor device, including: a substrate; a An intermediate dielectric layer is located on the substrate; a conductive pad is located in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stack carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the A first through hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a layer located on the first insulating layer A second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and A third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

Another aspect of the present disclosure provides a multi-stack carrier structure, including: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first passivation layer on the first passivation layer an insulating layer, and a first through hole, wherein the first through hole is arranged along the first passivation layer and the first insulating layer; a second layer, located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer layer, and a third via hole, wherein the third via hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via hole.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the In the dielectric layer; form a first layer on the dielectric layer, wherein the first layer includes a first passivation layer on the dielectric layer, a first passivation layer on the first passivation layer an insulating layer, and a first via hole, wherein the first via hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer , wherein the second layer includes a second passivation layer located on the first insulating layer, a second insulating layer located on the second passivation layer, and a second via hole, wherein the second via hole is along the disposed along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a a third passivation layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and electrically connected to the second via. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the multiple The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an interposer an electrical layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial carrier from the etch stop layer ; and thinning the substrate.

Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure can be used as a temporary carrier to assist in the thinning process of the substrate. Therefore, no carrier is required during the thinning process of the substrate. As a result, the manufacturing cost of the semiconductor element can be reduced. Furthermore, after the thinning process, the multi-stacked carrier structure can provide electrical paths connected to the device components of the semiconductor device. Therefore, the performance of semiconductor elements can be easily analyzed in the presence of multi-stacked carrier structures.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages forming the subject of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1A: Semiconductor components

1B: Semiconductor components

1C: Semiconductor components

1D: Semiconductor components

10: method

20: method

101: Substrate

103:Intermediate dielectric layer

105: Conductive gasket

200: Multi-stack carrier structure

203: Top passivation layer

203O: first top opening

205: Redistribution layer

207: etch stop layer

207O: second top opening

210: first floor

211: the first passivation layer

213: The first insulating layer

215: the first through hole

215BS: bottom surface

215O: First through-hole opening

215SW: side wall

215TS: Top surface

220: second floor

221: Second passivation layer

223: Second insulating layer

225: Second through hole

225O: Second through-hole opening

225TS: top surface

230: third floor

231: The third passivation layer

233: The third insulating layer

235: The third through hole

235O: Third through-hole opening

235TS: top surface

240: fourth floor

241: The fourth passivation layer

243: The fourth insulating layer

245: The fourth through hole

245TS: top surface

250: fifth floor

251: The fifth passivation layer

253: fifth insulating layer

255: Fifth through hole

255TS: top surface

401: sacrificial carrier

510: The first mask layer

510O: first patterned opening

520:Second mask layer

520O: second patterned opening

530: The third mask layer

530O: third patterned opening

AL: Adhesion layer

BL: barrier layer

FL: filler layer

IL: isolation layer

SL: seed layer

S11: step

S13: step

S15: step

S21: step

S23: step

S25: step

T0: Thickness

T1: Thickness

T2: Thickness

TL: Thickness

W0: width

W1: width

W2: width

W3: width

W4: width

W5: width

W6: width

W7: width

W8: width

W9: width

W10: width

WC: width

Z: Direction

Various aspects of this disclosure can be read in conjunction with the following diagrams and detailed descriptions for understanding. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily expanded or reduced for clarity of discussion.

FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

FIG. 2 is a schematic cross-sectional view showing a close-up of a first through hole for fabricating a semiconductor device according to an embodiment of the present disclosure.

3 to 5 illustrate schematic cross-sectional views of semiconductor devices according to some embodiments of the present disclosure.

FIG. 6 shows a method for fabricating a semiconductor device in the form of a flow chart according to an embodiment of the present disclosure.

7 to 21 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

FIG. 22 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure picture.

FIG. 23 shows a method for fabricating a semiconductor device in the form of a flow chart according to another embodiment of the present disclosure.

24 to 32 are cross-sectional schematic diagrams showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

FIG. 33 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different elements of the disclosed embodiments. Examples of specific components and their arrangement are described below to simplify the embodiments of the present disclosure. Of course, these are just examples and should not limit the scope of the embodiments of the present disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first component is in direct contact with the second component, or both. An embodiment in which other components are formed without direct contact between them. In addition, the present disclosure may repeat reference symbols and/or labels in different embodiments. These repetitions are for simplicity and clarity and are not intended to limit the relationship between the different embodiments and/or structures discussed.

In addition, the text uses terms related to space, such as: "below", "beneath", "lower", "above", "higher", and similar terms In order to facilitate description of the relationship between one element or component and another element or component shown in the drawings. These spatial relative terms are intended to encompass different orientations of the element in use or operation than that depicted in the drawings. The device may be turned in different orientations (rotated 90 degrees or otherwise) and the spatially relative adjectives used therein may be interpreted similarly.

It should be understood that when an element or layer is referred to as being "connected to" or "coupled When "to" another element or layer, it may be directly connected or coupled to the other element or layer, or intervening elements or layers may be present.

It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless stated otherwise, these terms are only used to distinguish one element from another. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.

Unless the context dictates otherwise, terms such as "same", "equal", "planar", or "coplanar" when used herein to refer to orientation, arrangement, position, shape, size, quantity, or other measure do not necessarily denote exactly the same orientation, arrangement, position, shape, size, quantity or other measure, but are intended to cover nearly the same orientation, arrangement, position, shape, size, quantity or other measure. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal or planar, or within acceptable variations, such as due to manufacturing processes Can be same, equal or flat.

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor properties, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of the direction Z, and below or down corresponds to the arrow direction opposite to the direction Z.

FIG. 1 shows a schematic cross-sectional view of a semiconductor device 1A according to an embodiment of the present disclosure. picture. FIG. 2 shows a close-up cross-sectional view of the first through hole 215 of the semiconductor device 1A according to an embodiment of the present disclosure. 3 to 5 show schematic cross-sectional views of semiconductor devices 1B, 1C, and 1D according to some embodiments of the present disclosure.

Referring to FIG. 1, a semiconductor device 1A may include a substrate 101, a plurality of device elements (device elements) (not shown for clarity), an inter-dielectric layer 103, a plurality of conductive components, and multiple stacks. Carrier structure 200 .

Referring to FIG. 1 , the substrate 101 may include a bulk semiconductor substrate entirely composed of at least one semiconductor material. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductors or Group II-VI compound semiconductors, or combinations thereof.

In some embodiments, the thickness T0 of the substrate 101 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness T0 of the substrate 101 may be about 3 μm.

Referring to FIG. 1, the element components may be formed on a bulk semiconductor substrate. Some parts of these element components may be formed in a bulk semiconductor substrate. These element components can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field effect Transistors (fin field-effect-transistors), their analogs, or combinations thereof.

Referring to FIG. 1 , an intermediate dielectric layer 103 may be disposed on a substrate 101 . In some embodiments, the interlayer dielectric layer 103 may be a stacked structure. The intermediate dielectric layer 103 may include a plurality of insulating sublayers. Each of these insulator layers may have a thickness between about 0.5 microns to thickness between approximately 3.0 microns. The insulator layers may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, and the like. , or a combination of the foregoing. The insulator layers may include different materials, but are not limited thereto. Low-k dielectric materials may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. The fabrication techniques of the dielectric layers may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. A planarization process may be performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent processing steps.

It should be noted that in the description of the present disclosure, the term "about" used to modify the amount of an ingredient, component, or reactant used in the present disclosure means, for example, by typical measurements and liquids used to prepare a concentrate or solution. The number of changes a handler may produce. In addition, variations may arise from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of ingredients used in making the compositions or performing the methods. In one aspect, the word "about" means within 10% of the reported value. On the other hand, the word "about" means within 5% of the reported value. In yet another aspect, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 1 , the conductive members may be disposed in the intermediate dielectric layer 103 . The conductive components may include an interconnect layer (not shown for clarity), conductive vias (not shown for clarity), and a plurality of conductive pads 105 . The interconnection layers may be separated from each other and may be arranged horizontally along the direction Z in the dielectric layers. In this embodiment, the topmost interconnect layer can be designated as conductive Liner 105. The top surfaces of the conductive pads 105 and the top surface of the interlayer dielectric layer 103 may be substantially coplanar. The conductive vias may connect adjacent interconnection layers in direction Z, adjacent component members and interconnection layers, and adjacent conductive pads 105 and interconnection layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive components may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides ( For example, titanium nitride), transition metal aluminides, or combinations thereof. The conductive features may be formed during the formation of the dielectric layers.

In some embodiments, the element components and the conductive components may together constitute a functional unit of the semiconductor element 1A. In the description of the present disclosure, functional units generally refer to functionally related circuits that are divided into different units for functional purposes. In some embodiments, a functional unit may typically be a highly complex circuit, like a processor core or an accelerator unit. In some other embodiments, the complexity and functionality of the functional units may be more or less complex.

Referring to FIG. 1 , a multi-stack carrier structure 200 may be disposed on the intermediate dielectric layer 103 . The multi-stack carrier structure 200 may include a first tier 210 , a second tier 220 , a third tier 230 , a fourth tier 240 , a fifth tier 250 , and a top passivation layer 203 . In some embodiments, the thickness TL of the multi-stack carrier structure 200 may be greater than about 500 microns. In some embodiments, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 1 , a first layer 210 may be disposed on the intermediate dielectric layer 103 . The first layer 210 may include a first passivation layer 211 , a first insulating layer 213 , and a plurality of first vias 215 .

Referring to FIG. 1 , a first passivation layer 211 may be disposed on the interlayer dielectric layer 103 . In some embodiments, the first passivation layer 211 may include, for example, an oxide material. In some embodiments, the first passivation layer 211 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass ( fluorinated silicate glass), its similar materials, or a combination of the foregoing. In some embodiments, the thickness T1 of the first passivation layer 211 may be between about 1 μm and about 2 μm.

Referring to FIG. 1 , a first insulating layer 213 may be disposed on the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, an oxide material. In some embodiments, the first insulating layer 213 may include the same material as the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, similar materials, or combinations thereof. In some embodiments, the thickness T2 of the first insulating layer 213 may be less than about 200 μm. For example, the thickness T2 of the first insulating layer 213 may be between about 150 μm and about 190 μm.

Referring to FIG. 1 and FIG. 2, in some embodiments, the first via holes 215 may be disposed along the first insulating layer 213 and the first passivation layer 211, disposed on the conductive pads 105, and respectively and correspondingly The ground is electrically connected to the conductive pads 105 .

For brevity, clarity and convenience of description, only one first through hole 215 is described.

In some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W0 of the bottom surface 215BS of the first through hole 215 may be smaller than the width W1 of the top surface 215TS of the first through hole 215 . In some embodiments, the first via hole 215 may include a filler layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and an isolation layer IL.

It should be noted that in the description of the present disclosure, the surface of an element (or part) located at the highest vertical level (vertical level) along the direction Z is referred to as the element (or part) pieces) top surface. The surface of the element (or component) located at the lowest vertical level along the direction Z is referred to as the bottom surface of the element (or component).

It should be noted that in the description of the present disclosure, "width" refers to the distance measured from one side surface of an element (e.g., layer, plug, groove, hole, opening, etc.) to an opposite surface in a cross-sectional perspective view. Component size. Where indicated, the word "thickness" may be used instead of "width".

The filler layer FL may be disposed along the first insulating layer 213 and the first passivation layer 211 , and disposed on the conductive pad 105 . In some embodiments, the filler layer FL may have an aspect ratio between about 1:2 to about 1:35 or between about 1:10 to about 1:25. The filler layer FL may include, for example, doped polysilicon, tungsten, copper, carbon nanotubes, or solder alloy.

Referring to FIG. 2 , in some embodiments, the seed layer SL may have a U-shaped cross-sectional profile. The seed layer SL may be disposed between the filler layer FL and the first insulating layer 213 , between the filler layer FL and the first passivation layer 211 , and between the filler layer FL and the conductive pad 105 . In some embodiments, the seed layer SL may have a thickness between about 10 nm and about 40 nm. In some embodiments, the seed layer SL may include copper, for example. The seed layer SL may reduce the resistivity of the opening during the formation of the filler layer FL.

In some embodiments, the adhesive layer AL may have a U-shaped cross-sectional profile. The adhesion layer AL may be disposed between the seed layer SL and the first insulating layer 213 , between the seed layer SL and the first passivation layer 211 , and between the seed layer SL and the conductive pad 105 . The seed layer SL may include, for example, titanium, tantalum, titanium, tungsten, or manganese nitride. The adhesion layer AL can improve the adhesion between the seed layer SL and the barrier layer BL.

In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be located between the adhesion layer AL and the first insulating layer 213, the adhesion layer AL and the first passivation layer 211, and between the adhesive layer AL and the conductive pad 105. The barrier layer BL may include, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride/tantalum bilayer. The barrier layer BL can inhibit the conductive material of the filler layer FL from diffusing into the first insulating layer 213 , the first passivation layer 211 , or the interlayer dielectric layer 103 .

In some embodiments, the isolation layer IL may be disposed between the barrier layer BL and the first insulating layer 213 , and between the barrier layer BL and the first passivation layer 211 . In some embodiments, the isolation layer IL may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The isolation layer IL may have a thickness between about 50 nm and about 200 nm. In some embodiments, the isolation layer IL may include, for example, parylene, epoxy resin, or poly(p-xylene). The isolation layer IL may have a thickness between about 1 μm to about 5 μm. The isolation layer IL can ensure that the filler layer FL is electrically isolated in the first insulating layer 213 and the first passivation layer 211 .

Referring to FIG. 1 , the second layer 220 may be disposed on the first layer 210 . The second layer 220 may include a second passivation layer 221 , a second insulating layer 223 , and a plurality of second via holes 225 . The second passivation layer 221 may be disposed on the first insulating layer 213 . The second insulating layer 223 may be disposed on the second passivation layer 221 . The second through holes 225 may be disposed along the second insulating layer 223 and the second passivation layer 221, disposed on the first through holes 215, and electrically connected to the first through holes 215 respectively and correspondingly. . The second passivation layer 221, the second insulating layer 223, and the second through holes 225 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

Referring to FIG. 1 , the width W2 of the top surface 225TS of the second through hole 225 may be greater than the width W1 of the top surface 215TS of the first through hole 215 .

Referring to FIG. 1 , a third layer 230 may be disposed on the second layer 220 . The third floor 230 A third passivation layer 231 , a third insulating layer 233 , and a plurality of third via holes 235 may be included. The third passivation layer 231 may be disposed on the second insulating layer 223 . A third insulating layer 233 may be disposed on the third passivation layer 231 . The third through holes 235 may be disposed along the third insulating layer 233 and the third passivation layer 231 , disposed on the second through holes 225 , and electrically connected to the second through holes 225 respectively and correspondingly. . The third passivation layer 231, the third insulating layer 233, and the third through holes 235 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

Referring to FIG. 1 , a width W3 of a top surface 235TS of the third through hole 235 may be greater than a width W2 of a top surface 225TS of the second through hole 225 .

Referring to FIG. 1 , a fourth layer 240 may be disposed on the third layer 230 . The fourth layer 240 may include a fourth passivation layer 241 , a fourth insulating layer 243 , and a plurality of fourth via holes 245 . A fourth passivation layer 241 may be disposed on the third insulating layer 233 . A fourth insulating layer 243 may be disposed on the fourth passivation layer 241 . The fourth through holes 245 may be disposed along the fourth insulating layer 243 and the fourth passivation layer 241, disposed on the third through holes 235, and electrically connected to the third through holes respectively and correspondingly. 235. The fourth passivation layer 241, the fourth insulating layer 243, and the fourth through holes 245 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

Referring to FIG. 1 , a width W4 of a top surface 245TS of the fourth through hole 245 may be greater than a width W3 of a top surface 235TS of the third through hole 235 .

Referring to FIG. 1 , a fifth layer 250 may be disposed on the fourth layer 240 . The fifth layer 250 may include a fifth passivation layer 251 , a fifth insulating layer 253 , and a plurality of fifth via holes 255 . A fifth passivation layer 251 may be disposed on the fourth insulating layer 243 . A fifth insulating layer 253 may be disposed on the fifth passivation layer 251 . The fifth via holes 255 can be formed along the fifth insulating layer 253 and the fifth passivation layer 251 is disposed on, disposed on the fourth through holes 245 , and electrically connected to the fourth through holes 245 respectively and correspondingly. The fifth passivation layer 251, the fifth insulating layer 253, and the fifth through holes 255 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

Referring to FIG. 1 , a width W5 of a top surface 255TS of the fifth through hole 255 may be greater than a width W4 of a top surface 245TS of the fourth through hole 245 .

It should be noted that in the description of the present disclosure, the number of layers of the multi-stacked carrier structure 200 is for illustrative purposes only. In other words, the multi-stack carrier structure 200 may have more or less than five layers.

Referring to FIG. 1 , a top passivation layer 203 may be disposed on the topmost insulating layer (ie, the fifth insulating layer 253 of the fifth layer 250 ). The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film , or similar materials, or a combination of the foregoing. In some other embodiments, the top passivation layer 203 may be a dielectric layer. Dielectric layers may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations thereof.

It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than that of nitrogen. Silicon oxynitride refers to a substance that contains silicon, oxygen and nitrogen and wherein the proportion of nitrogen is greater than that of oxygen.

Referring to FIG. 1 , a plurality of first top openings 203O may be disposed along the top passivation layer 203 to respectively and correspondingly expose the fifth via holes 255 . The exposed fifth via hole 255 can be Electrically coupled to probes for electrical characteristic testing.

During the thinning process of the substrate 101, the multi-stacked carrier structure 200 may serve as a temporary carrier. With the aid of the multi-stack carrier structure 200, the performance of the semiconductor device 1A comprising the substrate 101 smaller than 10 μm can be analyzed. In contrast, a conventional semiconductor element including a substrate smaller than 10 μm is covered by a carrier, so its performance cannot be easily analyzed.

Referring to FIG. 3 , the structure of the semiconductor element 1B may be similar to that shown in FIG. 1 . Components in FIG. 3 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 3 , a plurality of redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the fifth through holes 255 , and electrically connected to the fifth through holes 255 respectively and correspondingly. The redistribution layers 205 can re-route the fifth vias 255 to provide a more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

Referring to FIG. 4 , the structure of the semiconductor element 1C may be similar to that shown in FIG. 1 . Components in FIG. 4 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 4, the fifth layer 250, the fourth layer 240, the third layer 230, the second layer 220, and the first layer 210 may be disposed on the intermediate dielectric in the reverse order of the multi-stack carrier structure 200 shown in FIG. layer 103. For example, the fifth insulating layer 253 is disposed on the intermediate dielectric layer 103, the fifth passivation layer 251 is disposed on the fifth insulating layer 253, the fourth insulating layer 243 is disposed on the fifth passivation layer 251, and the fourth passivation layer 241 disposed on the fourth insulating layer 243 .

Referring to FIG. 4 , in some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W7 of the bottom surface 215BS of the first through hole 215 may be greater than that of the first through hole. The width W6 of the top surface 215TS of 215 .

Referring to FIG. 4 , in some embodiments, an etch stop layer 207 may be disposed on the first insulating layer 213 of the first layer 210 . In some embodiments, etch stop layer 207 may preferably include a dielectric material having an etch selectivity different from that of adjacent layers. For example, the etch stop layer 207 may include silicon nitride, silicon carbonitride, silicon oxycarbide, similar materials, or combinations thereof. A plurality of second top openings 207O can be disposed along the etch stop layer 207 to expose the first through holes 215 . The exposed first via hole 215 can be electrically coupled to a probe for electrical characteristic testing.

Referring to FIG. 5 , the structure of the semiconductor element 1D may be similar to that shown in FIG. 4 . Components in FIG. 5 that are the same as or similar to those in FIG. 4 have been marked with similar reference symbols and repeated descriptions are omitted.

Referring to FIG. 5 , a top passivation layer 203 may be disposed on the first insulating layer 213 of the first layer 210 . The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto build-up film, solder photoresist film, or similar materials, or combinations thereof. . In some other embodiments, the top passivation layer 203 may be a dielectric layer. Dielectric layers may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations thereof.

Referring to FIG. 5 , the redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the first through holes 215 , and electrically connected to the first through holes 215 respectively and correspondingly. The redistribution layers 205 can rewire the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. These redistribution layers 205 may include, for example Tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

It should be noted that the terms "forming," "formed," and "form" can mean and include creating, building, patterning, implanting, or depositing elements, doping debris, or material in any way. Examples of formation methods may include, but are not limited to, atomic layer deposition (atomic layer deposition), chemical vapor deposition (chemical vapor deposition), physical vapor deposition (physical vapor deposition), sputtering (sputtering), co-sputtering (co- sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

It should be noted that, in the description of the present disclosure, the functions or steps mentioned herein may appear in an order different from that mentioned in the drawings. For example, two figures shown in succession may, in fact, be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functions or steps involved.

FIG. 6 shows a method 10 for manufacturing the semiconductor device 1A in the form of a flowchart according to an embodiment of the present disclosure. 7 to 21 are schematic cross-sectional views showing the fabrication process of the semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIG. 6 and FIG. 7 , in step S11 , a substrate 101 may be provided, and an intermediate dielectric layer 103 may be formed on the substrate 101 .

Referring to FIG. 7 , the material of the substrate 101 is as shown in FIG. 1 , and its description will not be repeated here. In some embodiments, substrate 101 may include a semiconductor-on-insulator structure that includes, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost layer of semiconductor material may comprise the same materials as described above for the bulk semiconductor substrate. The insulating layer can be crystalline or amorphous dielectric material, such as oxide and/or nitride. For example, insulation It may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer can be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulating layer may include a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm to about 200 nm. It should be noted that at this stage, the thickness T0 of the substrate 101 may be greater than 700 μm or greater than 500 μm.

Referring to FIG. 7 , the fabrication technique for forming the interlayer dielectric layer 103 on the substrate 101 may include a deposition process such as chemical vapor deposition. Planarization processes such as chemical mechanical polishing may be performed to provide a substantially planar surface for subsequent processing steps. Element components (not shown for clarity) and conductive features (not shown for clarity) may be formed during formation of the interlayer dielectric layer 103 . The fabrication technique for forming the conductive pads 105 in the interlayer dielectric layer 103 may include, for example, a damascene process. The top surfaces of the conductive pads 105 and the top surface of the interlayer dielectric layer 103 may be substantially coplanar.

Referring to FIG. 6 and FIG. 8 to FIG. 19 , in step S13 , a multi-stack carrier structure 200 may be formed on the intermediate dielectric layer 103 .

Referring to FIG. 8, the first passivation layer 211 can be formed on the intermediate dielectric layer 103, and the fabrication technique of the third passivation layer 231 can include, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, or other applicable deposition techniques. Process. In some embodiments, an oxide bonding process may be performed to form the first insulating layer 213 on the first passivation layer 211 . The material of the first passivation layer 211 is as shown in FIG. 1 , and its description will not be repeated here.

Referring to FIG. 9 , a first mask layer 510 may be formed on the first insulating layer 213 . The first mask layer 510 may include a plurality of first patterned openings 510O, which define the positions of the first through holes 215 . The first patterned opening 510O may have a width W8. The width W8 of the first patterned opening 510O may be greater than the width WC of the conductive pad 105 .

Referring to FIG. 10, an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and a portion of the first passivation layer 211, and simultaneously form a plurality of first via openings. 215O. In some embodiments, the sidewalls of the first via openings 215O may be tapered. After the oxide etch process, the first mask layer 510 may be removed.

Referring to FIG. 11 , the fabrication techniques for forming the first via holes 215 in the first via hole openings 215O may include, for example, chemical vapor deposition, physical vapor deposition, evaporation, sputtering, electroplating, or combinations thereof. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The materials and structures of the first through holes 215 are shown in FIGS. 1 and 2 , and the description thereof will not be repeated here. The first passivation layer 211 , the first insulating layer 213 , and the first through holes 215 together constitute the first layer 210 .

12, a second passivation layer 221 can be formed on the first insulating layer 213, a second insulating layer 223 can be formed on the second passivation layer 221, and a second mask layer 520 can be formed on the second insulating layer 223. . The material of the second passivation layer 221 and the material of the second insulating layer 223 are as shown in FIG. 1 , and the description thereof will not be repeated here. The second passivation layer 221 , the second insulating layer 223 , and the second mask layer 520 may be formed through steps similar to those of the first layer 210 shown in FIGS. 8 to 11 , and the description thereof will not be repeated here. The second mask layer 520 may include a plurality of second patterned openings 520O, which define the positions of the second through holes 225 . The width W9 of the second patterned opening 520O may be greater than the width W8 of the first patterned opening 510O.

Referring to FIG. 13, an oxide etching process may be performed using the second mask layer 520 as a pattern guide to remove a portion of the second insulating layer 223 and a portion of the second passivation layer 221, and simultaneously form a plurality of second via openings. 225O. In some embodiments, the sidewalls of the second via openings 225O may be tapered. After the oxide etch process, it can be removed The second mask layer 520 .

Referring to FIG. 14 , the second through holes 225 can be formed in the second through hole openings 225O through a process similar to that of the first through holes 215 , and the description thereof will not be repeated here. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The second passivation layer 221 , the second insulating layer 223 , and the second through holes 225 together constitute the second layer 220 .

The larger width of the second patterned opening 520O may be transferred to the second via opening 225O and then inherited by the second via 225 . The larger width of the second via hole 225 may provide a larger tolerance window for subsequent lithography processes (eg, the lithography process of the third via hole 235 ). As a result, the yield of the semiconductor element 1A can be improved.

15, a third passivation layer 231 can be formed on the second insulating layer 223, a third insulating layer 233 can be formed on the third passivation layer 231, and a third mask layer 530 can be formed on the third insulating layer 233. . The material of the third passivation layer 231 and the material of the third insulating layer 233 are as shown in FIG. 1 , and the description thereof will not be repeated here. The third passivation layer 231 , the third insulating layer 233 , and the third mask layer 530 may be formed through steps similar to those of the first layer 210 shown in FIGS. 8 to 11 , and the description thereof will not be repeated here. The third mask layer 530 may include a plurality of third patterned openings 530O, which define the positions of the third through holes 235 . The width W10 of the third patterned opening 530O may be greater than the width W9 of the second patterned opening 520O.

Referring to FIG. 16, an oxide etching process may be performed using the third mask layer 530 as a pattern guide to remove a portion of the third insulating layer 233 and a portion of the third passivation layer 231, and simultaneously form a plurality of third via openings. 235O. In some embodiments, the sidewalls of the third via openings 235O may be tapered. After the oxide etch process, the third mask layer 530 may be removed.

Referring to FIG. 17 , the third through holes 235 can be formed in the third through hole openings 235O through steps similar to those of the first through holes 215 , and the description thereof will not be repeated here. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The third passivation layer 231 , the third insulating layer 233 , and the third through holes 235 together constitute the third layer 230 .

It should be noted that the third via 235 appears to be offset from the second via 225 in direction Z to emphasize the benefit of a larger tolerance window for the lithography process obtained through the wider width of the second via 225 . That is to say, even if the alignment of the lithography process deviates, the through holes 225 and 235 can still be electrically connected normally.

Referring to FIG. 18 , the fourth layer 240 and the fifth layer 250 may be formed through steps similar to the first layer 210 shown in FIGS. 8 to 11 , and description thereof will not be repeated here.

Referring to FIG. 19 , a top passivation layer 203 may be formed on the fifth layer 250 . Fabrication techniques for the top passivation layer 203 may include, for example, spin-coating, lamination, deposition, or similar techniques. Deposition may include chemical vapor deposition. The material of the top passivation layer 203 is as shown in FIG. 1 , and its description will not be repeated here. Layers 210 , 220 , 230 , 240 , 250 and top passivation layer 203 together constitute multi-stack carrier structure 200 .

In some embodiments, before the thinning process of the substrate 101, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1, or between about 1. :1 to approximately 7:5.

Referring to FIGS. 6 , 20 , and 21 , in step S15 , the substrate 101 may be thinned and a plurality of first top openings 203O may be formed along the top passivation layer 203 of the multi-stack carrier structure 200 .

Referring to Figure 20, through the use of wafer grinding (wafer grinding), The substrate 101 is thinned by mechanical abrasion, polishing, or similar techniques, or a thinning process using chemical removal such as wet etching. It should be noted that no carrier is required during the thinning process. The multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 .

Referring to FIG. 20 , after the thinning process, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 21 , the first top openings 203O may be formed along the top passivation layer 203 to respectively and correspondingly expose the fifth via holes 255 . The exposed fifth via hole 255 can be electrically coupled to a probe for electrical characteristic testing. That is, the performance of the semiconductor element 1A after the substrate has been thinned can be easily analyzed.

FIG. 22 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIG. 22 , the structure of the semiconductor element 1B may be similar to that shown in FIG. 21 . Components in FIG. 22 that are the same as or similar to those in FIG. 21 have been marked with similar reference symbols and repeated descriptions are omitted.

In the semiconductor device 1B, the redistribution layers 205 can be respectively and correspondingly formed on the fifth through holes 255 . In some embodiments, the formation of the redistribution layers 205 may include forming one or more insulating layers (ie, top passivation layer 203 ) and forming conductive components (ie, the redistribution layers 205 ) in the insulating layer. The formation of the conductive features may include patterning the insulating layer (e.g., using lithography and/or etching processes) and forming the conductive features in the patterned insulating layer (e.g., by using a mask layer to define the shape of the conductive features, and using electroless/electrochemical plating process to deposit the seed layer). For example, the first top openings 203O can define The patterns of the redistribution layers 205 . The redistribution layers 205 can be formed in the first top openings 203O.

FIG. 23 shows a method 20 of manufacturing a semiconductor device 1C in the form of a flowchart according to another embodiment of the present disclosure. 24 to 32 are cross-sectional schematic diagrams showing a fabrication process of a semiconductor device 1C according to another embodiment of the present disclosure.

Referring to FIGS. 23 to 27 , in step S21 , a sacrificial carrier 401 may be provided, and a multi-stacked carrier structure 200 may be temporarily formed on the sacrificial carrier 401 .

Referring to FIG. 24 , an etch stop layer 207 may be formed on the sacrificial carrier 401 . In general, the etch stop layer 207 can provide a mechanism to stop the etch process when forming conductive features. The etch stop layer 207 may preferably include a dielectric material having an etch selectivity different from that of an adjacent layer. For example, the etch stop layer 207 may include silicon nitride, silicon carbonitride, silicon oxycarbide, or similar materials, and the etch stop layer 207 may be deposited by chemical vapor deposition or plasma assisted chemical vapor deposition.

Referring to FIG. 24 , fabrication techniques for forming a first insulating layer 213 on the etch stop layer 207 may include, for example, deposition processes such as chemical vapor deposition or plasma-assisted chemical vapor deposition. The material of the first insulating layer 213 is as shown in FIG. 1 , and its description will not be repeated here. A first mask layer 510 can be formed on the first insulating layer 213 . The first mask layer 510 may include a pattern that defines the positions of the plurality of first through holes 215 .

Referring to FIG. 25 , an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and simultaneously form the first via openings 215O. A portion of the etch stop layer 207 may be exposed through the first via openings 215O. During the oxide etch process, the etch rate ratio of the first insulating layer 213 to the etch stop layer 207 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1. between, or between about 10:1 and about 2:1. After the oxide etch process, the first mask layer 510 may be removed.

Referring to FIG. 26 , a plurality of first through holes 215 may be formed in the first through hole openings 215O. A planarization process such as chemical mechanical polishing may be performed until the top surface of the first insulating layer 213 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. The materials of the first through holes 215 are as shown in FIG. 1 , and the description thereof will not be repeated here. The first insulating layer 213 and the first through holes 215 together constitute the first layer 210 .

Referring to FIG. 27 , the second layer 220 , the third layer 230 , the fourth layer 240 , and the fifth layer 250 may be formed through steps similar to those shown in FIGS. 12 to 19 , and description thereof will not be repeated here. The first layer 210 , the second layer 220 , the third layer 230 , the fourth layer 240 , the fifth layer 250 , and the etch stop layer 207 together constitute the multi-stacked carrier structure 200 .

23, FIG. 28, and FIG. 29, in step S23, a substrate 101 can be provided, an intermediate dielectric layer 103 can be formed on the substrate 101, and a plurality of conductive pads 105 can be formed in the intermediate dielectric layer 103, And the multi-stack carrier structure 200 may be bonded to the interlayer dielectric layer 103 .

Referring to FIG. 28 , the substrate 101 , the interlayer dielectric layer 103 , and the conductive pads 105 may be formed through steps similar to those shown in FIGS. 1 and 7 , and the description thereof will not be repeated here.

Referring to FIG. 29 , the multi-stacked carrier structure 200 may be flipped over and bonded onto the intermediate dielectric layer 103 . In some embodiments, the multi-stacked carrier structure 200 may be bonded to the interlayer dielectric layer 103 through a hybrid bonding process. In some embodiments, the hybrid bonding process may include, for example, thermo-compression bonding, passivation-capping-layer assisted bonding, or surface-activated bonding. In some embodiments, the process pressure of the hybrid bonding process may range from about 100 MPa to about Between 150MPa. In some embodiments, the process temperature of the hybrid bonding process may be between about room temperature (eg, 25° C.) to about 400° C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase heat treatment can be used to reduce the process temperature or shorten the time consumption of the hybrid bonding process. In some embodiments, the hybrid bonding process may include, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. -dielectric) joint. In some embodiments, a thermal annealing process may be performed after the bonding process to enhance the dielectric-to-dielectric bonding and cause thermal expansion of the metal-to-metal bonding, thereby further improving the bonding quality.

Referring to FIG. 30 , prior to the thinning process of the substrate 101 , in some embodiments, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1:1. , or between about 1:1 and about 7:5.

Referring to FIGS. 23 and 30 to 32 , in step S25 , the sacrificial carrier 401 may be separated, the substrate 101 may be thinned, and a plurality of second top openings 207O may be formed along the etch stop layer 207 of the multi-stacked carrier structure 200 .

As shown in FIG. 30 , sacrificial carrier 401 may be separated from etch stop layer 207 .

Referring to FIG. 31 , the substrate 101 may be thinned by a thinning process using wafer grinding, mechanical abrasion, lapping, or similar techniques, or using chemical removal such as wet etching. It should be noted that no carrier is required during the thinning process. The multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 .

Referring to FIG. 31 , after the thinning process of the substrate 101 , the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

Referring to FIG. 32, a plurality of second tops may be formed along the etch stop layer 207. The openings 207O respectively and correspondingly expose the first through holes 215 . The exposed first via hole 215 can be electrically coupled to a probe for electrical characteristic testing. That is, the performance of the semiconductor element 1C after the substrate has been thinned can be easily analyzed.

FIG. 33 is a schematic cross-sectional view showing a fabrication process of a semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIG. 33 , the structure of the semiconductor element 1D may be similar to that shown in FIG. 31 . Components in FIG. 33 that are the same as or similar to those in FIG. 31 have been marked with similar reference symbols and repeated descriptions are omitted.

In the semiconductor element 1D, the etch stop layer 207 may be completely removed. The top passivation layer 203 can be formed on the first layer 210 through steps similar to those shown in FIG. 19 , and the description thereof will not be repeated here. A plurality of redistribution layers 205 may be formed along the top passivation layer 203 and respectively and correspondingly formed on the first through holes 215 . The redistribution layers 205 can rewire the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. The materials of the redistribution layers 205 are shown in FIG. 3 , and the description thereof will not be repeated here.

An aspect of the present disclosure provides a semiconductor device, including: a substrate; an intermediate dielectric layer on the substrate; a conductive pad in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stack carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the A first through hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a layer located on the first insulating layer A second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer on the second layer and including on the second insulating layer a third passivation layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and electrically connected to the second via.

Another aspect of the present disclosure provides a multi-stack carrier structure, including: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first passivation layer on the first passivation layer an insulating layer, and a first through hole, wherein the first through hole is arranged along the first passivation layer and the first insulating layer; a second layer, located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer layer, and a third via hole, wherein the third via hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via hole.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the On the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the The first via hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second layer includes a layer located on the first layer A second passivation layer on the insulating layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is along the second passivation layer and the second insulating layer disposing and electrically connecting to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third passivation layer on the third passivation layer on A third insulating layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the multiple The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an interposer an electrical layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial carrier from the etch stop layer ; and thinning the substrate.

Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 . Therefore, no carrier is required during the thinning process of the substrate 101 . As a result, the manufacturing cost of the semiconductor element 1A can be reduced. In addition, after the thinning process, the multi-stack carrier structure 200 can provide electrical paths connected to the device components of the semiconductor device 1A. Therefore, the performance of the semiconductor element 1A can be easily analyzed in the presence of the multi-stack carrier structure 200 .

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. skill of the craft Those skilled in the art can understand from the disclosure content of this disclosure that existing or future development processes, machinery, manufacturing, and material compositions that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure , means, method, or steps. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components

101: Substrate

103:Intermediate dielectric layer

105: Conductive gasket

200: Multi-stack carrier structure

203: Top passivation layer

203O: first top opening

210: first floor

211: the first passivation layer

213: The first insulating layer

215: the first through hole

215BS: bottom surface

215SW: side wall

215TS: Top surface

220: second floor

221: Second passivation layer

223: Second insulating layer

225: Second through hole

225TS: top surface

230: third floor

231: The third passivation layer

233: The third insulating layer

235: The third through hole

235TS: top surface

240: fourth floor

241: The fourth passivation layer

243: The fourth insulating layer

245: The fourth through hole

245TS: top surface

250: fifth floor

251: The fifth passivation layer

253: fifth insulating layer

255: Fifth through hole

255TS: top surface

T0: Thickness

T1: Thickness

T2: Thickness

TL: Thickness

W0: width

W1: width

W2: width

W3: width

W4: width

W5: width

Z: Direction

Claims (25)

A semiconductor element, comprising: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stacked carrier structure comprising: a first layer comprising the A first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first through hole, wherein the first through hole is along the first passivation layer and the first The insulating layer is arranged and electrically connected to the conductive pad; a second layer is located on the first layer and includes a second passivation layer located on the first insulating layer, a first passivation layer located on the second passivation layer Two insulating layers, and a second via hole, wherein the second via hole is disposed along the second passivation layer and the second insulating layer and electrically connected to the first via hole; and a third layer, located on the second via hole On the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is along the The third passivation layer and the third insulating layer are disposed and electrically connected to the second through hole, the second through hole has a conductive filler layer, wherein a top surface of the filler layer is connected to a top surface of the second insulating layer The top surfaces are coplanar, and a bottom surface of the third through hole is at least partially outside a vertical projection area of a top surface of the second through hole. The semiconductor device of claim 1, wherein a thickness of the multi-stacked carrier structure is greater than about 500 microns. The semiconductor device of claim 2, wherein a thickness of the first insulating layer is less than about 200 microns. The semiconductor device as claimed in claim 2, wherein a thickness of the first passivation layer is between about 1 micron and about 2 microns. The semiconductor device according to claim 2, wherein a width of a top surface of the first via hole is smaller than a width of the top surface of the second via hole. The semiconductor device as claimed in claim 2, wherein a width of the top surface of the second via hole is smaller than a width of a top surface of the third via hole. The semiconductor device of claim 2, wherein a thickness of the substrate is less than about 200 microns. The semiconductor device of claim 2, wherein a thickness of the substrate is less than about 5 microns. The semiconductor device as claimed in claim 2, wherein the first passivation layer comprises an oxide material. The semiconductor device as claimed in claim 1, wherein the first insulating layer comprises an oxide material, and the conductive liner is composed of at least one of the following materials: tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper , metal carbides, metal nitrides, transition metal aluminides, or a combination of the foregoing. The semiconductor device as claimed in claim 2, further comprising a top passivation layer on the third insulating layer of the third layer. The semiconductor device as claimed in claim 11, further comprising a first top opening disposed along the top passivation layer to expose the third via hole. The semiconductor device of claim 1, wherein a thickness ratio of a thickness of the multi-stacked carrier structure to a thickness of the substrate is between about 180:1 and about 50:1. The semiconductor device as claimed in claim 1, wherein a sidewall of the first via hole is tapered and a width of a top surface of the first via hole is greater than a width of a bottom surface of the first via hole. The semiconductor device as claimed in claim 1, wherein the first via hole includes an isolation layer, wherein the filler layer is disposed along the first insulating layer and the first passivation layer and is located on the conductive pad, the isolation layer Located between the filler layer and the first insulating layer and between the filler layer and the first passivation layer. The semiconductor device as claimed in claim 15, wherein the first via hole includes a barrier layer between the filler layer and the isolation layer and between the filler layer and the conductive liner. The semiconductor device as claimed in claim 16, wherein the first via hole includes an adhesive layer between the filler layer and the barrier layer. The semiconductor device as claimed in claim 17, wherein the first via hole includes a seed layer located between the filler layer and the adhesion layer. The semiconductor device as claimed in claim 1, wherein the multi-stacked carrier structure includes a redistribution layer located on the third via and electrically conductive through the third via, the second via, and the first via coupled to the conductive pad. A multi-stacked carrier structure, comprising: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first insulating layer on the first passivation layer, and a first a via hole, wherein the first via hole is disposed along the first passivation layer and the first insulating layer; a second layer is located on the first layer and includes a second passivation layer located on the first insulating layer , a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, a third insulating layer located on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and is electrically connected To the second via hole, the second via hole has a conductive filler layer, wherein a top surface of the filler layer is coplanar with a top surface of the second insulating layer, and a bottom of the third via hole The surface is at least partially outside the area of a vertical projection of a top surface of the second through hole. The multi-stack carrier structure of claim 20, wherein a thickness of the multi-stack carrier structure is greater than about 500 microns. The multi-stacked carrier structure of claim 20, wherein a thickness of the first insulating layer is less than about 200 microns. The multi-stack carrier structure of claim 20, wherein a thickness of the first passivation layer is between about 1 micron and about 2 microns. The multi-stacked carrier structure of claim 20, wherein a width of a top surface of the first via is smaller than a width of the top surface of the second via. The multi-stacked carrier structure of claim 20, wherein a width of the top surface of the second via is smaller than a width of a top surface of the third via.

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