TWI817395B - Semiconductor device with stacking structure - Google Patents

Abstract

The present application discloses a semiconductor device with stacking structures. The semiconductor device includes a bottom die; a first stacking structure comprising a first controller die positioned on the bottom die, and a plurality of first storage dies stacked on the first controller die; and a second stacking structure comprising a second controller die positioned on the bottom die, and a plurality of second storage dies stacked on the second controller die. The plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array. The plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.

Description

Semiconductor components with stacked structures

This application claims priority to U.S. Patent Application Nos. 17/563,291 and 17/563,346 (that is, the priority date is "December 28, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having a plurality of stacked structures.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the downsizing process, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improvements in quality, yield, performance and reliability, and in reducing complexity.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. It should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device including a lower die; a first stack structure including a first controller die disposed on the lower die; and a plurality of a first storage die stacked on the first controller die; a second stack structure including a second controller die disposed on the lower die; and a plurality of second storage dies, stacked on this second controller die. The plurality of first storage dies respectively include a plurality of first storage cells, which are configured into a floating array. The plurality of second storage dies includes a plurality of second storage units, each of which includes an insulator-conductor-insulator structure.

Another embodiment of the present disclosure provides a semiconductor device including a lower die; a first stacked structure disposed on the lower die via a plurality of first interconnect units; and a second stacked structure via a plurality of first interconnect units. The second interconnect unit is disposed on the lower die. The first stacked structure includes: a first controller die disposed on the plurality of first interconnect units; a plurality of first storage dies stacked on the first controller die and configured to form a floating array. The second stacked structure includes: a second controller die disposed on the plurality of second interconnect units; and a plurality of second storage dies stacked on the second controller die and each including An insulator-conductor-insulator structure.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a first stacked structure. The first stacked structure includes: a first controller die; and a plurality of first storage dies, stacked in sequence. On the first controller die; provide a second stack structure, the second stack structure includes: a second controller die; and a plurality of second storage dies, sequentially stacked on the second controller on the die; the first controller die is bonded to the lower die via a plurality of first interconnect units; and the second controller die is bonded to the lower die via a plurality of second interconnect units superior. The plurality of first storage dies respectively include a plurality of first storage cells, which are configured into a floating array. The plurality of second storage dies includes a plurality of second storage units, each of which includes an insulator-conductor-insulator structure.

Due to the design of the semiconductor device disclosed in the present disclosure, the first stacked structure has The first memory cells in the form of a floating array, the second stack structure has the second memory cells, the second memory cells have the insulator-conductor-insulator structure, and the first stack structure and the second A stacked structure can be integrated with the lower die. Therefore, the dimension of the semiconductor device can be reduced. In addition, the through-substrate vias can also reduce a plurality of electrical paths within the first stacked structure and/or the second stacked structure, so that power consumption can be reduced. Therefore, the performance of the semiconductor device can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

1A: Semiconductor components

1B:Semiconductor components

1C: Semiconductor components

10:Preparation method

100: First stack structure

110: First controller die

110BS: Back surface

110FS: Front surface

111: Base

113:Dielectric layer

115: Through-base through hole

117:Conductive pad

120: The first storage chip

120BS: Back surface

120FS: Front surface

121: Base

123:Dielectric layer

125: Through-base through hole

127:Conductive pad

129: First storage unit

130: The first storage chip

130FS: Front surface

131: Base

133:Dielectric layer

137:Conductive pad

140: The first storage grain

150: The first storage chip

160: The first storage grain

170: The first storage chip

200: Second stack structure

210: Second controller die

210BS: Back surface

210FS: Front surface

211:Base

213:Dielectric layer

215: Through-base through hole

217:Conductive pad

220: Second storage grain

220BS: Lower surface

220FS: Upper surface

221: Base

223:Dielectric layer

225: Through-base through hole

227:Conductive pad

229: Second storage unit

230: Second storage grain

230FS: Front surface

231:Base

233:Dielectric layer

237:Conductive pad

240: Second storage grain

250: Second storage grain

310: Lower grain

311: Base

313: Dielectric layer

315:Through-substrate through hole

317: First connection pad

319: Second connection pad

411: First through-die via

413: First through-die via

421: Second through-die via

423: Second through-die via

431: Third through-die via

433: Third through-die via

441: The fourth through-die via

443: The fourth through-die via

510: First internal connection unit

511: First outer layer

513:First chamber

515: The first lower annular layer

517: First upper annular layer

520: Second internal connection unit

521: Second outer layer

523:Second chamber

525: Second lower annular layer

527:Second upper annular layer

530: The third internal connection unit

601: Bottom filling layer

603: Molding layer

605: Base base

A1:Area

A2:Area

AL: adhesive layer

BL: barrier layer

FL: filling layer

IL: insulation layer

S11: Steps

S13: Steps

S15: Steps

S17: Steps

SL: seed layer

T1:Thickness

T2:Thickness

T3:Thickness

T4:Thickness

T5:Thickness

T6:Thickness

W1: Width

W2: Width

W3: Width

W4: Width

Z: direction

By referring to the embodiments and the patent scope together with the drawings, the disclosure content of the present application can be more fully understood. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

2 to 22 are schematic cross-sectional views illustrating part of the process of preparing a semiconductor device according to an embodiment of the present disclosure.

23 and 24 are enlarged cross-sectional schematic views, illustrating the cross-sections of areas A1 and A2 in FIG. 22 .

25 and 26 are schematic cross-sectional views illustrating part of the process of preparing a semiconductor device according to an embodiment of the present disclosure.

FIG. 27 is an enlarged cross-sectional schematic diagram illustrating a semiconductor device according to another embodiment of the present disclosure.

28 is a schematic cross-sectional view illustrating part of the process of preparing a semiconductor device according to another embodiment of the present disclosure.

FIG. 29 is an enlarged schematic cross-sectional view illustrating the cross-section of area A1 in FIG. 28 .

Fig. 30 is a schematic cross-sectional view illustrating the cross-sections along the cross-section lines A-A', B-B' and C-C' of Fig. 29.

FIG. 31 is an enlarged schematic cross-sectional view illustrating the cross-section of area A2 in FIG. 28 .

Fig. 32 is a schematic cross-sectional view illustrating the cross-sections along the cross-section lines A-A', B-B' and C-C' of Fig. 30.

33 is a schematic cross-sectional view illustrating part of the process of preparing a semiconductor device according to another embodiment of the present disclosure.

34 and 35 are enlarged cross-sectional schematic views, illustrating the cross-sections of areas A1 and A2 in FIG. 33 .

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

In addition, for ease of explanation, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Relative terms used to describe the relationship between one element or feature shown in a figure and another (Other) relationship between components or features. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when one component is formed on, connected to, and/or coupled to another component, it may include forming direct contact between those components. examples, and may also include embodiments in which additional components are formed between the components so that the components are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

Unless otherwise specified in the content, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, Then terms such as "same", "equal", "planar", or "coplanar" as used in this article are not necessary means an exactly identical orientation, arrangement, position, shape, size, quantity, or other measurement, but it means a nearly identical orientation, arrangement, position, shape, size, within acceptable differences , quantity, or other measurement, and the acceptable differences may occur due to manufacturing processes, for example. The term "substantially" may be used herein to mean Show this meaning. For example, as substantially the same, substantially equal, or substantially planar, as exactly the same, equal, or planar, or It may be the same, equal, or flat within acceptable differences that may occur due to the manufacturing process, for example.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a A semiconductor circuit (semiconductor circuit) and an electronic device (electronic device) are both included in the category of semiconductor components.

It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow. .

It should be understood that the terms "forming", "formed" and "form" can mean and include any creating, building, patterning, planting. A method of implanting or depositing an element, a dopant or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), depositing (depositing), growing (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but are not limited thereto.

It should be understood that in the description of the present disclosure, the functions or steps mentioned in the text May occur in a different order than in each diagram. For example, two diagrams shown in succession may actually be executed at approximately the same time, or sometimes in the reverse order, depending on the functions or steps involved.

FIG. 1 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 20 are schematic cross-sectional views illustrating part of the process of preparing the semiconductor device 1A according to an embodiment of the present disclosure. 23 and 24 are enlarged cross-sectional schematic views, illustrating the cross-sections of areas A1 and A2 in FIG. 22 . 25 and 26 are schematic cross-sectional views illustrating part of the process of preparing the semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIGS. 1 to 10 , in step S11 , a first stacked structure 100 may be provided, and a plurality of first interconnect units 510 may be formed below the first stacked structure 100 .

Referring to FIG. 2, a first controller die 110 may be provided. The first controller die 110 may include a substrate 111 , a plurality of through-substrate vias 115 , a plurality of device components (not shown for clarity), a plurality of conductive features having a plurality of conductive pads 117 , and a dielectric layer. 113.

In some embodiments, the substrate 111 of the first controller die 110 may be a block-shaped semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof; the elemental semiconductor is such as silicon or germanium; the compound semiconductor is such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, Indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the through-substrate vias 115 of the first controller die 110 may be formed in the substrate 111 . Each upper surface of the through-substrate through holes 115 may be substantially coplanar with the upper surface of the substrate 111 . In some embodiments, the fabrication technique of the through-substrate vias 115 may include a via-first process. In some embodiments, the through-base The manufacturing technology of the bottom via 115 may include a via-middle process or a via-last process.

In some embodiments, a plurality of device elements of first controller die 110 may be formed on substrate 111 . The plurality of device elements may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect semiconductors, the like, or combinations thereof.

In some embodiments, dielectric layer 113 may be formed on substrate 111 . The dielectric layer 113 may be a stacked layer structure. The dielectric layer 113 may include a plurality of isolation sub-layers. Each spacer sub-layer may have a thickness ranging from about 0.5 μm to about 3.0 μm. For example, the isolation sublayers may include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like, or combinations thereof . The isolation sub-layers may include different materials, but are not limited thereto.

A low dielectric constant dielectric material may have a dielectric material that is less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. The manufacturing technology of the isolation sub-layers may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or similar processes. Following these deposition processes, multiple planarization processes may be performed to remove excess material and provide a generally flat surface for subsequent processing steps.

In some embodiments, the conductive features of first controller die 110 may be formed in dielectric layer 113 . The conductive features may include conductive lines (not shown), conductive vias (not shown), and conductive pads 117 . The conductive lines may be spaced apart from each other and may be horizontally disposed in the dielectric layer 113 along the direction Z. In this embodiment, the uppermost conductive lines may be designated as conductive pads 117 . Each upper surface of the conductive pads 117 and the upper surface of the dielectric layer 113 The surfaces may be approximately coplanar. The conductive vias can connect adjacent conductive features.

In some embodiments, for example, the conductive features of first controller die 110 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide , titanium magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. These conductive features may be formed during formation of dielectric layer 113 .

In some embodiments, the device elements of the first controller die 110 and the conductive features may be configured together into functional units of the first controller die 110 . In the description of this disclosure, a functional unit generally refers to a functionally related circuit that has been divided into a distinct unit for multiple functional purposes. In some embodiments, for example, the functional circuits of the first controller die 110 may include multiple highly complex circuits, such as memory controllers or accelerator units. In some embodiments, the functional units of the first controller die 110 may include control circuitry and high-speed circuitry associated with a memory die. In some embodiments, the first controller die 110 may be configured as a controller of a memory die.

It should be understood that in the description of the present disclosure, the term "front" surface is a technical term that implies the main surface of a structure on which device elements and conductive features are formed. Likewise, the "back" surface of a structure is the side opposite the main surface. For example, the upper surface of the dielectric layer 113 may be represented as the front surface 110FS of the first controller die 110 . The lower surface of the substrate 111 may be represented as the back surface 110BS of the first controller die 110 .

It should be understood that in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical plane along the direction Z represents an upper surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical plane along direction Z represents the lower surface of the element (or the feature).

Referring to FIG. 3 , a first storage die 120 may be provided. The first storage die 120 may include a substrate 121, a plurality of through-substrate through holes 125, a plurality of device components (not shown in the figure for simplicity), a plurality of conductive features including a plurality of conductive pads 127, a plurality of first storage unit 129 and a dielectric layer 123. The device elements of the substrate 121, the dielectric layer 123, the first storage die 120, and the conductive features of the first storage die 120 may respectively and correspondingly include components similar to the substrate 111, the dielectric layer 113, the first control The structure/materials of the device elements of the device die 110 and the conductive features of the first controller die 110 are described, and their descriptions will not be repeated herein.

In some embodiments, the first memory cells 129 may be formed in the dielectric layer 123 . The plurality of first storage cells 129 may be configured into a floating array. The plurality of first memory cells 129 may be electrically coupled to the conductive features of the first memory die 120 . In some embodiments, the device elements and the conductive features of the first storage die 120 may be configured together into the functional units of the first storage die 120 .

In some embodiments, the functional units of the first storage die 120 may only include core storage circuits, such as input/output (I/O) and clocking circuits. The functional units of the first storage chip 120 may not include any control circuits or high-speed circuits. In this case, the first storage die 120 may cooperate with the first controller die including control circuits and/or high-speed circuits. By isolating the control circuit and/or the high-speed circuit from the first storage die, the process complexity of manufacturing the first storage die 120 can be reduced. Therefore, the yield and reliability of manufacturing the first storage die 120 can be improved, and the cost of manufacturing the first storage die 120 can be reduced.

In some embodiments, the functional units of the first storage die 120 may include storage circuits, control circuits, and high-speed circuits. In some embodiments, the first storage die 120 can be configured as a memory die.

In some embodiments, the upper surface of the dielectric layer 123 may be regarded as the upper surface 120FS of the first storage die 120 . The lower surface of the base 121 can be regarded as the back surface 120BS of the first storage die 120 .

Referring to FIG. 4, the first storage die 120 can be flipped. The front surface 120FS of the first storage die 120 may be bonded to the front surface 110FS of the first controller die 110 . That is, the first storage die 120 and the first controller die 110 are bonded in a face-to-face configuration.

In some embodiments, the first storage die 120 and the first controller die 110 may be bonded through a hybrid bonding process. In some embodiments, a hybrid bonding process such as thermocompression bonding, passivation-capping-layer assisted bonding, or surface activation bonding is used. In some embodiments, the process pressure for hybrid process bonding may range from about 100 MPa to about 150 MPa. In some embodiments, the process temperature for hybrid process bonding may range from approximately room temperature (eg, 25°C) to approximately 400°C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase heat treatment can be used to reduce the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process. In some embodiments, a hybrid bonding process may include dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding, for example.

In some embodiments, a dielectric-to-dielectric bond may originate from a bond between dielectric layer 113 and dielectric layer 123 . Metal-to-metal bonding may result from the bonding between the conductive pads 117 and the conductive pads 127 . Metal-to-dielectric bonds may result from bonds between the conductive pads 127 and the dielectric layer 113 , as well as from bonds between the conductive pads 117 and the dielectric layer 123 .

In some embodiments, after the bonding process, a thermal annealing process may be performed. process to enhance dielectric-to-dielectric bonding and generate thermal expansion of metal-to-metal bonding to further improve bonding quality.

In some embodiments, the bonding process of the first storage die 120 and the first controller die 110 can be assisted by a carrier, but is not limited to this.

Referring to FIG. 5 , the substrate 121 of the first storage die 120 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. In some embodiments, the thinning process of the first storage die 120 can be assisted by a carrier, but it is not limited to this. After the thinning process, the thickness of the substrate 121 may range from about 5 μm to about 100 μm.

Referring to FIG. 5 , a first through-die via 411 may be formed along the first storage die 120 to electrically connect to the first controller die 110 . In detail, the first through-die via 411 may be formed along the substrate 121 and the dielectric layer 123 , formed on the corresponding conductive pad 117 and electrically connected to the corresponding conductive pad 117 .

Referring to FIG. 6 , a first storage die 130 is provided, which has a structure similar to the first storage die 120 , and its description will not be repeated herein. The front surface 130FS of the first storage die 130 may be bonded to the back surface 120BS of the first storage die 120 . That is, the first storage die 130 and the first storage die 120 may be arranged face to face for bonding. The plurality of conductive pads 137 of the first storage die 130 may be electrically connected to the corresponding through-substrate vias 125 .

Referring to FIG. 7 , the substrate 131 of the first storage die 130 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. In some embodiments, the thinning process of the first storage die 130 may A carrier is used as an auxiliary, but is not limited to this. After the thinning process, the thickness of the substrate 131 may range from about 5 μm to about 100 μm.

Referring to FIG. 7 , a second through-die via 421 may be formed along the first storage dies 120 and 130 to electrically connect to the first controller die 110 . In detail, the second through-die via 421 may be formed along the substrate 131, the dielectric layer 133, the substrate 121, and the dielectric layer 123, be formed on the corresponding conductive pad 117, and be electrically connected to the corresponding conductive pad 117. conductive pad 117.

In some embodiments, a width W1 of the first through-die via 411 may be smaller than a width W2 of the second through-die via 421 .

Please refer to FIGS. 8 and 9 , first storage dies 140 , 150 , 160 , and 170 may be provided respectively, and the first storage dies 140 , 150 , 160 , and 170 have a structure similar to the first storage die 120 , and Its description will not be repeated in the text. The first storage dies 140 , 150 , 160 , and 170 may be sequentially bonded to the first storage die 130 through a bonding process similar to that between the first storage die 120 and the first storage die 130 . The bonding process and its description will not be repeated in the text.

In some embodiments, a third through-die via 431 may be formed along the first storage dies 120 , 130 , 140 to electrically connect to the first controller die 110 . The third through-die through hole 431 may have a width that is greater than the widths of the first through-die through hole 411 and the second through-die through hole 421 . In some embodiments, the first storage dies may be electrically connected through a plurality of fourth through-die vias 441 . For example, the fourth through-die via 441 may be formed along the first storage dies 160 and 170 to electrically connect the first storage dies 160 and 170 . As another example, the fourth through-die via 441 may be formed along the first storage dies 140 and 150 to electrically connect the first storage dies 140 and 150 .

The first storage die 120, 130, 140, 150, 160, 170, the first control The die 110 , the first through-die via 411 , the second through-die via 421 , the third through-die via 431 and the fourth through-die via 441 may be configured together into the first stack structure 100 . The first stack structure 100 may be configured as a non-volatile memory, such as a NAND memory. It should be understood that the number of first storage dies is for illustrative purposes only, and the number of first storage dies may be greater or less than that shown in the figures.

Referring to FIG. 10 , the substrate 111 of the first control die 110 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. After the thinning process, the through-substrate vias 115 may be exposed.

In some embodiments, because the first storage dies 120, 130, 140, 150, 160, 170 can be used as a temporary carrier without a The carrier is used to perform the thinning process of the first controller die 110 . Therefore, the cost and process complexity can be reduced. After the thinning process, the thickness of the substrate 111 may be between approximately 5 μm and 100 μm.

In some embodiments, the thickness T1 of the first controller die 110 may be smaller than the thickness T2 of the first storage die 120 . In some embodiments, the thickness 110 of the first controller die 110 may be substantially the same as the thickness T2 of the first storage die 120 .

Referring to FIG. 10 , the first internal connection units 510 may be formed under the substrate 111 and electrically connected to the through-substrate through holes 115 respectively and correspondingly. In some embodiments, the first interconnect units 510 may be microbumps and may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the first internal connection units 510 may be solder balls and may be formed under the substrate 111 through a hot pressing process and/or a reflow process.

Referring to FIG. 1 and FIG. 11 to FIG. 19 , in step S13 , a second stacked structure 200 may be provided, and a plurality of second internal connection units 520 may be formed below the second stacked structure 200 .

Referring to FIG. 11, a second controller die 210 may be provided. The second controller die 210 may include a substrate 211, a plurality of through-substrate vias 215, a plurality of device components (not shown for simplicity), a plurality of conductive features including a plurality of conductive pads 217, and a dielectric layer. 213.

In some embodiments, the substrate 211 of the second controller die 210 may be a block-shaped semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof; the elemental semiconductor is such as silicon or germanium; the compound semiconductor is such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, Indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the through-substrate vias 215 of the second controller die 210 may be formed in the substrate 211 . Each upper surface of the through-substrate through holes 215 may be substantially coplanar with the upper surface of the substrate 211 . In some embodiments, the fabrication technique of the through-substrate vias 215 may include a via-first process. In some embodiments, the manufacturing technology of the through-substrate vias 215 may include a via-middle process or a via-last process.

In some embodiments, a plurality of device elements of the second controller die 210 may be formed on the substrate 211 . The plurality of device elements may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect semiconductors, the like, or combinations thereof.

In some embodiments, dielectric layer 213 may be formed on substrate 211 . The dielectric layer 213 may be a stacked layer structure. The dielectric layer 213 may include a plurality of isolation sub-layers. every isolation The sub-layer may have a thickness between about 0.5 μm and about 3.0 μm. For example, the isolation sublayers may include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like, or combinations thereof . The isolation sub-layers may include different materials, but are not limited thereto.

The manufacturing technology of the isolation sub-layers may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or similar processes. Following these deposition processes, multiple planarization processes may be performed to remove excess material and provide a generally flat surface for subsequent processing steps.

In some embodiments, the conductive features of second controller die 210 may be formed in dielectric layer 213 . The conductive features may include conductive lines (not shown), conductive vias (not shown), and conductive pads 217 . The conductive lines may be spaced apart from each other and may be horizontally disposed in the dielectric layer 213 along the direction Z. In this embodiment, the uppermost conductive lines may be designated as conductive pads 217 . The upper surfaces of the conductive pads 217 and the upper surface of the dielectric layer 213 may be substantially coplanar. The conductive vias may connect adjacent conductive features, connect adjacent device components to conductive lines, and connect adjacent conductive pads 117 to conductive lines along the Z direction.

In some embodiments, for example, the conductive features of the second controller die 210 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide , titanium magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. These conductive features may be formed during formation of dielectric layer 213 .

In some embodiments, the device elements of the second controller die 210 and the conductive features may be configured together into functional units of the second controller die 210 . In some embodiments, for example, the functional circuits of the second controller die 210 may include multiple highly complex circuits, such as memory controllers or accelerator units. In some embodiments, the second The functional units of the controller die 210 may include control circuitry and high-speed circuitry associated with a memory. In some embodiments, the second controller die 210 may be configured as a controller die of a memory die.

In some embodiments, the upper surface of dielectric layer 213 may be represented as front surface 210FS of second controller die 210 . The lower surface of the substrate 211 may be represented as the back surface 210BS of the second controller die 210 .

Referring to Figure 12, a second storage die 220 may be provided. The second storage die 220 may include a substrate 221, a plurality of through-substrate through holes 225, a plurality of device components (not shown for simplicity), a plurality of conductive features including a plurality of conductive pads 227, and a plurality of second storage devices. Cell 229 and a dielectric layer 223. The device elements of the substrate 221, the dielectric layer 223, the second storage die 220, and the conductive features of the second storage die 220 may respectively and correspondingly include components similar to the substrate 211, the dielectric layer 213, the second control The structure/materials of the device elements of the device die 210 and the conductive features of the second controller die 210 are described, and their descriptions will not be repeated herein.

In some embodiments, the second storage cells 229 may be formed in the dielectric layer 223 . Each second storage unit 229 may include an insulator-conductor-insulator structure. The second storage units 229 may be electrically coupled to the conductive features of the second storage die 220 respectively and correspondingly. In some embodiments, the device elements and the conductive features of the second storage die 220 may be configured together into the functional units of the second storage die 220 .

In some embodiments, the functional units of the second storage die 220 may only include core storage circuits, such as input/output (I/O) and clocking circuits. The functional units of the second storage chip 220 may not include any control circuits or high-speed circuits. In this case, the first storage die 120 may be connected to a third memory chip including a control circuit and/or a high-speed circuit. The two controller dies 210 cooperate. By isolating the control circuit and/or the high-speed circuit from the second storage die 220, the process complexity of manufacturing the second storage die 220 can be reduced. Therefore, the yield and reliability of manufacturing the second storage die 220 can be improved, and the cost of manufacturing the second storage die 220 can be reduced.

In some embodiments, the functional units of the second storage die 220 may include storage circuits, control circuits, and high-speed circuits. In some embodiments, the second storage die 220 may be configured as a memory die.

In some embodiments, the upper surface of the dielectric layer 223 may be regarded as the upper surface 220FS of the second storage die 220 . The lower surface of the base 221 can be regarded as the back surface 220BS of the second storage die 220 .

Referring to FIG. 13, the second storage die 220 can be flipped. The front surface 220FS of the second storage die 220 may be bonded to the front surface 210FS of the second controller die 210 . That is, the second storage die 220 and the second controller die 210 are bonded in a face-to-face configuration.

In some embodiments, the second storage die 220 and the second controller die 210 may be bonded through a hybrid bonding process. In some embodiments, a hybrid bonding process such as thermocompression bonding, passivation-capping-layer assisted bonding, or surface activation bonding is used. In some embodiments, the process pressure for hybrid process bonding may range from about 100 MPa to about 150 MPa. In some embodiments, the process temperature for hybrid process bonding may range from approximately room temperature (eg, 25°C) to approximately 400°C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase heat treatment can be used to reduce the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process. In some embodiments, hybrid bonding processes may include dielectric-to-dielectric bonding, metal-to-metal bonding, for example. Bonding and metal-to-dielectric joining.

In some embodiments, a dielectric-to-dielectric bond may originate from a bond between dielectric layer 213 and dielectric layer 223 . Metal-to-metal bonding may result from the bonding between the conductive pads 217 and 227 . Metal-to-dielectric bonds may result from bonds between the conductive pads 227 and the dielectric layer 213 , as well as from bonds between the conductive pads 217 and the dielectric layer 223 .

In some embodiments, after the bonding process, a thermal annealing process may be performed to strengthen the dielectric-to-dielectric bond and generate thermal expansion of the metal-to-metal bond to further improve bonding quality.

In some embodiments, the bonding process of the second storage die 220 and the second controller die 210 can be assisted by a carrier, but is not limited thereto.

Referring to FIG. 14 , the substrate 221 of the second storage die 220 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. In some embodiments, the thinning process of the second storage die 220 can be assisted by a carrier, but it is not limited to this. After the thinning process, the thickness of the substrate 221 may range from about 5 μm to about 100 μm.

Referring to FIG. 14 , a first through-die via 413 may be formed along the second storage die 220 to electrically connect to the second controller die 210 . In detail, the first through-die via 413 may be formed along the substrate 221 and the dielectric layer 223 , formed on the corresponding conductive pad 217 and electrically connected to the corresponding conductive pad 217 .

Referring to FIG. 15 , a second storage die 230 is provided, which has a structure similar to the second storage die 220 , and its description will not be repeated herein. The front surface 230FS of the second storage die 230 may be bonded to the back surface 220BS of the second storage die 220 . That is to say, the second storage The storage die 230 and the second storage die 220 may be bonded in a face-to-face configuration. The plurality of conductive pads 237 of the second storage die 230 may be electrically connected to the corresponding through-substrate vias 225 .

Referring to FIG. 16 , the substrate 231 of the second storage die 230 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. In some embodiments, the thinning process of the second storage die 230 can be assisted by a carrier, but it is not limited to this. After the thinning process, the thickness of the substrate 231 may range from about 5 μm to about 100 μm.

Referring to FIG. 16 , a second through-die via 423 may be formed along the second storage dies 220 and 230 to electrically connect to the second controller die 210 . In detail, the second through-die via 423 may be formed along the substrate 231, the dielectric layer 233, the substrate 221, and the dielectric layer 223, be formed on the corresponding conductive pad 217, and be electrically connected to the corresponding conductive pad 217. conductive pad 217.

In some embodiments, the width W3 of the first through-substrate via hole 413 may be smaller than the width W4 of the second through-substrate via hole 423 .

Referring to FIG. 17 and FIG. 18 , second storage dies 240 and 250 may be provided respectively, which have a structure similar to the second storage die 220 , and their description will not be repeated herein. The second storage dies 240 and 250 may be sequentially bonded to the second storage die 230 in a process similar to the bonding process between the second storage die 220 and the second storage die 230, and in Its description will not be repeated in the text.

In some embodiments, a third through-die via 433 is formed along the second memory die 220 , 230 , 240 to electrically connect to the second controller die 210 . The third through-die through hole 433 may have a width that is greater than the widths of the first through-die through hole 413 and the second through-die through hole 423 . In some embodiments, the second storage dies may be configured via a plurality of third The four through-die through holes 443 are electrically connected. For example, the fourth through-die via 443 may be formed along the second storage dies 240 and 250 to electrically connect the second storage dies 240 and 250 . As another example, the fourth through-die via 443 may be formed along the second storage dies 230 and 240 to electrically connect the second storage dies 230 and 240 .

The second storage die 220, 230, 240, 250, the second control die 210, the first through-die through hole 413, the second through-die through hole 423, the third through-die through hole 433, and the fourth through-die through hole 413. Die vias 443 may be configured together into the second stacked structure 200 . The second stack structure 200 may be configured as a volatile memory, such as a dynamic random access memory. It should be understood that the number of second storage dies is only for illustration, and the number of second storage dies may be greater or smaller than the number shown in the figure.

Referring to FIG. 18 , the substrate 211 of the second control die 210 can be thinned through a thinning process using wafer grinding, mechanical abrasion, polishing or polishing. A similar process may use chemical removal, such as a wet etch. After the thinning process, the through-substrate vias 225 may be exposed.

In some embodiments, because the second storage dies 220, 230, 240, 250 can be used as a temporary carrier without a carrier to execute the second controller chip. This thinning process of grain 210 is carried out. Therefore, the cost and process complexity can be reduced. After the thinning process, the thickness of the substrate 211 may be between approximately 5 μm and 100 μm.

In some embodiments, the thickness T3 of the second controller die 210 may be smaller than the thickness T4 of the second storage die 220 . In some embodiments, the thickness T3 of the second controller die 210 may be substantially the same as the thickness T4 of the second storage die 220 .

Referring to FIG. 19 , the second internal connection units 520 may be formed under the substrate 211 square, and are electrically connected to the through-substrate vias 215 respectively and correspondingly. In some embodiments, the second interconnect units 520 may be microbumps and may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the second internal connection units 520 may be solder balls and may be formed under the substrate 211 through a hot pressing process and/or a reflow process.

Please refer to FIG. 1 and FIG. 20 to FIG. 25. In step S15, a lower die 310 may be provided, the first stacked structure 100 may be bonded to the lower die 310, and the second stacked structure 200 may be bonded to the lower die 310. .

Referring to Figure 20, the lower die 310 may include a substrate 311, a plurality of through-substrate through holes 315, a plurality of device components (not shown for simplicity), a plurality of first connection pads 317 and a plurality of second connections. A plurality of conductive features on pad 319 and a dielectric layer 313 .

In some embodiments, the substrate 311 of the lower die 310 may be a block-shaped semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof; the elemental semiconductor is such as silicon or germanium; the compound semiconductor is such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, Indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the through-substrate vias 315 of the lower die 310 may be formed in the substrate 311 . Each upper surface of the through-substrate through holes 315 may be substantially coplanar with the upper surface of the substrate 311 . In some embodiments, the fabrication technique of the through-substrate vias 315 may include a via-first process. In some embodiments, the manufacturing technology of the through-substrate vias 315 may include a via-middle process or a via-last process.

In some embodiments, device elements of lower die 310 may be formed on on base 311. The plurality of device elements may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect semiconductors, the like, or combinations thereof.

In some embodiments, dielectric layer 313 may be formed on substrate 311 . The dielectric layer 313 may be a stacked layer structure. Dielectric layer 313 may include a plurality of isolation sub-layers. Each spacer sub-layer may have a thickness ranging from about 0.5 μm to about 3.0 μm. For example, the isolation sublayers may include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like, or combinations thereof . The isolation sub-layers may include different materials, but are not limited thereto.

The manufacturing technology of the isolation sub-layers may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or similar processes. Following these deposition processes, multiple planarization processes may be performed to remove excess material and provide a generally flat surface for subsequent processing steps.

In some embodiments, the conductive features of lower die 310 may be formed in dielectric layer 313 . The conductive features may include a plurality of conductive lines (not shown), a plurality of conductive vias (not shown), and a plurality of first connection pads 317 and a plurality of second connection pads 319 . The conductive lines may be spaced apart from each other and may be horizontally disposed in the dielectric layer 313 along the direction Z. In this embodiment, the uppermost conductive lines may be designated as the first connection pads 317 and the second connection pads 319 . The upper surfaces of the first connection pads 317 , the upper surfaces of the second connection pads 319 and the upper surface of the dielectric layer 313 may be substantially coplanar. The conductive vias can connect adjacent conductive lines along direction Z, connect adjacent device components and conductive lines, connect adjacent first connection pads 317 and conductive lines, and connect adjacent second connection pads 319 with conductive thread.

In some embodiments, within a given area, the first connection pads The number 317 may be smaller than the number of the second connection pads 319 . In other words, the pad density of the first connection pads 317 may be smaller than the pad density of the second connection pads 319 .

In some embodiments, for example, the conductive features of lower die 310 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, titanium carbide Magnesium), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. These conductive features may be formed during formation of dielectric layer 313 .

In some embodiments, the device elements of lower die 310 and the conductive features may be configured together into functional units of first controller die 110 . In some embodiments, for example, the functional circuits of lower die 310 may include multiple highly complex circuits, such as processor cores, memory controllers, or accelerator units. In some embodiments, the functional units of lower die 310 may include control circuits and high-speed circuits. In some embodiments, lower die 310 may be configured as a logic die.

Referring to FIG. 21 , the first stacked structure 100 may be formed on the lower die 310 via the first interconnect units 512 . The first internal connection units 510 may be formed on the first connection pads 317 and be electrically connected to the first connection pads 317 . In some embodiments, the bonding between the first stacked structure 100 and the lower die 310 may use a hot pressing process and/or a reflow process.

Referring to FIG. 21 , the second stacked structure 200 may be formed on the lower die 310 through the second interconnect units 520 . The second internal connection units 520 may be formed on the second connection pads 319 and be electrically connected to the second connection pads 319 . In some embodiments, the bonding between the second stacked structure 200 and the lower die 310 may use a hot pressing process and/or a reflow process.

In some embodiments, the number of the second internal connection units 520 may be greater than The number of the first internal connection units 510 . In some embodiments, the thickness T1 of the first controller die 110 and the thickness T3 of the second controller die 210 may be substantially the same. In some embodiments, the thickness T5 of the first stacked structure 100 and the thickness T6 of the second stacked structure 200 may be substantially the same. In some embodiments, the thickness T3 of the first storage die 120 may be smaller than the thickness T4 of the second storage die 220 . In some embodiments, the number of first storage dies 120, 130, 140, 150, 160, 170 may be greater than the number of second storage dies 220, 230, 240, 250.

Referring to FIGS. 22 to 24 , a plurality of underfill layers 601 may be filled between the first stacked structure 100 and the lower die 310 , and between the second stacked structure 200 and the lower die 310 . The underfill layers 601 may surround the first interconnect units 510 and the second interconnect units 520 . In some embodiments, the underfill layers 601 may also seal a portion of each side (eg, side surface) of the first stacked structure 100 and the second stacked structure 200 .

In some embodiments, the fabrication technique of the underfill layers 601 may include curing an underfill material composed of a cross-linked organic resin and low coefficient of thermal expansion (CTE) non-organic particles (eg, 75 wt. percentage). In some embodiments, the underfill material prior to curing may be combined with a liquid resin such as epoxy, a hardener such as anhydrides or amines, an elastomer for toughness, or an elastomer for toughness. Formulated with a catalyst to promote cross-linking and other additives for flow improvement and adhesion.

The underfill layers 601 can be tightly adhered to the first stacked structure 100 , the second stacked structure 200 and the lower die 310 , so that the underfill layers 601 can be re-formed on the first stacked structure 100 and the second stacked structure 200 Distribute stresses and strains from CTE mismatches and mechanical impacts. Therefore, the initiation and growth of cracks in the first interconnected units 510 and the second interconnected units 520 can be prevented or significantly reduced. In addition, the bottom The internal filling layer 601 can provide protection for the first interconnection units 510 and the second interconnection units 520 to improve the mechanical integrity of the arrangement of the lower die 310 and the first stacked structure 100 and the second stacked structure 200 Mechanical integrity. Furthermore, the underfill layers 601 may provide partial protection from moisture ingress and other forms of contamination.

Referring to FIGS. 22 to 24 , a molding layer 603 may be formed to cover the first stacked structure 100 and the second stacked structure 200 . The molding layer 603 may include a molding compound such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride. (ammonium bifluoride). The manufacturing technology of the molding layer 603 may include compression molding, transfer molding, liquid encapsulant molding or similar molding methods. For example, a molding compound is dispensed in liquid form. Next, a curing process may be performed to solidify the molding compound. The formation of the molding compound may overflow the first stacking structure 100 and the second stacking structure 200 so that the molding compound covers the first stacking structure 100 and the second stacking structure 200 .

Referring to FIG. 25 , a planarization process such as chemical mechanical polishing may be performed until the first stacked structure 100 and the second stacked structure 200 are exposed. A heat dissipation layer (not shown) may be formed on the first stacked structure 100 and the second stacked structure 200 to improve heat dissipation capability. In some embodiments, the planarization process is optional.

Referring to FIGS. 1 and 26 , in step S17 , the lower die 310 may be bonded to a base substrate 605 .

Referring to Figure 26, a base substrate 605 may be provided. The base substrate 605 may be a laminate, but is not limited thereto. In some embodiments, base substrate 605 may include an epoxy-based material or bismaleimide triazine. In some embodiments, the base The base 605 may be a printed circuit board. The lower die 310 and the base substrate 605 may be bonded via a plurality of third interconnect units 530 . The third interconnect units 530 may be formed between the lower die 310 and the base substrate 605 . The third internal connection units 530 may be electrically connected to the through-substrate vias 315 respectively and correspondingly. In some embodiments, the third interconnect units 530 may be solder balls and may be formed between the lower die 310 and the base substrate 605 using a hot pressing process and/or a reflow process.

FIG. 27 is an enlarged cross-sectional schematic diagram illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

In the semiconductor device 1B, the through-substrate via 115 may include a filling layer FL, a seed layer SL, an adhesive layer AL, a barrier layer BL and an insulating layer IL.

In some embodiments, the filling layer FL may be formed along the substrate 111 of the first controller die 110 and be electrically connected to the corresponding first interconnect unit 510 . For example, the filling layer FL may include doped polycrystalline silicon, tungsten, copper, carbon nanotubes or solder alloy.

In some embodiments, the insulating layer IL may be formed between the filling layer FL and the substrate 111 . In some embodiments, for example, the insulating layer IL may include silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The insulating layer IL may have a thickness ranging from about 50 nm to about 200 nm. In some embodiments, for example, the insulating layer IL may include parylene (trade name: Parylene), epoxy resin (epoxy) or poly(p-xylene). . The insulating layer IL may have a thickness ranging from about 1 μm to about 5 μm. The insulating layer IL can ensure that the filling layer FL is electrically insulated in the substrate 111 .

In some embodiments, the seed layer SL may be formed between the filling layer FL and the insulating layer between IL. In some embodiments, the seed layer SL may have a thickness ranging from about 10 nm to about 40 nm. In some embodiments, for example, the seed layer SL may include at least one of the following groups: aluminum, gold, beryllium, bismuth, cobalt, copper, hafnium, indium, manganese, molybdenum, nickel, lead, palladium, platinum , rhodium, rhenium, gallium, tantalum, tellurium, titanium, tungsten, zinc and zirconium. The seed layer SL can reduce a resistivity of an opening during formation of the filling layer FL.

In some embodiments, the adhesion layer AL may be formed between the seed layer SL and the insulating layer IL. For example, the seed layer SL may include titanium, tantalum, titanium tungsten, or manganese nitride. The seed layer SL can improve the adhesion between the seed layer SL and the barrier layer BL.

In some embodiments, the barrier layer BL may be between the adhesive layer AL and the insulating layer IL. For example, the barrier layer BL may include tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride/tantalum layer. The barrier layer BL can prevent the conductive material of the filling layer FL from diffusing into the substrate 111 .

In some embodiments, other through-substrate vias or through-die vias may have structures similar to the through-substrate vias 115 , and their description will not be repeated herein.

FIG. 28 is a schematic cross-sectional view illustrating part of the process of preparing a semiconductor device 1C according to another embodiment of the present disclosure. FIG. 29 is an enlarged schematic cross-sectional view illustrating the cross-section of area A1 in FIG. 28 . Fig. 30 is a schematic cross-sectional view illustrating the cross-sections along the cross-section lines A-A', B-B' and C-C' of Fig. 29. FIG. 31 is an enlarged schematic cross-sectional view illustrating the cross-section of area A2 in FIG. 28 . Fig. 32 is a schematic cross-sectional view illustrating the cross-sections along the cross-section lines A-A', B-B' and C-C' of Fig. 30.

Referring to FIG. 28 , an intermediate semiconductor device can be manufactured by a process similar to that described in FIGS. 2 to 21 , and its description will not be repeated herein. For simplicity, clarity, and ease of description, only one first internal connection unit 510 and one second internal connection unit 520 are described.

Referring to FIGS. 28 to 31 , in some embodiments, a first lower annular layer 515 may be formed on the first connection pad 317 . A first upper annular layer 517 may be formed under the through-substrate via 115 . In some embodiments, for example, the first lower annular layer 515 and the first upper annular layer 517 may include copper or other suitable metals or metal alloys.

The first internal connection unit 510 may include a first outer layer 511 and a first cavity 513 . The first outer layer 511 may be formed between the first lower annular layer 515 and the first upper annular layer 517 . The first outer layer 511 , the first lower annular layer 515 and the first upper annular layer 517 may respectively and correspondingly have an annular cross-sectional profile. The space surrounded by the through-substrate via 115 , the first upper annular layer 517 , the first outer layer 511 , the first lower annular layer 515 and the first connection pad 317 may be represented as a first chamber 513 .

In some embodiments, through the use of the first lower ring layer 515 on the first connection pad 317, a first "seed" point is created for the non-conductive/non-wetting center of the ring Accumulate vaporized flux. As the vapor expands during heating and liquefaction of the solder, a first internal cavity (not shown) is formed, and the internal cavity is contained by the surface tension and viscosity of the molten solder. By including a second seed point in the first upper annular layer 517 below the through-substrate via 115, a second internal chamber (not shown) is initiated that is identical to the first internal chamber. The chambers abut to create the resulting first chamber 513. The surface tension properties force a convex shape on the liquefied structure which, when cooled, solidifies into the barrel form of the first outer layer 511 as the shell solidifies before the vaporized flux inside shrinks.

In some embodiments, the first internal connection unit 510 may be a solder ball. A relative volume of the first chamber 513 may range from 1% to 90% of the total volume of the first internal connection unit 510 . The volume of the first chamber 513 can be controlled by controlling the temperature and time during solder heating. The composition of the solder should balance the properties of the solder and solder alloy as well as the properties of the flux vapor. An exemplary solder compound may be composed of any common solder material, such as solder, silver, and tin, and some portion of a flux selected from, for example, rosin, resin, activator, and thixotropic agent. and one or more of a group of high-temperature boiling solvents.

Referring to FIGS. 29 , 31 and 32 , in some embodiments, a second lower annular layer 525 may be formed on the second connection pad 319 . A second upper annular layer 527 may be formed below the through-substrate via 215 . In some embodiments, for example, the second lower annular layer 525 and the second upper annular layer 527 may include copper or other suitable metals or metal alloys.

The second internal connection unit 520 may include a second outer layer 521 and a second cavity 523 . The second outer layer 521 may be formed between the second lower annular layer 525 and the second upper annular layer 527 . The second outer layer 521 , the second lower annular layer 525 and the second upper annular layer 527 may respectively and correspondingly have an annular cross-sectional profile. The space surrounded by the through-substrate via 215 , the second upper annular layer 527 , the second outer layer 521 , the second lower annular layer 525 and the second connection pad 319 may be represented as a second chamber 523 .

In some embodiments, through the use of the second lower ring layer 525 on the second connection pad 319, a first "seed" point is created for the non-conductive/non-wetting center of the ring Accumulate vaporized flux. As the vapor expands during heating and liquefaction of the solder, a first internal cavity (not shown) is formed, and the internal cavity is contained by the surface tension and viscosity of the molten solder. By including a second seed point in the first upper annular layer 527 below the through-substrate via 215, a second internal chamber (not shown) is initiated that is identical to the first internal chamber. The chambers abut to create the resulting first chamber 523. The surface tension properties force a convex shape on the liquefied structure which, when cooled, solidifies into the barrel-shaped form of the first outer layer 521 as the shell solidifies before the vaporized flux inside shrinks.

In some embodiments, the second internal connection unit 520 may be a solder ball. A relative volume of the second chamber 523 may be between 1% and 90% of the total volume of the first internal connection unit 510 . The volume of the second chamber 523 can be controlled by controlling the temperature and time during solder heating. The composition of the solder should balance the properties of the solder and solder alloy as well as the properties of the flux vapor. An exemplary solder compound may be composed of any common solder material, such as solder, silver, and tin, and some portion of a flux selected from, for example, rosin, resin, activator, and thixotropic agent. and one or more of a group of high-temperature boiling solvents.

FIG. 33 is a schematic cross-sectional view illustrating part of the process of preparing a semiconductor device 1C according to another embodiment of the present disclosure. 34 and 35 are enlarged cross-sectional schematic views, illustrating the cross-sections of areas A1 and A2 in FIG. 33 .

Referring to FIGS. 33 to 35 , the underfill layers 601 , the molding layer 603 , the third interconnect units 530 and the base substrate 605 may be formed by a process similar to that described in FIGS. 22 to 26 . And its description will not be repeated in the text.

During the fabrication or operation of the semiconductor device 1C, potentially damaging stresses may be neutralized and reduced by the first interconnect unit 510 including the first cavity 513 and the second interconnect unit 520 including the second cavity 523 or remove. Therefore, the yield and reliability of the semiconductor element 1C can be improved.

An embodiment of the present disclosure provides a semiconductor device including a lower die; a first stack structure including a first controller die disposed on the lower die; and a plurality of first storage dies stacked on the lower die. on the first controller die; a second stack structure including a second controller die disposed on the lower die; and a plurality of second storage dies stacked on the second controller die superior. The plurality of first storage dies respectively include a plurality of first storage cells. element, which is configured as a floating array. The plurality of second storage dies includes a plurality of second storage units, each of which includes an insulator-conductor-insulator structure.

Another embodiment of the present disclosure provides a semiconductor device including a lower die; a first stacked structure disposed on the lower die via a plurality of first interconnect units; and a second stacked structure via a plurality of first interconnect units. The second interconnect unit is disposed on the lower die. The first stacked structure includes: a first controller die disposed on the plurality of first interconnect units; a plurality of first storage dies stacked on the first controller die and configured to form a floating array. The second stacked structure includes: a second controller die disposed on the plurality of second interconnect units; and a plurality of second storage dies stacked on the second controller die and each including An insulator-conductor-insulator structure.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a first stacked structure. The first stacked structure includes: a first controller die; and a plurality of first storage dies, stacked in sequence. On the first controller die; provide a second stack structure, the second stack structure includes: a second controller die; and a plurality of second storage dies, sequentially stacked on the second controller on the die; the first controller die is bonded to the lower die via a plurality of first interconnect units; and the second controller die is bonded to the lower die via a plurality of second interconnect units superior. The plurality of first storage dies respectively include a plurality of first storage cells, which are configured into a floating array. The plurality of second storage dies includes a plurality of second storage units, each of which includes an insulator-conductor-insulator structure.

Due to the design of the semiconductor device of the present disclosure, the first stacked structure 100 has the first storage units 129 in the form of a floating array, the second stacked structure 200 has the second storage units 229, and the second storage units 229 have These insulator-conductor-insulator structures, and the first stack structure 100 and the second stack structure 200 can be integrated with the lower die 310 rise. Therefore, the dimension of the semiconductor element 1A can be reduced. In addition, the through-substrate vias can also reduce a plurality of electrical paths within the first stacked structure 100 and/or the second stacked structure 200 so as to reduce power consumption. Therefore, the performance of the semiconductor device 1A can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components 100: First stack structure 110: First controller die 120: The first storage chip 130: The first storage chip 140: The first storage grain 150: The first storage chip 160: The first storage grain 170: The first storage chip 200: Second stack structure 210: Second controller die 220: Second storage grain 230: Second storage grain 240: Second storage grain 250: Second storage grain 310: Lower grain 311: Base 313: Dielectric layer 315:Through-substrate through hole 317: First connection pad 319: Second connection pad 510: First internal connection unit 520: Second internal connection unit 530: The third internal connection unit 601: Bottom filling layer 603: Molding layer 605: Base base Z: direction

Claims (35)

A semiconductor component, including: a lower die; a first stack structure, including: a first controller die, arranged on the lower die; and a plurality of first storage dies, stacked on the first controller on the die; a second stack structure, including: a second controller die disposed on the lower die; and a plurality of second storage dies stacked on the second controller die; wherein the The plurality of first storage dies respectively include a plurality of first storage cells, which are configured into a floating array; wherein the plurality of second storage dies include a plurality of second storage cells, which respectively include an insulator-conductor-insulator structure. . The semiconductor device of claim 1, wherein a thickness of the first controller die and a thickness of the second controller die are substantially the same. The semiconductor device of claim 1, wherein a thickness of one of the plurality of first memory cells is smaller than a thickness of one of the plurality of second memory dies. The semiconductor device of claim 1, wherein a thickness of the first stacked structure is substantially the same as a thickness of the second stacked structure. The semiconductor device according to claim 4, wherein the number of the plurality of first memory cells is greater than the number of the plurality of second memory dies. The semiconductor device according to claim 1, further comprising a first through-die through hole and a second through-die through hole, the first through-die through hole being disposed along one of the first storage units and disposed in On the first controller die and electrically connected to the first controller die, the second through-die via is disposed along at least two first storage dies and is disposed on the first controller die and electrically connected to the first controller die. The semiconductor device of claim 6, wherein a width of the second through-die via is greater than a width of the first through-die via. The semiconductor device according to claim 1, further comprising a plurality of first interconnection units and a plurality of second interconnection units, the plurality of first interconnection units being disposed between the first controller die and the lower die between, the plurality of second internal connection units are disposed between the second controller die and the lower die; wherein the plurality of first internal connection units are micro bumps or solder balls, and the plurality of first internal connection units are The second internal connection unit is a micro-bump or a solder ball. The semiconductor device according to claim 8, wherein the number of the plurality of first interconnected units is less than the number of the plurality of second interconnected units. The semiconductor device according to claim 9, wherein the lowest of the plurality of first storage units The surfaces are arranged on the first controller die in a face-to-face configuration. The semiconductor device of claim 9, further comprising: an underfill layer disposed between the first controller die and the lower die and surrounding the plurality of first interconnect units; and a molding A layer is disposed on the lower die and surrounds the first stacked structure and the second stacked structure. A semiconductor element, including: a lower die; a first stacked structure arranged on the lower die via a plurality of first internal connection units; and a second stacked structure arranged via a plurality of second internal connection units on the lower die; wherein the first stacked structure includes: a first controller die disposed on the plurality of first interconnect units; a plurality of first storage dies stacked on the first controller on the die and configured into a floating array; wherein the second stack structure includes: a second controller die disposed on the plurality of second interconnect units; and a plurality of second storage dies stacked on the on the second controller die, and each includes an insulator-conductor-insulator structure. The semiconductor device of claim 12, wherein the plurality of first interconnect units respectively include a first outer layer and a first cavity, the first outer layer is disposed between the first stacked structure and the lower die The first cavity is surrounded by the first outer layer, the first stack structure and the lower die. The semiconductor device according to claim 13, further comprising a first lower annular layer and a first upper annular layer; wherein the first lower annular layer is disposed between the first outer layer and the lower die , and the first upper annular layer is disposed between the first outer layer and the first stacked structure; wherein the first chamber is composed of the first outer layer, the first upper annular layer, the first lower Surrounded by an annular layer, the first stacked structure and the lower grain. The semiconductor device of claim 14, wherein a thickness of the first controller die is substantially the same as a thickness of the second controller die. The semiconductor device of claim 15, wherein a thickness of the first stacked structure is substantially the same as a thickness of the second stacked structure. The semiconductor device of claim 16, wherein the number of the first storage dies is greater than the number of the second storage dies. The semiconductor device of claim 17, further comprising a first through-die via and a second through-die via, the first through-die via being disposed along one of the first storage dies, and Electrically connected to the first controller die, the second through-die via is along at least two The first storage die is disposed on the first controller die and is electrically connected to the first controller die. The semiconductor device of claim 18, wherein a width of the second through-die via is greater than a width of the first through-die via. The semiconductor device of claim 19, wherein the number of the plurality of first interconnected units is less than the number of the plurality of second interconnected units. A method of manufacturing a semiconductor element, including: providing a first stacked structure, the first stacked structure including: a first controller die; and a plurality of first storage die, sequentially stacked on the first controller die. on the die; provide a second stacked structure, the second stacked structure includes: a second controller die; and a plurality of second storage dies, sequentially stacked on the second controller die; the first The controller die is bonded to the lower die via a plurality of first interconnect units; and the second controller die is bonded to the lower die via a plurality of second interconnect units; wherein the plurality of first interconnect units A storage die includes a plurality of first storage units, which are configured into a floating array; wherein the plurality of second storage dies includes a plurality of second storage units, which respectively include Includes an insulator-conductor-insulator structure. The method of manufacturing a semiconductor device according to claim 21, further comprising forming an underfill layer between the first controller die and the lower die and surrounding the plurality of first interconnect units. The method of manufacturing a semiconductor device according to claim 22, further comprising: bonding the lower die to a substrate through a plurality of third interconnect units. The method of manufacturing a semiconductor device as claimed in claim 23, wherein the lowest one of the plurality of first storage dies is stacked on the first controller die in a face-to-face configuration. A method of manufacturing a semiconductor element, including: providing a lower die; forming a first stack structure on the lower die via a plurality of first interconnect units; and forming a second stack structure via a plurality of second interconnect units. A structure is formed on the lower die; wherein the first stacked structure includes: a first controller die formed on the plurality of first interconnect units; and a plurality of first storage dies stacked on the first interconnect unit. on a controller die and configured into a floating array; The second stacked structure includes: a second controller die formed on the plurality of second interconnect units; and a plurality of second storage dies stacked on the second controller die, and respectively Includes an insulator-conductor-insulator structure. The method of manufacturing a semiconductor device according to claim 25, wherein the plurality of first interconnection units respectively include a first outer layer and a first cavity, the first outer layer is disposed between the first stacked structure and the first cavity. between the lower dies, and the first cavity is surrounded by the first outer layer, the first stack structure and the lower dies. The method for manufacturing a semiconductor device according to claim 26, further comprising forming a first lower annular layer and a first upper annular layer; wherein the first lower annular layer is disposed between the first outer layer and the lower between the die, and the first upper annular layer is disposed between the first outer layer and the first stacked structure; wherein the first chamber is composed of the first outer layer, the first upper annular layer, Surrounded by the first lower annular layer, the first stacked structure and the lower die. The method of manufacturing a semiconductor device as claimed in claim 27, wherein a thickness of the first controller die is substantially the same as a thickness of the second controller die. The method of manufacturing a semiconductor device as claimed in claim 28, wherein a thickness of the first stacked structure is substantially the same as a thickness of the second stacked structure. The method of manufacturing a semiconductor device as claimed in claim 29, wherein the number of the plurality of first storage dies is greater than the number of the plurality of second storage dies. The method of manufacturing a semiconductor device according to claim 30, further comprising forming a first through-die via, which is arranged along one of the first storage dies, is arranged on the first controller die, and is electrically connected to the first controller die. The method of manufacturing a semiconductor device according to claim 31, further comprising forming a second through-die via, which is arranged along at least two first storage dies, is arranged on the first controller die and electrically electrically connected to the first controller die. The method of manufacturing a semiconductor device according to claim 32, wherein a width of the second through-die via hole is greater than a width of the first through-die via hole. The method of manufacturing a semiconductor device as claimed in claim 33, wherein the number of the plurality of first interconnected units is less than the number of the plurality of second interconnected units. The method of manufacturing a semiconductor device according to claim 34, further comprising forming an underfill layer between the first controller die and the lower die and surrounding the plurality of first interconnect units.