CN110400787B - Silicon-based vertical interconnection structure and preparation method - Google Patents
Silicon-based vertical interconnection structure and preparation method Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
The invention discloses a silicon-based vertical interconnection structure and a preparation method thereof, wherein the silicon-based vertical interconnection structure comprises a large-thickness substrate formed by two monocrystalline silicon wafers, a metal bonding layer is arranged between the two monocrystalline silicon wafers, and inverted pyramid-shaped pits which are symmetrical up and down are arranged on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer; the upper surface and the lower surface of the large-thickness substrate and the metal bonding layer between the monocrystalline silicon wafers are provided with metal wiring, and the vertical interconnection of electrical signals on the upper surface and the lower surface of the large-thickness substrate is realized through the side walls of the inverted pyramid-shaped pits on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer; the invention prepares the large-thickness silicon-based vertical interconnection structure by utilizing the processes of intermetallic bonding, anisotropic corrosion of monocrystalline silicon, film deposition and the like, has the characteristics of batch, low cost, easy realization and the like, and can realize the vertical interconnection of the large-thickness silicon substrate.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a silicon-based vertical interconnection structure and a preparation method thereof.
Background
With the development of advanced packaging technology, the system-in-package technology has the advantages of miniaturization and high integration, so that the system-in-package technology is widely applied to various fields of consumer electronics, automobile electronics, industrial electronics, military electronics and the like. As the most mainstream semiconductor material in the microelectronic process, monocrystalline silicon has been gradually developed as one of the most promising substrate materials in the system-in-package technology due to its numerous advantages such as high manufacturing accuracy, low cost, mass production, easy integration, etc. Therefore, the research of the vertical interconnection structure in the monocrystalline silicon substrate has important significance for the structure, the electrical performance and the process design of the future silicon-based three-dimensional packaging micro-system.
Conventional vertical interconnects for through-silicon vias are metal filled hollow or solid cylindrical vias. Such a cylindrical through-silicon via structure is generally required to be manufactured by a plasma deep silicon etching process (abbreviated as DRIE process) and a metal plating process in sequence. From a technical perspective, the current DRIE process can already etch silicon deep holes with a depth of hundreds of micrometers, but the subsequent process of electroplating metal to fill deep holes still cannot realize metal filling with a depth of hundreds of micrometers. The main reason is that the electroplating of the vertical deep hole is extremely easy to generate pinch-off effect at the orifice, so that the inside of the metal column is defective. This also greatly limits the depth of the metallized through silicon vias and thus the thickness of the final silicon substrate. According to the current domestic micro-nano processing technology level, the maximum thickness of the silicon substrate with the vertical interconnection structure can be only 200-300 microns. The thickness of the silicon substrate is too thin, so that the structural reliability is very low, and the silicon substrate with larger size cannot be manufactured on the premise of ensuring the structural rigidity, so that the larger-scale system-in-package cannot be realized; on the other hand, it makes it difficult to embed multiple chips in a silicon substrate. From a cost perspective, the DRIE deep silicon etching process is costly and can only etch one wafer at a time, and the productivity cannot be increased, so that the cost of the silicon substrate cannot be further compressed with the increase of the production quantity. To sum up, it is currently difficult to implement large-scale applications of conventional cylindrical through silicon via vertical interconnect structures in the field of system-in-package.
In view of the above drawbacks, the present inventors have finally achieved the present invention through long-time studies and practices.
Disclosure of Invention
In order to solve the technical defects, the technical scheme adopted by the invention is that the silicon-based vertical interconnection structure comprises a large-thickness substrate formed by two monocrystalline silicon wafers, wherein a metal bonding layer is arranged between the two monocrystalline silicon wafers, and inverted pyramid-shaped pits which are symmetrical up and down are arranged on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer; and the upper surface and the lower surface of the large-thickness substrate and the metal bonding layer between the monocrystalline silicon wafers are respectively provided with metal wiring, and the vertical interconnection of the electrical signals on the upper surface and the lower surface of the large-thickness substrate is realized through the side walls of the inverted pyramid-shaped pits on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer.
Preferably, the upper and lower surfaces of the two monocrystalline silicon wafers and all side walls in the inverted pyramid-shaped pits are covered with insulating layers, and the insulating layers are arranged between the metal wiring and the substrate.
Preferably, the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer both contain five inverted pyramid pits, and are correspondingly arranged one by one; the inverted pyramid pits are arranged at the central positions of the other four inverted pyramid pits, the inverted pyramid pits at the center are used for transmitting radio frequency signals, and the four inverted pyramid pits at the periphery are all grounding signals; the bonding metal layer is divided into a central bonding pad and peripheral metal, the central bonding pad is connected with the metal films of the inverted pyramid pits located on the upper side and the lower side of the center, and the peripheral metal is connected with the metal films of the inverted pyramid pits on the upper side and the lower side of the periphery.
Preferably, the preparation method of the silicon-based vertical interconnection structure comprises the following steps:
s1, preparing a first monocrystalline silicon wafer;
s2, depositing a first insulating layer on the lower surface of the first monocrystalline silicon wafer;
s3, depositing a bonding film on the lower surface of the first monocrystalline silicon wafer, and carrying out graphical treatment on the bonding film so as to form a metal pattern on the lower surface of the first monocrystalline silicon wafer;
s4, repeating the steps S1 to S3 to form the second monocrystalline silicon wafer with the bonding film on the surface, bonding the first monocrystalline silicon wafer and the second monocrystalline silicon wafer, and forming the large-thickness silicon substrate with the metal bonding layer in the middle;
s5, forming an etching mask on the upper surface of the first monocrystalline silicon wafer, and anisotropically etching the first monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s6, depositing a second insulating layer on the upper surface of the first monocrystalline silicon wafer and the inner wall of the inverted pyramid pit;
s7, forming an etching mask by utilizing a photoetching process, and removing the second insulating layer at the bottom of the inverted pyramid pit on the first monocrystalline silicon wafer;
s8, depositing a metal film on the upper surface of the first monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and performing graphical treatment on the metal film so as to form metal wiring on the upper surface of the first monocrystalline silicon wafer and in the inverted pyramid pit;
and S9, repeating the steps S5-S8 for the second monocrystalline silicon wafer, so as to form inverted pyramid pits and metal wiring of the second monocrystalline silicon wafer, and finally forming the large-thickness silicon-based vertical interconnection structure.
Preferably, the wafer thickness of the first single crystal silicon wafer and the second single crystal silicon wafer is set to be 0.1 mm-1 mm.
Preferably, the included angles between the four inner side surfaces of the inverted pyramid-shaped concave pit and the horizontal plane are 54.74 degrees.
Preferably, the first monocrystalline silicon wafer and the second monocrystalline silicon wafer are subjected to deep silicon corrosion by utilizing a wet anisotropic corrosion process, so that the inverted pyramid-shaped pits are formed.
Preferably, the patterning of the metal film and the bonding film adopts photoetching patterning and film etching processes.
Preferably, the preparation method of the silicon-based vertical interconnection structure comprises the following steps:
s1, preparing a first monocrystalline silicon wafer;
s2, depositing a bonding film on the lower surface of the first monocrystalline silicon wafer, and carrying out graphical treatment on the bonding film so as to form a metal pattern on the lower surface of the first monocrystalline silicon wafer;
s3, repeating the steps S1-S2 to form the second monocrystalline silicon wafer with the bonding film on the surface, bonding the first monocrystalline silicon wafer and the second monocrystalline silicon wafer, and forming the large-thickness silicon substrate with the metal bonding layer in the middle;
s4, forming an etching mask on the upper surface of the first monocrystalline silicon wafer, and performing anisotropic etching on the first monocrystalline silicon wafer to form an inverted pyramid-shaped pit;
s5, depositing a metal film on the upper surface of the first monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and performing graphical treatment on the metal film so as to form metal wiring on the upper surface of the first monocrystalline silicon wafer and in the inverted pyramid pit;
and S6, repeating the steps S4-S5 for the second monocrystalline silicon wafer, so as to form inverted pyramid pits and metal wiring of the second monocrystalline silicon wafer, and finally forming the large-thickness silicon-based vertical interconnection structure.
Preferably, the resistivity of the first single crystal silicon wafer and the second single crystal silicon wafer is higher than 1000Ω·cm.
Compared with the prior art, the invention has the beneficial effects that: the invention prepares the large-thickness silicon-based vertical interconnection structure by utilizing processes such as intermetallic bonding, anisotropic corrosion of monocrystalline silicon, film deposition and the like, has the characteristics of batch, low cost, easy realization and the like, can realize vertical interconnection of large-thickness (more than 600 um) silicon substrates, overcomes the defect that the traditional cylindrical silicon through hole is only suitable for the thin silicon substrate (the thickness is less than 300 um), and has wide application prospect in silicon-based system level packaging.
Drawings
FIG. 1 is a cross-sectional view of a silicon-based vertical interconnect structure in accordance with the present invention;
FIG. 2 is a three-dimensional view of a silicon-based vertical interconnect structure according to the present invention;
FIG. 3 is a flow chart of a process for fabricating a silicon-based vertical interconnect structure according to the present invention;
FIG. 4 is a top view of the silicon-based vertical interconnect structure for radio frequency signal transmission;
FIG. 5 is a cross-sectional view of the RF signal transmission structure shown in FIG. 4 taken along line A-A';
fig. 6 is a graph of S-parameters of the vertical interconnect structure of the present invention for transmission of radio frequency signals in the frequency range of OGHz to 20 GHz.
The figures represent the numbers:
101-monocrystalline silicon wafer; 102-inverted pyramid-shaped pits; 103-an insulating layer; 104-metal wiring.
Detailed Description
The above and further technical features and advantages of the present invention are described in more detail below with reference to the accompanying drawings.
Example 1
As shown in fig. 1 and 2, fig. 1 is a cross-sectional view of a silicon-based vertical interconnect structure according to the present invention, and fig. 2 is a three-dimensional view of the silicon-based vertical interconnect structure according to the present invention; the silicon-based vertical interconnection structure comprises a large-thickness substrate formed by bonding two monocrystalline silicon wafers 101 through metal, wherein a metal bonding layer is arranged between the two monocrystalline silicon wafers 101, and the upper monocrystalline silicon wafer 101 and the lower monocrystalline silicon wafer 101 respectively form inverted pyramid-shaped pits 102 which are symmetrical up and down by utilizing a wet anisotropic etching process. The metal wiring 104 is disposed on the upper and lower surfaces of the large-thickness substrate and the metal bonding layer between the monocrystalline silicon wafers 101, and the metal wiring 104 realizes vertical interconnection of electrical signals on the upper and lower surfaces of the large-thickness substrate through the side walls of the inverted pyramid-shaped pits 102 of the monocrystalline silicon wafers 101, thereby forming a vertical interconnection structure of the large-thickness substrate.
Preferably, the upper and lower surfaces of the two monocrystalline silicon wafers 101 and all the side walls in the inverted pyramid-shaped pits 102 are covered with an insulating layer 103, so as to isolate the electrical signals from the monocrystalline silicon wafers 101. The insulating layer 103 may be omitted if the resistivity of the single crystal silicon wafer 101 is higher than 1000Ω·cm.
All details of the silicon-based vertical interconnect structure are more clearly shown in fig. 2. The silicon-based vertical interconnection structure comprises the monocrystalline silicon wafer 101 divided into an upper layer and a lower layer, the metal wiring 104 on the upper surface and the lower surface of the large-thickness substrate, the metal bonding layer with a certain pattern and the inverted pyramid pit 102 in the monocrystalline silicon wafer 101.
Example two
As shown in fig. 3, fig. 3 is a process flow chart of preparing a silicon-based vertical interconnection structure according to the present invention, and the preparation method of the silicon-based vertical interconnection structure according to the present invention specifically includes the following steps:
s1, preparing a first monocrystalline silicon wafer, wherein the wafer thickness of the first monocrystalline silicon wafer can be set to any value within the range of 0.1 mm-1 mm;
s2, depositing a first insulating layer on the lower surface of the first monocrystalline silicon wafer by using a film deposition process, wherein if the resistivity of the first monocrystalline silicon wafer is not less than 1000 Ω & cm, the first insulating layer can be omitted;
s3, depositing a bonding film on the lower surface of the first monocrystalline silicon wafer by utilizing a metal film deposition process, and then utilizing photoetching patterning and a metal film etching process to realize patterning of the bonding film so as to form a metal pattern on the lower surface of the first monocrystalline silicon wafer;
s4, repeating the steps S1-S3 to form the second monocrystalline silicon wafer with the bonding film on the surface, and bonding the bonding film on the first monocrystalline silicon wafer and the second monocrystalline silicon wafer by utilizing an intermetallic bonding process, so as to form the large-thickness silicon substrate with the metal bonding layer in the middle;
s5, forming an etching mask on the upper surface of the first monocrystalline silicon wafer by utilizing a photoetching patterning process, and then anisotropically etching the first monocrystalline silicon wafer by utilizing a wet etching process to form inverted pyramid-shaped pits; the etching solution in the anisotropic etching can be TMAH, KOH or other solutions capable of carrying out anisotropic etching on the monocrystalline silicon material;
s6, depositing a second insulating layer on the upper surface of the first monocrystalline silicon wafer and the inner wall of the inverted pyramid pit by using a thin film deposition process so as to realize electrical isolation between the subsequent metal wiring and the first monocrystalline silicon wafer;
s7, forming an etching mask by utilizing photoetching patterning technology, and then removing the second insulating layer at the bottom of the inverted pyramid pit on the first monocrystalline silicon wafer by utilizing a thin film etching technology;
s8, depositing a metal film on the upper surface of the first monocrystalline silicon wafer and the side wall of the inverted pyramid pit by using a metal film deposition process, and then realizing patterning of the metal film by using photoetching patterning and a metal film etching process so as to form metal wiring on the upper surface of the first monocrystalline silicon wafer and in the inverted pyramid pit;
and S9, repeating the steps S5-S8 for the second monocrystalline silicon wafer, so as to form inverted pyramid pits and metal wiring of the second monocrystalline silicon wafer, and finally forming the large-thickness silicon-based vertical interconnection structure.
The first insulating layer and the second insulating layer can be any material with insulating function such as silicon dioxide, silicon nitride, organic matters and the like; the specific deposition process can be any process such as chemical vapor deposition, physical sputtering, spin coating glue and the like.
The specific deposition process of the bonding film and the metal film can be any deposition process such as electroplating, chemical plating, evaporation deposition, physical sputtering and the like; the specific patterning process can be any patterning process such as plasma reaction etching, ion beam etching, physical etching, laser etching and the like.
The two monocrystalline silicon wafers are bonded by utilizing a metal bonding process to form a silicon substrate with large thickness, wherein the metal bonding process can be hot-press bonding and eutectic bonding between metal films or mixed bonding between metal and nonmetal films.
The invention utilizes wafer-level intermetallic bonding technology to bond two monocrystalline silicon wafers together; then, carrying out deep silicon etching on the upper and lower monocrystalline silicon wafers respectively by utilizing a wet anisotropic etching process, and stopping etching pits on the metal bonding layer; and then depositing metal films on the surfaces of the upper and lower monocrystalline silicon wafers and the side walls of the pits by utilizing an electroplating process, and finally forming the dumbbell-shaped vertical interconnection structure which is symmetrical up and down.
The invention bonds two single crystal silicon wafers together by using an intermetallic bonding process, thereby realizing a silicon substrate structure with a metal layer in the middle and a large thickness. The metal bonding layer can be used as a self-stopping layer for subsequent deep silicon wet etching in the process, so that the structure obtained by etching is highly controllable. Meanwhile, the metal bonding layer is connected with the metal films in the inverted pyramid pits, so that the electrical interconnection of the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer is realized.
The invention uses a monocrystalline silicon wet anisotropic etching process to carry out deep silicon etching on the monocrystalline silicon wafers. The four inner side surfaces of the inverted pyramid pit formed by corrosion form angles of 54.74 degrees with the horizontal plane, but not 90 degrees formed by the inner wall of the traditional cylindrical silicon through hole and the horizontal plane, so that the pit opening is open, and the exposed area of the side wall is large. The subsequent metal plating process is therefore prone to depositing a metal film on all sidewalls and bottom of the inverted pyramidal pits without pinch-off effects resulting in defects. This greatly reduces the process difficulty of metal plating.
The invention uses the monocrystalline silicon wet anisotropic etching process to carry out deep silicon etching on the upper and lower monocrystalline silicon wafers and automatically stops at the metal bonding layer between the two monocrystalline silicon wafers, and the subsequent metal electroplating process does not increase the process difficulty along with the increase of the depth of the etching pit. Thus, the thickness of the entire through-silicon via vertical interconnect (i.e., the silicon substrate thickness) is the sum of the thicknesses of the two single crystal silicon wafers. With this structure and process, a silicon substrate with a vertical interconnect structure having a large thickness (a thickness of 600 μm or more) can be easily manufactured.
Compared with the DRIE plasma dry etching process adopted by the conventional through silicon via, the single crystal silicon wet anisotropic etching process adopted by the invention has lower manufacturing cost and can simultaneously etch and process a large number of wafers. Therefore, the process of the invention reduces the cost of the through silicon via vertical interconnection structure and improves the production efficiency.
The invention prepares the large-thickness silicon-based vertical interconnection structure by utilizing the processes of intermetallic bonding, anisotropic corrosion of monocrystalline silicon, film deposition and the like, and has the characteristics of batch, low cost, easy realization and the like, so that the cost of the large-thickness silicon-based vertical interconnection structure is lower than that of the traditional cylindrical silicon through hole vertical interconnection structure. On the other hand, the anisotropic wet etching of monocrystalline silicon has no limit on the thickness of wafers, and the silicon substrate is formed by bonding two wafers, so that the vertical interconnection of the silicon substrate with large thickness (more than 600 um) is realized, the defect that the traditional cylindrical silicon through hole is only suitable for a thin silicon substrate (with the thickness less than 300 um) is overcome, and the silicon substrate has wide application prospect in silicon-based system level packaging.
Example III
The silicon-based vertical interconnection structure can be applied to the vertical transition transmission of direct-current optical signals and radio-frequency signals within a certain frequency range in a silicon-based three-dimensional system-in-package structure.
As shown in fig. 4, the silicon-based vertical interconnect structure of fig. 4 for rf signal transmission is shown. In fig. 4, the gray areas are covered with a patterned metal film, specifically, the metal film includes a first metal area 105 and a second metal area 106, and the first metal area 105 and the second metal area 106 are not connected; the first metal region 105 is used for transmitting radio frequency signals, and the vertical interconnection between the vertical symmetrical inverted pyramid-shaped through holes arranged on the first metal region 105 and the radio frequency signal transmission line on the lower end face of the large-thickness silicon substrate is realized. The second metal region 106 is used for grounding to realize the shielding and impedance matching functions of the radio frequency signal. In this embodiment, the four vertically symmetrical inverted pyramid-shaped through holes provided on the second metal region 106 are vertically interconnected with the ground metal on the lower end surface of the substrate, and the vertical interconnection through holes on the second metal region 106 are annularly provided on the periphery of the vertical interconnection through holes on the first metal region 105.
As shown in fig. 5, fig. 5 is a cross-sectional view of the radio frequency signal transmission structure shown in fig. 4 taken along A-A'. In fig. 5, the metal lead on the upper end surface is vertically interconnected with the radio frequency signal on the lower end surface of the substrate through the vertically symmetrical inverted pyramid-shaped through hole on the first metal region 105; the grounding metal of the upper end face is vertically interconnected with the grounding metal of the lower end face of the substrate through the vertically symmetrical inverted pyramid-shaped through holes on the second metal region 106; the whole vertical transmission structure of the radio frequency signal can be prepared by the process flow shown in fig. 3.
As shown in fig. 6, fig. 6 is an S-parameter graph of the vertical interconnection structure for radio frequency signal transmission in the frequency range of 0GHz to 20GHz according to the present invention, where the graph in fig. 6 is simulated by finite element electromagnetic simulation software HFSS. The result of the curve shows that when the frequency of the radio frequency signal is lower than 12GHz, the insertion loss (S21) is smaller than 0.15dB, and the return loss (S11) is larger than 24dB. And when the frequency is higher than 12GHz, the corresponding S parameter index starts to deteriorate. Therefore, the vertical interconnection structure of the invention has good radio frequency transmission characteristics in the 12GHz range.
The foregoing description of the preferred embodiment of the invention is merely illustrative of the invention and is not intended to be limiting. It will be appreciated by persons skilled in the art that many variations, modifications, and even equivalents may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. The silicon-based vertical interconnection structure is characterized by comprising a large-thickness substrate formed by two monocrystalline silicon wafers, wherein a metal bonding layer is arranged between the two monocrystalline silicon wafers, and inverted pyramid-shaped pits which are symmetrical up and down are arranged on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer; the upper surface and the lower surface of the large-thickness substrate and the metal bonding layer between the monocrystalline silicon wafers are provided with metal wiring, and the vertical interconnection of electrical signals on the upper surface and the lower surface of the large-thickness substrate is realized through the side walls of the inverted pyramid-shaped pits on the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer; the upper monocrystalline silicon wafer and the lower monocrystalline silicon wafer both contain five inverted pyramid pits and are correspondingly arranged one by one; the inverted pyramid pits are arranged at the central positions of the other four inverted pyramid pits, the inverted pyramid pits at the center are used for transmitting radio frequency signals, and the four inverted pyramid pits at the periphery are all grounding signals; the bonding metal layer is divided into a central bonding pad and peripheral metal, the central bonding pad is connected with the metal films of the inverted pyramid pits located on the upper side and the lower side of the center, and the peripheral metal is connected with the metal films of the inverted pyramid pits on the upper side and the lower side of the periphery.
2. The silicon-based vertical interconnect structure of claim 1 wherein both upper and lower surfaces of two single crystal silicon wafers and all sidewalls within the inverted pyramid-shaped recess are covered with an insulating layer disposed between the metal wiring and the substrate.
3. A method of fabricating a silicon-based vertical interconnect structure as defined in claim 2 comprising the steps of:
s1, preparing a first monocrystalline silicon wafer;
s2, depositing a first insulating layer on the lower surface of the first monocrystalline silicon wafer;
s3, depositing a bonding film on the lower surface of the first monocrystalline silicon wafer, and carrying out graphical treatment on the bonding film so as to form a metal pattern on the lower surface of the first monocrystalline silicon wafer;
s4, repeating the steps S1 to S3 to form the second monocrystalline silicon wafer with the bonding film on the surface, bonding the first monocrystalline silicon wafer and the second monocrystalline silicon wafer, and forming the large-thickness silicon substrate with the metal bonding layer in the middle;
s5, forming an etching mask on the upper surface of the first monocrystalline silicon wafer, and anisotropically etching the first monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s6, depositing a second insulating layer on the upper surface of the first monocrystalline silicon wafer and the inner wall of the inverted pyramid pit;
s7, forming an etching mask by utilizing a photoetching process, and removing the second insulating layer at the bottom of the inverted pyramid pit on the first monocrystalline silicon wafer;
s8, depositing a metal film on the upper surface of the first monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and performing graphical treatment on the metal film so as to form metal wiring on the upper surface of the first monocrystalline silicon wafer and in the inverted pyramid pit;
and S9, repeating the steps S5-S8 for the second monocrystalline silicon wafer, so as to form inverted pyramid pits and metal wiring of the second monocrystalline silicon wafer, and finally forming the large-thickness silicon-based vertical interconnection structure.
4. The method of manufacturing according to claim 3, wherein the wafer thickness of the first single crystal silicon wafer and the second single crystal silicon wafer is set to 0.1mm to 1mm.
5. A method of manufacturing as claimed in claim 3, wherein the four inner sides of the inverted pyramidal pits are at an angle of 54.74 ° to the horizontal.
6. The method of manufacturing as claimed in claim 3, wherein the first single crystal silicon wafer and the second single crystal silicon wafer are subjected to deep silicon etching using a wet anisotropic etching process to form the inverted pyramid-shaped pits.
7. The method of claim 3, wherein patterning of the metal film and the bonding film is performed by photolithographic patterning and film etching.
8. A method of fabricating a silicon-based vertical interconnect structure as defined in claim 1 comprising the steps of:
s2, depositing a bonding film on the lower surface of the first monocrystalline silicon wafer, and carrying out graphical treatment on the bonding film so as to form a metal pattern on the lower surface of the first monocrystalline silicon wafer;
s3, repeating the steps S1-S2 to form the second monocrystalline silicon wafer with the bonding film on the surface, bonding the first monocrystalline silicon wafer and the second monocrystalline silicon wafer, and forming the large-thickness silicon substrate with the metal bonding layer in the middle;
s4, forming an etching mask on the upper surface of the first monocrystalline silicon wafer, and performing anisotropic etching on the first monocrystalline silicon wafer to form an inverted pyramid-shaped pit;
s5, depositing a metal film on the upper surface of the first monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and performing graphical treatment on the metal film so as to form metal wiring on the upper surface of the first monocrystalline silicon wafer and in the inverted pyramid pit;
and S6, repeating the steps S4-S5 for the second monocrystalline silicon wafer, so as to form inverted pyramid pits and metal wiring of the second monocrystalline silicon wafer, and finally forming the large-thickness silicon-based vertical interconnection structure.
9. The method of manufacturing according to claim 8, wherein the resistivity of the first single crystal silicon wafer and the second single crystal silicon wafer is higher than 1000 Ω -cm.
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