CN103887231B - Self-alignment technology for leak holes and dielectric layer on back of TSV and TSV - Google Patents

Self-alignment technology for leak holes and dielectric layer on back of TSV and TSV Download PDF

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Publication number
CN103887231B
CN103887231B CN201410131113.5A CN201410131113A CN103887231B CN 103887231 B CN103887231 B CN 103887231B CN 201410131113 A CN201410131113 A CN 201410131113A CN 103887231 B CN103887231 B CN 103887231B
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tsv
substrate
back side
dielectric layer
layer
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CN103887231A (en
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薛恺
张文奇
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

The invention provides a self-alignment technology for leak holes and a dielectric layer on the back of a TSV and the TSV. The self-alignment technology comprises the following steps that a substrate with TSV blind hole structure manufacturing finished is provided; back thinning is carried out on the substrate, and the etching technology is used for enabling the back end of the TSV to protrude out of the surface of the back of the substrate; the back face of the substrate is coated by the back dielectric layer which covers the back face of the substrate and the TSV back end protruding out of the back surface of the substrate; the CMP technology is used for carrying out flattening processing on the back dielectric layer, and the TSV is made to be exposed; the etching technology is used for processing the exposed TSV, and steps of the TSV and the back dielectric layer are formed; an adhesion layer and a seed layer are deposited on the back face of the substrate; the steps of the TSV and the back dielectric layer are used for carrying out photoetching alignment on micro salient points or RDL, and the technology of manufacturing the micro salient points or the RDL is completed. The self-alignment technology can prevent metal from polluting the silicon substrate, and photoetching precision when the micro salient points or the RDL is manufactured is guaranteed.

Description

Self-registered technology for TSV back side small opening and dielectric layer and TSV
Technical field
The present invention relates to microelectronic packaging process, especially a kind of for TSV back side small opening and dielectric layer and TSV from right Quasi- technique.
Background technology
In microelectronics Packaging, need simple, reliable TSV back side Joining Technology method.And the existing TSV back side Interconnection technique generally adopt following methods：
1. pair complete TSV blind hole structure substrate back be ground thinning.
2. carry out CMP in substrate back（Chemically mechanical polishing）Technique is until TSV small opening, but Si and TSV of now substrate Cu（Copper）Expose simultaneously, the contamination to silicon substrate for the metal may be led to.
3. make dielectric layer in substrate back.
4. make back side dielectric layer graphical using double-sided alignment technique, that is, the alignment mark first with substrate face carry out right Standard, carries out photoetching to the dielectric layer of substrate back, forms medium layer pattern（Lithographic accuracy can affect the position of back side medium layer pattern Put precision）；Then complete RDL technique using back side medium layer pattern as the alignment mark of back side RDL.
Used in the method, double-sided alignment technique alignment precision is poor, and it is reasonable smooth to require wafer rear to have Degree, is only applicable to be carried out the technique of TSV small opening using CMP, may lead to the contamination to silicon substrate for the metal.
Content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, provides one kind to be used for TSV back side small opening and medium Layer and the self-registered technology of TSV, the photoetching one side Alignment Process of achievable RDL and salient point；On the one hand metal can be avoided to silicon The contamination of substrate, still further aspect back side RDL adopts one side Alignment Process it is ensured that making photoetching when micro convex point or RDL Precision.The technical solution used in the present invention is：
Step one, provides the substrate having completed the manufacture of TSV blind hole structure；
Step 2, carries out thinning back side to the substrate containing TSV blind hole structure；
Step 3, using the high selectivity etching technics etched substrate back side so that TSV the back end head process is for substrate back Surface；
Step 4, coats one layer of back side dielectric layer in substrate back, covers substrate back and prominent substrate back surfaces TSV back side termination；
Step 5, carries out planarization process using CMP and so that TSV is exposed to back side dielectric layer；
Step 6, processes, using etching technics, the TSV exposing, and forms the step of TSV and back side dielectric layer；
Step 7, deposits adhesion layer and Seed Layer in substrate back；
Step 8, carries out micro convex point or RDL lithography alignment using the step of TSV and dielectric layer, complete make micro convex point or RDL technique.
Further, in step one, around TSV blind hole, it is provided with TSV insulating barrier.
Further, in step 3, the method for etching adopts wet-etching technology.
Further, the material of back side dielectric layer includes one of polymeric material, silicon dioxide, silicon nitride or many Kind.
Further, in step 7, adhesion layer and Seed Layer are deposited using PVD physical gas-phase deposition.
Further, the material of adhesion layer is titanium.The material of Seed Layer is copper.
It is an advantage of the current invention that：Back side dielectric layer, using adopting self-registered technology, does not have lithographic accuracy deficiency to lead to Error；The TSV back side small opening technique of no metal contamination can be realized；Can reduce by a step photoetching process, process costs are relatively low；The back side RDL adopts one side Alignment Process it is ensured that making micro convex point or lithographic accuracy during RDL.
Brief description
Fig. 1 is the substrate schematic diagram of the present invention.
Fig. 2 is the substrate thinning schematic diagram of the present invention.
Fig. 3 is that the silicon of the etching wafer rear of the present invention exposes TSV back side termination schematic diagram.
Fig. 4 is the making back side dielectric layer schematic diagram of the present invention.
Fig. 5 is that the planarized back of the present invention processes schematic diagram.
Fig. 6 is the formation step schematic diagram of the present invention.
Fig. 7 is deposit adhesion layer and the Seed Layer schematic diagram of the present invention.
Fig. 8 is that the back side of the present invention is directed at and is completed micro convex point or RDL process schematic representation.
Fig. 9 is the flow chart of the present invention.
Specific embodiment
With reference to concrete drawings and Examples, the invention will be further described.
Self-registered technology for TSV back side small opening and dielectric layer and TSV proposed by the invention, comprises the steps：
Step one, provides the substrate 1 having completed the manufacture of TSV blind hole structure, as shown in figure 1, TSV blind hole week in substrate 1 Enclose and be provided with TSV insulating barrier 2, in TSV blind hole, be filled with TSV filling conductor 3；The material that TSV fills conductor 3 is typically copper.
Step 2, as shown in Fig. 2 carry out thinning back side to the substrate 1 containing TSV blind hole structure；
Step 3, as shown in figure 3, using high selectivity etching technics etched substrate 1 back side so that TSV the back end head process For substrate 1 back surfaces；
Specifically substrate 1 back side silicon etching, such as wet-etching technology can be carried out using the method for etching；Because TSV is by TSV Insulating barrier 2 is protected, and therefore in etching process, TSV structure will not be damaged, and is also not in the feelings of metal contamination silicon substrate Condition.
Step 4, as shown in figure 4, in substrate one layer of back side dielectric layer 4 of 1 backside coating, cover substrate 1 back side and prominent lining The TSV back side termination of bottom 1 back surfaces；The material of back side dielectric layer 4 includes one or more of following material：Polymeric material Material, silicon dioxide, silicon nitride；
Step 5, as shown in figure 5, utilize CMP（Chemically mechanical polishing）Planarization process is carried out to back side dielectric layer 4 And so that TSV is exposed；In this step, because dielectric layer 4 has covered the back side of substrate 1 in advance, therefore in CMP, substrate 1 The back side will not produce the situation of metal contamination.TSV small opening in this step, completes the self-registered technology of dielectric layer and TSV.
Step 6, as shown in fig. 6, processing, using etching technics, the TSV exposing, forms the step of TSV and back side dielectric layer 4 5；Step 5 herein is in follow-up back side RDL（RDL：Wiring layer again）The effect of alignment mark can be played in technique.
Step 7, as shown in fig. 7, deposit adhesion layer and seed using PVD physical gas-phase deposition at substrate 1 back side Layer；For convenience, together with adhesion layer has been drawn in Seed Layer in Fig. 6, this two-layer, wherein, adhesion layer are represented with reference 6 Material be titanium, the material of Seed Layer is copper.
Step 8, as shown in figure 8, carrying out micro convex point 7 or RDL lithography alignment using the step 5 of TSV and dielectric layer, completes Make micro convex point or RDL technique.
It is micro convex point 7 shown in Fig. 8, though RDL is not drawn into, those skilled in the art are appreciated that the structure of RDL.Make micro- Need when salient point or RDL to carry out the techniques such as photoetching, plating, using existing common process, the application is no longer developed in details in Narration.And in this step, substrate back RDL adopts one side Alignment Process it is ensured that lithographic accuracy.
Technical term of the present embodiment：TSV：I.e. Through Silicon Vias, Chinese looks like for " by silicon Piece passage ", or referred to as silicon hole.

Claims (3)

1. a kind of self-registered technology for TSV back side small opening and dielectric layer and TSV is it is characterised in that comprise the steps：
Step one, provides the substrate (1) having completed the manufacture of TSV blind hole structure；
Step 2, carries out thinning back side to the substrate containing TSV blind hole structure (1)；
Step 3, using high selectivity etching technics etched substrate (1) back side so that TSV the back end head process is carried on the back for substrate (1) Portion surface；
Step 4, in one layer of back side dielectric layer (4) of substrate (1) backside coating, covers substrate (1) back side and prominent substrate (1) back of the body The TSV back side termination on portion surface；
Step 5, carries out planarization process using CMP to back side dielectric layer (4) and so that TSV is exposed；
Step 6, processes, using etching technics, the TSV exposing, and forms the step (5) of TSV and back side dielectric layer (4)；
Step 7, deposits adhesion layer and Seed Layer at substrate (1) back side；
Step 8, the step (5) using TSV and dielectric layer carries out micro convex point (7) or RDL lithography alignment, completes to make micro convex point Or RDL technique；
In step one, around TSV blind hole, it is provided with TSV insulating barrier (2)；
In step 3, the method for etching adopts wet-etching technology；
The material of back side dielectric layer (4) includes one or more of polymeric material, silicon dioxide, silicon nitride；
In step 7, deposit adhesion layer and Seed Layer using PVD physical gas-phase deposition.
2. be used for as claimed in claim 1 the self-registered technology of TSV back side small opening and dielectric layer and TSV it is characterised in that：Viscous The material of attached layer is titanium.
3. be used for as claimed in claim 1 the self-registered technology of TSV back side small opening and dielectric layer and TSV it is characterised in that：Kind The material of sublayer is copper.
CN201410131113.5A 2014-04-02 2014-04-02 Self-alignment technology for leak holes and dielectric layer on back of TSV and TSV Active CN103887231B (en)

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CN110858536A (en) * 2018-08-24 2020-03-03 中芯国际集成电路制造（天津）有限公司 Method for forming semiconductor device
CN109273403B (en) * 2018-09-27 2021-04-20 中国电子科技集团公司第五十四研究所 TSV hole filling method
CN109461699B (en) * 2018-10-22 2020-08-14 中国电子科技集团公司第三十八研究所 Coaxial TSV structure adapter plate and manufacturing method thereof
US11183443B2 (en) * 2019-06-13 2021-11-23 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same
CN111370375A (en) * 2020-03-23 2020-07-03 苏州晶方半导体科技股份有限公司 Packaging structure, semiconductor device and packaging method
CN111769097B (en) * 2020-06-18 2022-11-18 复旦大学 Silicon through hole structure for three-dimensional interconnection and manufacturing method thereof
CN113035829B (en) * 2021-03-04 2022-11-25 复旦大学 TSV passive adapter plate and manufacturing method thereof

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CN103426864A (en) * 2013-08-26 2013-12-04 华进半导体封装先导技术研发中心有限公司 TSV structure applicable to adapter board and preparation method of TSV structure

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