KR20050005961A - method for forming metal line in semiconductor device - Google Patents
method for forming metal line in semiconductor device Download PDFInfo
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- KR20050005961A KR20050005961A KR1020030045956A KR20030045956A KR20050005961A KR 20050005961 A KR20050005961 A KR 20050005961A KR 1020030045956 A KR1020030045956 A KR 1020030045956A KR 20030045956 A KR20030045956 A KR 20030045956A KR 20050005961 A KR20050005961 A KR 20050005961A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 62
- 239000002184 metal Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012790 adhesive layer Substances 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 7
- 238000005260 corrosion Methods 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000003628 erosive effect Effects 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 금속 다마신 공정에서 금속막과 옥사이드막 간의 연마선택비와 증착 특성으로 인해 발생되는 디싱(dishing) 현상 및 침식 현상을 방지할 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to prevent dishing and erosion caused by polishing selectivity and deposition characteristics between a metal film and an oxide film in a metal damascene process. A metal wiring formation method of a semiconductor device.
일반적으로, 반도체 기판과 금속배선 사이를 전기적으로 연결하기 위한 접속 통로로서 콘택홀을 형성하고 있으며, 이러한 콘택홀을 매립하기 위한 금속 배선의 재료로는 전도도가 높고, 경제성이 있는 알루미늄 또는 구리 등의 금속막 및 그의합금이 주로 이용되고 있다.In general, a contact hole is formed as a connection path for electrically connecting the semiconductor substrate and the metal wiring, and as a material of the metal wiring for filling the contact hole, aluminum or copper having high conductivity and economical efficiency Metal films and alloys thereof are mainly used.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 금속배선 형성 방법은, 도 1a에 도시된 바와 같이, 먼저 반도체기판(1) 상에 옥사이드 계열의 절연막(2)을 형성하고 나서, 상기 절연막(2) 상에 감광막을 도포하고 노광 및 현상하여 금속배선 형성영역(미도시)을 노출시키는 감광막 패턴(5)을 형성한다.In the method of forming a metal wiring of a semiconductor device according to the prior art, as shown in FIG. 1A, an oxide-based insulating film 2 is first formed on a semiconductor substrate 1, and then a photosensitive film is formed on the insulating film 2. It is applied, exposed and developed to form the photosensitive film pattern 5 which exposes a metal wiring formation area (not shown).
이어, 도 1b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하여 상기 절연막을 건식 식각하여 트렌치(trench)(T1)를 형성한다. 그런 다음, 감광막 패턴을 제거한다.Subsequently, as illustrated in FIG. 1B, a trench T1 is formed by dry etching the insulating layer using the photoresist pattern as a mask. Then, the photoresist pattern is removed.
이 후, 상기 결과물 상에 Ta/TaN막(3)을 차례로 형성한 다음, Ta/TaN막 (3)위에 트렌치(T1)를 매립시키는 금속배선 형성용 금속막(4)을 형성한다. 이때, 상기 금속막(4)으로 구리(Cu)를 이용한다. 한편, 상기 금속막(4)은 표면이 평탄치 않고 상기 트렌치와 대응된 부분이 움푹 패인 형상을 가지고 있다.After that, a Ta / TaN film 3 is sequentially formed on the resultant, and then a metal film 4 for forming metal wiring 4 is formed on the Ta / TaN film 3 to fill the trench T1. At this time, copper (Cu) is used as the metal film 4. On the other hand, the metal film 4 has a shape where the surface is not flat and the portion corresponding to the trench is recessed.
이 후, 도 1c에 도시된 바와 같이, 상기 Ta/TaN막이 노출되는 시점까지 금속막을 씨엠피(Chemical Mechnical Polishing)하여 트렌치(T1)를 매립시키는 금속 배선(4a)을 형성한다.Thereafter, as shown in FIG. 1C, the metal film is chemically polished to the point where the Ta / TaN film is exposed to form a metal wiring 4a for filling the trench T1.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도이다.Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
그러나, 종래의 기술에서는 금속막 씨엠피 공정 시, 금속배선 형성용 금속막과 옥사이드 계열의 절연막 간의 연마 선택비 및 증착 특성 차이로 인해, 트렌치와 대응된 부분에서, 도 2에 도시된 바와 같이, 금속막이 움푹 패이는 디싱 현상(A부분 참조)이 발생되며, 뿐만 아니라 Ta/TaN막이 침식(B부분)되어 하부의 절연막이 노출되는 문제점이 발생되었다.However, in the related art, in the metal film CMP process, due to the difference in polishing selectivity and deposition characteristics between the metal film for forming metal wiring and the oxide-based insulating film, the portion corresponding to the trench, as shown in FIG. 2, A dishing phenomenon in which the metal film is pitted (see section A) occurs, as well as a problem in that the Ta / TaN film is eroded (B section) to expose the lower insulating film.
따라서, 상기 문제점을 해소하고자, 본 발명은 디싱현상 및 침식 현상이 발생되는 지역에 연마 스토퍼 역할을 하는 옥사이드 계열의 절연막을 형성함으로써, 디상 현상 및 침식 현상을 방지할 수 있는 반도체 소자의 금속배선 형성 방법을 제공하기 위한 것이다.Accordingly, in order to solve the above problem, the present invention forms an oxide-based insulating film that acts as a polishing stopper in a region in which dishing and erosion occur, thereby forming metal wiring of a semiconductor device capable of preventing diphase and erosion. It is to provide a method.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the prior art.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도.Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도.3A to 3E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
상기 목적을 달성하고자, 본 발명에 따른 반도체 소자의 금속배선 형성 방법은 금속배선 형성영역이 정의된 반도체기판을 제공하는 단계와, 기판 상에 금속배선 형성영역을 노출시키는 트렌치를 가진 제 1절연막을 형성하는 단계와, 트렌치를 포함한 제 1절연막 상에 접착층 및 확산방지막을 차례로 형성하는 단계와, 결과물 전면에 금속막 및 제 2절연막을 차례로 형성하는 단계와, 제 2절연막을 선택 식각하여 트렌치와 대응된 부분에 잔류되는 제 2절연막 패턴을 형성하는 단계와, 확산방지막이 노출되는 시점까지 제 2절연막 패턴 및 금속막을 씨엠피하여 트렌치를 매립시키는 금속 배선을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate with a metal wiring forming region defined, and a first insulating film having a trench for exposing the metal wiring forming region on the substrate; Forming a layer; forming an adhesive layer and a diffusion barrier layer on the first insulating layer including the trench; forming a metal layer and a second insulating layer on the entire surface of the resultant; and selectively etching the second insulating layer to correspond to the trench. Forming a second insulating film pattern remaining in the portion, and forming a metal wiring to fill the trench by CMPing the second insulating film pattern and the metal film until the diffusion barrier is exposed.
상기 접착층으로는 Ta막을 이용하고, 상기 확산방지막으로는 TaN막을 이용한다.A Ta film is used as the adhesive layer, and a TaN film is used as the diffusion barrier.
상기 제 2절연막은 옥사이드막 및 질화막 중 어느 하나를 이용하며, 상기 제2절연막으로서 옥사이드막을 이용할 경우 500∼1000Å두께로 형성하고, 상기 제 2절연막으로서 질화막을 이용할 경우 300∼500Å두께로 형성한다.The second insulating film is formed of any one of an oxide film and a nitride film. The second insulating film is formed to have a thickness of 500 to 1000 kW when the oxide film is used as the second insulating film, and to 300 to 500 kW when the nitride film is used as the second insulating film.
(실시예)(Example)
도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도이다.3A to 3E are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 금속배선 형성 방법은, 도 3a에 도시된 바와 같이, 반도체기판(10) 상에 옥사이드 계열의 제 1절연막(11)을 형성하고 나서, 상기 제 1절연막(11) 위에 금속배선 형성영역(미도시)을 노출시키는 제 1감광막 패턴(15)을 형성한다.In the method of forming metal wirings of a semiconductor device according to the present invention, as shown in FIG. 3A, an oxide-based first insulating film 11 is formed on a semiconductor substrate 10, and then on the first insulating film 11. The first photosensitive film pattern 15 exposing the metal wiring forming region (not shown) is formed.
이어, 도 3b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하여 상기 제 1절연막을 식각하여 트렌치(T2)를 형성한다. 그런 다음, 제 1감광막 패턴을 제거한다.Next, as shown in FIG. 3B, the trench T2 is formed by etching the first insulating layer using the first photoresist pattern as a mask. Then, the first photoresist pattern is removed.
이 후, 상기 트렌치(T2)를 포함한 제 1절연막 전면에 Ta/TaN막(12)을 차례로 형성한다. 이때, 상기 Ta/TaN막(12)에 있어서, Ta막은 상기 제 1절연막과 이 후 형성될 금속막 간의 접착력이 좋지 못한 점을 해소하기 위한 것으로서, 제 1절연막과 금속막 사이에 개재되어 이들 간의 접착력을 향상시키기 위한 접착막 역할을 한다. 또한, TaN막은 이 후 형성될 금속막 성분이 기판으로 확산되는 것을 방지하기 위한 확산방지막 역할을 한다.After that, a Ta / TaN film 12 is sequentially formed on the entire surface of the first insulating film including the trench T2. At this time, in the Ta / TaN film 12, the Ta film is intended to solve the problem of poor adhesion between the first insulating film and the metal film to be formed thereafter, and is interposed between the first insulating film and the metal film. It serves as an adhesive film to improve adhesion. In addition, the TaN film serves as a diffusion barrier for preventing diffusion of the metal film component to be formed later onto the substrate.
이어, 상기 Ta/TaN막(12) 구조 전면에 CVD(Chemical Vapor Deposition) 공정을 진행시켜 금속막(13)을 형성한다. 이때, 상기 금속막(14)으로는 구리를 이용한다. 한편, 상기 구리막(13) 표면은 평탄하지 못하며, 트렌치(T2)와 대응된 부분이 움푹 패인 형상을 가진다.Subsequently, a CVD (Chemical Vapor Deposition) process is performed on the entire Ta / TaN film 12 structure to form the metal film 13. At this time, copper is used as the metal film 14. On the other hand, the surface of the copper film 13 is not flat, and the portion corresponding to the trench T2 has a recessed shape.
그런 다음, 상기 금속막(13) 위에 제 2절연막(14)을 형성한다. 이때, 제 2절연막(14)으로는 옥사이드막 또는 질화막 중 어느 하나를 이용한다. 한편, 제 2절연막(14)으로서 옥사이드막을 이용할 경우 500∼1000Å두께로 형성하고, 질화막을 이용할 경우 300∼500Å두께로 형성한다. 여기에서, 상기 제 2절연막으로서 질화막을 이용할 경우 옥사이드막에 비해 적은 두께로도 가능한 이유는, 상기 질화막이 옥사이드막에 비해 상대적으로 경도(硬度)가 크기 때문에 적은 두께만으로도 이 후의 씨엠피 공정에서 베리어로서의 역할을 충분하게 수행할 수 있기 때문이다.Then, a second insulating film 14 is formed on the metal film 13. At this time, either the oxide film or the nitride film is used as the second insulating film 14. On the other hand, when the oxide film is used as the second insulating film 14, it is formed to have a thickness of 500 to 1000 GPa, and when using a nitride film, it is formed to be 300 to 500 GPa. Here, when the nitride film is used as the second insulating film, the reason that the nitride film is smaller than that of the oxide film is possible because the nitride film has a relatively high hardness compared to the oxide film, so that even a small thickness is used as a barrier in the subsequent CMP process. This is because they can fully fulfill their role as.
이 후, 상기 제 2절연막(14) 위에 감광막을 도포하고, 노광 및 현상하여 트렌치(T2) 및 트렌치(T2) 주변의 제 1절연막 일부를 덮는 제 2감광막 패턴(16)을 형성한다. 이때, 상기 제 2감광막 패턴(16)은 감광막을 리버스톤(reverse tone)으로 0.05㎛ 과도 노광(over exposure)을 실시하여 트렌치(T2)와 대응된 부위 뿐만 아니라 트렌치(T2) 주변의 제 1절연막의 일부와 대응된 부분까지 잔류되도록 한다.Thereafter, a photosensitive film is coated on the second insulating film 14, and exposed and developed to form a second photosensitive film pattern 16 covering the trench T2 and a portion of the first insulating film around the trench T2. In this case, the second photoresist pattern 16 may be overexposed to the photoresist with a reverse tone, and thus may not only be exposed to the trench T2 but also may be formed around the trench T2. Allow some to remain in place.
이어, 도 3d에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하여 상기 제 2절연막을 식각하여 트렌치(T2) 및 트렌치(T2) 주변의 제 1절연막의 일부와 대응된 부분에 잔류된 제 2절연막 패턴(14a)을 형성한다. 그런 다음, 제 2감광막 패턴을 제거한다.Subsequently, as shown in FIG. 3D, the second insulating layer is etched using the second photoresist pattern as a mask, and the second insulating layer is formed on the trench T2 and the portion of the first insulating layer around the trench T2. 2 insulating film pattern 14a is formed. Then, the second photoresist pattern is removed.
이 후, 도 3e에 도시된 바와 같이, 상기 Ta/TaN막(12)이 노출되는 시점까지 제 2절연막 패턴 및 금속막을 씨엠피하여 트렌치(T2)를 매립시키는 금속 배선(13a)을 형성한다. 이때, 상기 씨엠피 공정 진행 시, 경도가 큰 제 2절연막 패턴이 연마되고 나서 그 하부의 금속막이 연마되므로, 기존에 디싱 현상 및 침식 현상이 생기는 부분, 즉 트렌치 및 트렌치 주변의 제 1절연막의 일부와 대응된 부분에서 상대적으로 금속막의 연마량이 기존과 대비하여 현저히 적어진다. 따라서, 금속막이 움푹패이는 디싱 현상 및 제 1절연막이 노출되는 현상이 발생되지 않는다.Thereafter, as illustrated in FIG. 3E, the second wiring pattern and the metal film are CMPed to the point where the Ta / TaN film 12 is exposed to form a metal wiring 13a to fill the trench T2. At this time, during the CMP process, since the second insulating film pattern having a high hardness is polished and then the metal film below the metal film is polished, a portion in which dishing and erosion occurs, that is, a portion of the first insulating film around the trench and the trench, is polished. In the portion corresponding to, the polishing amount of the metal film is significantly smaller than that of the conventional one. Therefore, the dishing phenomenon in which the metal film is recessed and the phenomenon that the first insulating film is exposed are not generated.
본 발명에 따르면, 표면이 평탄하지 못하고 움푹패인 금속막 표면, 즉 트렌치 및 트렌치 주변의 제 1절연막의 일부와 대응된 부분에 잔류되도록 경도가 큰 제 2절연막 패턴을 형성함으로써, 후속의 금속막 씨엠피 공정 진행 시, 상기 제 2절연막 패턴이 식각 베리어 역할을 한다. 따라서, 표면이 평탄하지 못하고 움푹 패인 부분에서 디싱 현상 및 침식 현상이 발생되지 않는다.According to the present invention, the subsequent metal film CEM is formed by forming a second insulating film pattern having a high hardness such that the surface remains uneven and recessed on the surface of the metal film, that is, the trench and the portion of the first insulating film around the trench. During the process, the second insulating layer pattern serves as an etching barrier. Therefore, dishing and erosion do not occur at the uneven surface of the surface.
이상에서와 같이, 본 발명은 표면이 평탄하지 못하고 움푹 패인 금속막 부위에 잔류되도록 경도가 큰 절연막 패턴을 형성함으로써, 후속의 금속막 씨엠피 공정 시, 상기 절연막 패턴이 식각 베리어 역할을 하게 되어 상기 움푹 패인 금속막 부위가 과다 연마되는 것을 방지할 수 있다.As described above, the present invention forms an insulating film pattern having a high hardness so that the surface remains on the uneven and recessed metal film portion, so that the insulating film pattern serves as an etching barrier during the subsequent metal film CMP process. Over-polishing of the recessed metal film portion can be prevented.
따라서, 본 발명은 특정 부위에서 금속막이 움푹 패이는 디싱 현상 및 절연막이 노출되는 침식현상을 방지할 수 있다.Therefore, the present invention can prevent the dishing phenomenon in which the metal film is pitted at a specific site and the erosion phenomenon in which the insulating film is exposed.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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