CN101887863B - Manufacture method of silicon perforation - Google Patents
Manufacture method of silicon perforation Download PDFInfo
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- CN101887863B CN101887863B CN2009101414022A CN200910141402A CN101887863B CN 101887863 B CN101887863 B CN 101887863B CN 2009101414022 A CN2009101414022 A CN 2009101414022A CN 200910141402 A CN200910141402 A CN 200910141402A CN 101887863 B CN101887863 B CN 101887863B
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- pit
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- perforation
- scolder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a manufacture method of a silicon perforation, comprising the following steps of firstly, supplying a wafer, wherein the wafer is provided with an active surface, a back surface and a protective layer covering the active surface; secondly, forming at least one first sunk hole, wherein the first sunk hole penetrates through the wafer; thirdly, forming insulating materials on the protective layer to form an insulating layer, wherein parts of the insulating materials are filled into the first sunk hole to form an insulating cylinder; fourthly, forming at least one second sunk hole, wherein the second sunk hole penetrates through the insulating cylinder to enable the insulating cylinder to form a hollow part in the first sunk hole; and fifthly, forming solders at the end of the hollow part and heating the solders to melt the solders, wherein a pressure difference is formed between the outside of the wafer and the inside of the hollow part, and the solders are filled in the hollow part through the pressure difference to form a conductive cylinder.
Description
Technical field
The invention relates to a kind of manufacturing approach of substrate perforation, and the manufacturing approach of particularly boring a hole relevant for a kind of silicon.
Background technology
Along with the increase of electronic product microminiaturization and high running speed requirement, multichip packaging structure is widely used in the various electronic installations gradually.Multichip packaging structure can via with two or more chip portfolios in single encapsulating structure, come the running speed of elevator system.In addition, multichip packaging structure can reduce the length of chip chamber connection line and reduce signal delay and access time.
Fig. 1 illustrates the profile of known multichip packaging structure.Please with reference to Fig. 1, known multichip packaging structure 100 comprises a wiring board 110, one first chip 120 and one second chip 130, and wherein first chip 120 is disposed at circuit 1l0 and goes up and be electrically connected to wiring board 110 via a plurality of conductive projections 140.Second chip 130 is disposed on first chip 120, and is electrically connected to wiring board 110 via a plurality of conductive projections 150 with a plurality of conductive poles 160 that run through first chip 120.
In general, the method that forms first chip 120 is described below.At first, the mode via etching or laser drill forms a plurality of perforations 122 that run through first chip 120.Then, (Chemical Vapor Deposition CVD) forms an insulating barrier 170 with chemical vapour deposition technique on the inwall 122a of perforation 122.Afterwards, in perforation 122, electroplate a conductor layer 180.
Yet the thickness of the insulating barrier 170 that forms with chemical vapour deposition technique has restriction in the sky earlier, usually less than 0.5 μ m.In addition, be formed on the uneven thickness of the insulating barrier 170 in the perforation 122, that is to say, the thickness of the insulating barrier 170 at contiguous perforation 122 two ends is different.When the uneven thickness of insulating barrier 170, there is the inconsistent situation of electric capacity to produce easily.
In addition, when electroplating conductor layer 180 in the perforation 122 in high-aspect-ratio, deposit a large amount of conductors because of the point discharge effect in that periphery C1, the C2 at the two ends of perforation 122 are last easily.The conductor that is deposited at periphery C1, C2 can hinder electroplate liquid, makes electroplate liquid be difficult for flowing in the perforation 122, so that conductor layer 180 uneven thickness and technology yield are on the low side.
Summary of the invention
The present invention proposes a kind of manufacturing approach of silicon perforation, and the mode via being formed with pressure differential outside the wafer and in the perforation can fill in the hollow bulb scolder of fusing via aforementioned pressure difference, to form conductive pole.
The manufacturing approach that the present invention proposes a kind of silicon perforation is described below.At first, a wafer is provided, the protective layer that wafer has an active surface, a back side and is covered in active surface.Then, form at least one first pit, first pit runs through wafer.Then, form one first insulating material on protective layer, forming one first insulating barrier, and part first insulating material fills in first pit, to form an insulation cylinder.Afterwards, form at least one second pit, second pit runs through insulation cylinder, so that insulation cylinder forms a hollow bulb in first pit.Then, form a scolder on the end of hollow bulb, and add hot solder, so that solder fusing wherein is formed with one first pressure differential outside the wafer and in the hollow bulb, scolder fills in the hollow bulb via first pressure differential, to form a conductive pole.
In one embodiment of this invention; The method that forms insulation cylinder comprises and forms first insulating material on protective layer and cover the end of first pit; Wherein be formed with one second pressure differential outside the wafer with in first pit, first insulating material fills in first pit via second pressure differential.
In one embodiment of this invention, the material of first insulating material comprises a polymer (Polymer).
In one embodiment of this invention, form one first insulating material on protective layer after, more comprise forming one second insulating barrier in the back side of wafer.
In one embodiment of this invention, form in the step of at least one second pit, second pit more can run through the insulation cylinder and second insulating barrier.
In one embodiment of this invention, the step that forms at least one first pit is described below.At first, a photoresist that is attached at the dry film on the protective layer or coat on the protective layer is carried out developing process, to form at least one patterns of openings.Then, carry out dry-etching, be revealed in the wafer of patterns of openings below with removal.
In one embodiment of this invention, carry out after the dry-etching, when first pit is not through to the back side of wafer, more comprise the back side of grinding wafer, to appear first pit.
In one embodiment of this invention, the step that forms at least one first pit comprises with the laser ablation wafer.
In one embodiment of this invention; Forming a pressure is worse than outer being included in the interior step of hollow bulb of wafer and does not form a scolder before on the end of hollow bulb; Wafer is positioned in the environment of first air pressure; And after adding hot solder, first air pressure is risen to second air pressure, to form pressure differential.
In one embodiment of this invention, the environment of first air pressure is a vacuum environment.
In one embodiment of this invention, the bore of first pit is greater than the bore of second pit.
The present invention proposes a kind of subsequent technique of manufacturing approach of silicon perforation of previous embodiment, and wherein scolder forms after the conductive pole, comprises that more forming one reroutes layer on first insulating barrier, and the layer that reroutes electrically connects an end of conductive pole.
In one embodiment of this invention, scolder forms after the conductive pole, more comprises forming a bump bottom metal layer (Under Bump Metallurgy layer, UBM layer) in the back side of wafer, and bump bottom metal layer electrically connects the other end of conductive pole.
Hold the above, wafer of the present invention outer with hollow bulb in be formed with pressure differential, and the scolder of fusing can fill in the hollow bulb via aforementioned pressure difference, with the formation conductive pole.Therefore, conductive pole of the present invention does not need to form with galvanoplastic, thus can avoid the problem of point discharge in the known technology, and then have higher technology yield.
For letting above-mentioned and further feature of the present invention and the advantage can be more obviously understandable, the special act of hereinafter embodiment, and conjunction with figs. elaborate as follows.
Description of drawings
Fig. 1 illustrates the profile of known multichip packaging structure.
Fig. 2 A～Fig. 2 I illustrates the process section of the silicon perforation of one embodiment of the invention.
Fig. 2 J～Fig. 2 L illustrates the profile of subsequent technique of manufacturing approach of the silicon perforation of Fig. 2 A～Fig. 2 I.
The primary clustering symbol description:
100: multichip packaging structure
110: wiring board
120: the first chips
122: perforation
122a: inwall
130: the second chips
140,150: conductive projection
160: conductive pole
170: insulating barrier
180: conductor layer
210: wafer
212: active surface
214: the back side
216: protective layer
216a: opening
218: connection pad
220: dry film
222: patterns of openings
230 first insulating material:
232: the first insulating barriers
232a: surface
234: insulation cylinder
234a: hollow bulb
240: the second insulating barriers
250: patterned conductive layer
252: end face
260: conductive pole
260a: scolder
262,264: the end
270: layer reroutes
280: the three insulating barriers
290: bump bottom metal layer
A1, A2: an end of pit
B1, B2: an end of hollow bulb
C1, C2: periphery
E1, E2: pit
S: cover body
Embodiment
Fig. 2 A～Fig. 2 I illustrates the process section of the silicon perforation of one embodiment of the invention.At first,, a wafer 210 is provided, the protective layer 216 that it has an active surface 212, a back side 214 and is covered in active surface 212 please with reference to Fig. 2 A.Wafer 210 can be the wafer with circuit.In the present embodiment, protective layer 216 has an opening 216a, and to expose the connection pad 218 that is disposed on the active surface 212, connection pad 218 for example is an aluminium pad.It should be noted that present embodiment does not limit the number of opening 216a, for instance, the number of the visual connection pad 218 of the number of opening 216a and be one or more.
Then, please with reference to Fig. 2 B, in the present embodiment, can on protective layer 216, attach a dry film 220 or be coated with a photoresist (not illustrating), and dry film 220 or photoresist are carried out developing process, to form a patterns of openings 222.
Then, please with reference to Fig. 2 C, in the present embodiment, can dry film 220 or photoresist for the cover curtain wafer 210 is carried out dry-etching, be revealed in the wafer 210 of patterns of openings 222 belows and form a pit E1 who runs through wafer 210 with removal.Then, remove dry film 220 or photoresist.In addition, the method for formation pit E1 also can be with laser ablation wafer 210.In addition, after carrying out dry-etching, when pit E1 is not through to the back side 214 of wafer 210, can grind the back side 214 of wafer 210, to appear pit E1.
Afterwards, please with reference to Fig. 2 D and Fig. 2 E, form one first insulating material 230 on protective layer 216, forming one first insulating barrier 232, and part first insulating material 230 fills among the pit E1, to form an insulation cylinder 234.The material of first insulating material 230 can be high molecular polymer (Polymer), for example benzocyclobutene (benzocyclobutene, BCB) resin or polyimide (Polyimide) resin etc.
In the present embodiment; The method that forms insulation cylinder 234 comprises and forms first insulating material 230 on protective layer 216 and cover the end A1 of pit E1; And be formed with a pressure differential outside the wafer 210 and in the pit E1, and first insulating material 230 can fill among the pit E1 via pressure differential.
Particularly, the method for formation insulation cylinder 234 is described below.At first, please with reference to Fig. 2 C, seal the other end A2 of pit E1.For instance, can a cover body S be placed on the other end A2 of pit E1, and make the back side 214 and cover body S driving fit of chip 210.Then, wafer 210 is placed in the environment (for example vacuum environment) of one first air pressure with cover body S.For instance, can wafer 210 and cover body S be positioned in the cavity that vacuumizes.Then, please with reference to Fig. 2 D, for example be on protective layer 216, to form first insulating material 230 with the mode that is coated with (coating), and the end A1 of first insulating material, 230 covering pit E1, so that pit E1 pressure inside remains on first air pressure.
Afterwards, please with reference to Fig. 2 E, for example to destroy the mode of vacuum environment (being vacuum breaker), it is one second air pressure that the wafer 210 first outer air pressure are promoted.At this moment, because the air pressure inside of pit E1 remains on the first relatively low air pressure, therefore, second air pressure that is applied on first insulating material 230 will force first insulating material 230 to be clamp-oned among the pit E1.In other words, can first insulating material 230 be inserted among the pit E1 via formed pressure differential outside wafer 210 and between in the pit E1 (i.e. the draught head of second air pressure and first air pressure).Then, removable cover body S is with the back side 214 that exposes wafer 210.
From the above, the manufacturing approach of the silicon of present embodiment perforation is via wafer 210 outside Yu in the pit E1, being formed with pressure differential, and this pressure differential can make first insulating material 230 insert in the pit E1, and formation insulation cylinder 234.Therefore, the insulation cylinder 234 of present embodiment does not need to form with chemical vapour deposition technique, so the restriction on the thickness and problem in uneven thickness in the no known technology.
Then, please with reference to Fig. 2 F, in the present embodiment, can form one second insulating barrier 240 with the mode that for example is coated with at the back side 214 of wafer 210, and the material of second insulating barrier 240 can be high molecular polymer (a for example benzocyclobutane olefine resin).In addition; In the present embodiment; Mode that can sputter forms a conductive layer (not illustrating) comprehensively on the active surface 212 of wafer 210; Covering connection pad 218, and remove the part beyond the opening 216a that is positioned at of conductive layer, in opening 216a, to form a patterned conductive layer 250 with the mode of lithography.The end face 252 of patterned conductive layer 250 can flush in fact with the surperficial 232a of first insulating barrier 232.
Afterwards, please with reference to Fig. 2 G, form a pit E2 who runs through insulation cylinder 234, so that insulation cylinder 234 forms a hollow bulb 234a in pit E1, wherein the bore of pit E1 can be greater than the bore of pit E2.In addition, pit E2 also can run through second insulating barrier 240.
Then,, form a scolder 260a on the end B1 of hollow bulb 234a, and add hot solder 260a, so that scolder 260a fusing please with reference to Fig. 2 H and Fig. 2 I.Be formed with a pressure differential outside the wafer 210 and in the hollow bulb 234a, and scolder 260a can fill among the hollow bulb 234a via aforementioned pressure difference, to form a conductive pole 260.
Particularly, in the present embodiment, the step that forms a pressure differential outside wafer 210 and in the hollow bulb 234a is described below.At first, please with reference to Fig. 2 G, seal the end B2 of hollow bulb 234a.For instance, can a cover body S be disposed on the end B2 of hollow bulb 234a, and make second insulating barrier 240 and cover body S driving fit.Then, wafer 210 is positioned in the environment (like vacuum environment) of first air pressure with cover body S.For instance, can wafer 210 and cover body S be positioned in the cavity that vacuumizes.Then, please with reference to Fig. 2 H,, scolder 260a is coated on the end B1 of hollow bulb 234a, so that the air pressure inside of hollow bulb 234a remains on first air pressure with the mode of for example screen printing (screen printing).Then, add hot solder 260a, so that scolder 260a fusion.
Afterwards, please with reference to Fig. 2 I,, the wafer 210 first outer air pressure are risen to second air pressure for example to destroy the mode of vacuum environment (being vacuum breaker).At this moment, because the air pressure inside of hollow bulb 234a remains on the first relatively low air pressure, therefore, second air pressure that is applied on the scolder 260a will force the scolder 260a of fusion to clamp-on among the hollow bulb 234a.In other words, can scolder 260a be inserted among the hollow bulb 234a, to form a conductive pole 260 via formed pressure differential outside wafer 210 and between in the hollow bulb 234a (i.e. the draught head of first air pressure and second air pressure).
Know that by aforementioned the manufacturing approach of the silicon of present embodiment perforation is via wafer 210 outside Yu in the hollow bulb 234a, being formed with pressure differential, and this pressure differential can make the scolder 260a of fusing fill among the hollow bulb 234a, with formation conductive pole 260.Therefore, the conductive pole 260 of present embodiment does not need to form with galvanoplastic, thus can avoid the problem of point discharge in the known technology, and can have comparatively homogeneous thickness and higher technology yield.
Fig. 2 J～Fig. 2 L illustrates the profile of subsequent technique of manufacturing approach of the silicon perforation of Fig. 2 A～Fig. 2 I.
At first, please with reference to Fig. 2 J, form one and reroute layer 270 on first insulating barrier 232, and the layer 270 that reroutes electrically connects an end 262 of conductive pole 260.In addition, the layer that reroutes 270 also electrically connects patterned conductive layer 250 and connection pad 218.
Then,, in the present embodiment, can on first insulating barrier 232, form one the 3rd insulating barrier 280 please with reference to Fig. 2 K, with covering reroute the layer 270.Then,, form the back side 214 of a bump bottom metal layer 290, and bump bottom metal layer 290 electrically connects an end 264 of conductive pole 260 in wafer 210 please with reference to Fig. 2 L.The multiple layer metal layer that the optional free titanium of the material of bump bottom metal layer 290, titanium-tungsten, aluminium, chromium, nickel-vanadium alloy or copper are formed is in order to electrically connect conductive projections (not illustrating) such as Solder Bumps or unleaded projection.So, the chip in the wafer 210 can be via the chip of conductive projection and another wafer (not illustrating) storehouse and form multi-chip stack structure mutually.
In sum, the manufacturing approach of silicon of the present invention perforation is via wafer outside Yu in the hollow bulb, being formed with pressure differential, and this pressure differential can make the scolder of fusing insert in the hollow bulb, with the formation conductive pole.Therefore, conductive pole of the present invention does not need to form with galvanoplastic, thus can avoid the problem of point discharge in the known technology, and can have comparatively homogeneous thickness and higher technology yield.In like manner, insulation cylinder of the present invention does not need to form with chemical vapour deposition technique, so the restriction on the thickness and problem in uneven thickness in the no known technology.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (13)
1. the manufacturing approach of silicon perforation comprises:
One wafer is provided, the protective layer that this wafer has an active surface, a back side and is covered in this active surface;
Form at least one first pit, this first pit runs through this wafer;
Form one first insulating material on this protective layer, forming one first insulating barrier, and this first insulating material of part fills in this first pit, to form an insulation cylinder;
Form at least one second pit, this second pit runs through this insulation cylinder, so that this insulation cylinder forms a hollow bulb in this first pit;
Form a scolder on the end of this hollow bulb, and heat this scolder, so that this solder fusing wherein is formed with one first pressure differential outside this wafer and in this hollow bulb, this scolder fills in this hollow bulb via this first pressure differential, to form a conductive pole.
2. the manufacturing approach of silicon perforation as claimed in claim 1, the method that wherein forms this insulation cylinder comprises:
Form this first insulating material on this protective layer and cover the end of this first pit, wherein be formed with one second pressure differential in outer and this first pit of this wafer, this first insulating material fills in this first pit via this second pressure differential.
3. the manufacturing approach of silicon perforation as claimed in claim 2, wherein the material of this first insulating material comprises a polymer (Polymer).
4. the manufacturing approach of silicon as claimed in claim 1 perforation, wherein form one first insulating material on this protective layer after, more comprise forming one second insulating barrier in this back side of this wafer.
5. the manufacturing approach of silicon perforation as claimed in claim 4 wherein forms in the step of at least one second pit, and this second pit more can run through this insulation cylinder and this second insulating barrier.
6. the manufacturing approach of silicon perforation as claimed in claim 1, the step that wherein forms at least one first pit comprises:
A photoresist that is attached at the dry film on this protective layer or coat on this protective layer is carried out developing process, to form at least one patterns of openings; And
Carry out dry-etching, be revealed in this wafer of this patterns of openings below with removal.
7. the manufacturing approach of silicon perforation as claimed in claim 6 is wherein carried out after the dry-etching, when this first pit is not through to this back side of this wafer, more comprises this back side of grinding this wafer, to appear this first pit.
8. the manufacturing approach of silicon perforation as claimed in claim 7, the step that wherein forms at least one first pit comprises with this wafer of laser ablation.
9. the manufacturing approach of silicon as claimed in claim 1 perforation wherein forms a pressure and is worse than that this wafer is outer to be comprised with the interior step of this hollow bulb:
Do not form a scolder before on the end of this hollow bulb, this wafer is positioned in the environment of first air pressure; And
Heat after this scolder, this first air pressure is risen to second air pressure, to form this pressure differential.
10. the manufacturing approach of silicon perforation as claimed in claim 9, wherein the environment of this first air pressure is a vacuum environment.
11. the manufacturing approach of silicon perforation as claimed in claim 1, wherein the bore of this first pit is greater than the bore of this second pit.
12. the subsequent technique of the manufacturing approach of a silicon perforation as claimed in claim 1, wherein this scolder forms after the conductive pole, comprises that more forming one reroutes layer on this first insulating barrier, and this layer that reroutes electrically connects an end of this conductive pole.
13. the subsequent technique of the manufacturing approach of silicon perforation as claimed in claim 12, wherein this scolder forms after the conductive pole, more comprises forming a bump bottom metal layer in this back side of this wafer, and this bump bottom metal layer electrically connects the other end of this conductive pole.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101414022A CN101887863B (en) | 2009-05-11 | 2009-05-11 | Manufacture method of silicon perforation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101414022A CN101887863B (en) | 2009-05-11 | 2009-05-11 | Manufacture method of silicon perforation |
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| Publication Number | Publication Date |
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| CN101887863A CN101887863A (en) | 2010-11-17 |
| CN101887863B true CN101887863B (en) | 2012-03-14 |
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| CN2009101414022A Active CN101887863B (en) | 2009-05-11 | 2009-05-11 | Manufacture method of silicon perforation |
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| CN104470262A (en) * | 2014-10-24 | 2015-03-25 | 成都博芯联科科技有限公司 | Three-dimensional circuit interlayer connection method based on soldering tin welding technology |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008079913A1 (en) * | 2006-12-20 | 2008-07-03 | Lam Research Corporation | Methods, apparatuses, and systems for fabricating three dimensional integrated circuits |
| CN101335261A (en) * | 2007-06-27 | 2008-12-31 | 台湾积体电路制造股份有限公司 | Formation of through via before contact processing |
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2009
- 2009-05-11 CN CN2009101414022A patent/CN101887863B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008079913A1 (en) * | 2006-12-20 | 2008-07-03 | Lam Research Corporation | Methods, apparatuses, and systems for fabricating three dimensional integrated circuits |
| CN101335261A (en) * | 2007-06-27 | 2008-12-31 | 台湾积体电路制造股份有限公司 | Formation of through via before contact processing |
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| CN101887863A (en) | 2010-11-17 |
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