JP2010129952A - Method of manufacturing through electrode wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form through-electrode wiring by forming a hole part of more uniform depth in a state where an increase in cost, breakage, etc., are suppressed without employing a complicated process. <P>SOLUTION: A silicon substrate 101 is selectively etched by RIE (Reactive Ion Etching) using a silicon oxide layer 104 as a mask to form a through-hole 106 reaching one surface of the silicon substrate 101 (an interface with a buried oxide layer 102). In the etching processing (RIE) for forming the through-hole 106, the etching progresses only up to the interface between the silicon substrate 101 and buried oxide layer 102 along the depth of the silicon substrate 101. Consequently, the through-hole 106 is formed up to a uniform depth as long as the silicon substrate 101 has a uniform plate thickness. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a through electrode wiring in which a through electrode wiring is formed on a substrate.

  Various technologies have been developed to increase the density and functionality of LSIs. In addition, it is said that the planar technology has been miniaturized to increase the density and functionality of the chip, and is now approaching this limit. Until now, LSI miniaturization has progressed in accordance with the so-called Moore's law, but the physical miniaturization limit of the element itself is becoming visible. For this reason, a high-functional approach different from Moore's Law includes not only conventional LSI manufacturing technology but also packaging technology, and is expected as a so-called “More than Moore” approach.

  As one of these approaches, a method has been proposed in which chips are three-dimensionally stacked and each stacked chip is connected by a via (through electrode wiring) penetrating the substrate (non-patent document). 1). In this technique, a basic technique is to form a through hole in a silicon substrate constituting a chip and fill the through hole with a conductive material.

  A well-known reactive ion etching (RIE) is used as a method for forming a through-electrode wiring by forming a through-hole in the silicon substrate as described above. For example, as shown in FIG. 2A, an insulating layer 202 is formed on one surface of a silicon substrate 201, an opening 203 is formed in the insulating layer 202, and then the silicon substrate 201 is formed by RIE using the insulating layer 202 as a mask. Etch. By this etching, a hole 204 having a depth halfway through the silicon substrate 201 is formed.

  Next, as illustrated in FIG. 2B, an insulating layer 205 is formed so as to cover the inner surface of the hole 204. Next, as shown in FIG. 2C, for example, a metal film 206 is formed so as to fill the hole 204 by electrolytic plating using a thin metal film formed by sputtering as a seed layer. The metal film 206 may be formed by a known chemical vapor deposition (CVD) method.

  Next, by cutting and polishing the other surface of the silicon substrate 201 by chemical mechanical polishing (CMP), as shown in FIG. 2D, a penetration made of a portion filled in the insulating layer 205 of the metal film 206 is formed. One end of the electrode wiring 207 is exposed. Thereafter, so-called bumps for connecting to other substrates (chips) are formed on the exposed portions of the through electrode wirings 207.

K. Takahashi, et al., "Process Integration of 3D Chip Stack with Vertical Interconnection", Proceeding, 2004 Electronic Components and Technology Conference (ECTC), pp.601-609, 2004. T.Sakata. Et al., "Selective Electrodeposition Technology for Organic Insulator Films on Microelectromechanical-System Structures", IEEJ Transactions E, Journal of Sensors and Micromachines, Vol.126, No.1, pp.14-18, 2006. N. Sato, et al., "Advanced transfer system for spin coating film transfer and hot-pressing in planarization technology", J. Vac. Sci. Technol. B, Vol. 20, No. 3, pp. 797-801, 2002.

  By the way, when the through hole is formed in the silicon substrate as described above, dry etching having vertical anisotropy such as RIE is generally used. However, in dry etching, the etching rate differs between the wafer surface and the chip, so it is not easy to make the depth of each hole constant. For this reason, in consideration of the above-described variation in depth, a large amount of cutting and polishing after filling with the conductive material is performed, resulting in a wasteful state.

  For example, in the hole formed deeper, the through electrode wiring made of the metal material filled therein is exposed, but in the hole formed shallower, the through electrode wiring is not exposed. It becomes. In order to prevent this, a large amount of the substrate is cut and polished so that the through-electrode wiring is exposed even in the shallowest hole. In this case, in the comparatively formed hole, not only the substrate but also the formed through electrode wiring (filling metal) is cut and polished wastefully.

  These become more prominent as the substrate becomes thicker. In other words, by making the substrate thinner, the hole can be formed shallower, and the depth variation of the hole described above can be reduced. However, by making the substrate thinner, this time, there arises a problem that the substrate is easily damaged. In particular, in CMP, since a large stress is applied to the substrate, the risk of breakage is increased by thinning the substrate. In addition, there is a problem that the process becomes more complicated and the cost is increased, for example, a more complicated support mechanism is required to suppress the breakage of the thinned substrate.

  The present invention has been made in order to solve the above-described problems, and has a more uniform depth in a state in which an increase in cost and occurrence of breakage are suppressed without using a complicated process. It is an object of the present invention to form a through electrode wiring by forming a portion.

  A method for manufacturing a through electrode wiring according to the present invention includes a first step of forming a second insulating layer having an opening on the other surface of a silicon substrate having a first insulating layer on one surface, and a second step. A second step of selectively etching the silicon substrate using the insulating layer as a mask and the first insulating layer as an etching stop layer to form a through hole reaching one surface from the other surface of the silicon substrate through the opening. And a third step of forming a third insulating layer covering the wall surface of the through hole, and after forming the third insulating layer, the through hole is filled with a conductive material to form a through electrode wiring made of the conductive material. It is a method comprising at least a fourth step and a fifth step in which a part of the first insulating layer is removed to expose the through electrode wiring on one surface side.

  In the method of manufacturing the through electrode wiring, the silicon substrate is an SOI substrate including a buried oxide layer and a silicon layer disposed on the buried oxide layer on one surface, and the first insulating layer is a buried oxide layer. In the fifth step, a part of the silicon layer may be removed in addition to the buried oxide layer so that the through electrode wiring on one surface side is exposed.

  In the through electrode wiring manufacturing method, in the third step, the third insulating layer may be formed by electrodeposition. Further, in the fourth step, a through electrode wiring made of metal may be formed by filling the through hole with metal by a plating method. In this case, in the fourth step, after the seed layer is formed by the electroless plating method, the metal may be filled by the electrolytic plating method.

  In the fourth method for manufacturing a through electrode wiring, in the fourth step, a metal dispersion paste in which metal particles are dispersed is applied to fill the through hole with metal to form a through electrode wiring made of metal. May be.

  As described above, according to the present invention, the selective etching of the silicon substrate with the first insulating layer as the etching stop layer is performed on the other surface of the silicon substrate having the first insulating layer on one surface. Since the through hole that reaches one surface from the other surface is formed, a hole with a more uniform depth can be used without increasing the cost and the occurrence of damage without using complicated processes. As a result, it is possible to obtain an excellent effect that a through electrode wiring can be formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1J are process diagrams for explaining an example of a method of manufacturing a through electrode wiring according to an embodiment of the present invention. First, as shown in FIG. 1A, a so-called SOI substrate having a surface silicon layer 103 on a silicon substrate 101 with a buried oxide layer 102 interposed is prepared. For example, an SOI substrate having a plate thickness of 625 μm is prepared in which the surface silicon layer 103 is 10 μm thick and the buried oxide layer 102 is 1 μm thick. This SOI substrate is a silicon substrate 101 having a buried oxide layer (first insulating layer) on one surface.

  Next, as shown in FIG. 1B, a silicon oxide layer (second insulating layer) 104 having an opening 105 is formed on the other surface of the silicon substrate 101. For example, the silicon oxide layer 104 is formed by oxidizing the other surface of the silicon substrate 101 by a known thermal oxidation method. Alternatively, the silicon oxide layer 104 may be formed by a CVD method. Thereafter, the silicon oxide layer 104 is patterned by a known photolithography technique and etching technique to form the opening 105.

  Next, by selectively etching the silicon substrate 101 by RIE using the silicon oxide layer 104 formed as described above as a mask, as shown in FIG. 1C, one surface of the silicon substrate 101 ( A through hole 106 that reaches the interface with the buried oxide layer 102 is formed. At this time, by comparison, the silicon oxide layer 104 functions as a mask and the buried oxide layer 102 functions as an etching stopper under conditions where silicon oxide is not etched and silicon is selectively etched. Become.

  In other words, in the etching process (RIE) for forming the through hole 106, the etching proceeds only to the interface between the silicon substrate 101 and the buried oxide layer 102 in the depth direction of the silicon substrate 101. As a result, if the thickness of the silicon substrate 101 is uniform, the depth of the through hole 106 is also formed uniformly. In the present embodiment, since the through hole 106 is formed in the substrate 101 having a thickness of about 614 μm, the through hole 106 is in a high aspect ratio state having a depth of 614 μm.

  Next, as illustrated in FIG. 1D, an insulating layer (third insulating layer) 107 is formed so as to cover the wall surface of the through hole 106. For example, with the well-known electrodeposition method, the silicon substrate 101 is used as one electrode, and an organic resin film is deposited only on the wall surface where silicon is exposed inside the through hole 106. In this electrodeposition, if the surface silicon layer 103 is not immersed in the electrodeposition solution and the silicon substrate 101 side is immersed in the electrodeposition solution, an organic resin film is formed on the surface silicon layer 103 by electrodeposition. Can be suppressed. After forming the organic resin film in this way, the insulating layer 107 is formed by thermosetting the organic resin film (see Non-Patent Document 2).

  The electrodeposition is performed under the condition that the temperature of the electrodeposition liquid is 50 ° C., and the thermosetting is a temperature of about 300 ° C. at most. Thus, the formation of the insulating layer 107 by electrodeposition can be performed at a low temperature as compared with a temperature of 400 ° C. or higher that is generally used in the formation of the insulating layer by the CVD method. As described above, if the temperature condition is 300 ° C. or lower, for example, the LSI formed in the region (not shown) of the surface silicon layer 103 of the SOI substrate can be suppressed from being affected by high temperature processing. . In addition, when a film is deposited on the inner wall of the through hole having a high aspect ratio as described above, it is not easy to form a uniform film. On the other hand, in the case of electrodeposition performed in a liquid phase, a uniform coating (insulating layer 107) can be easily formed in an area where the electrodeposition liquid can enter.

  Next, a metal (conductive material) is deposited so as to fill the inside of the through hole 106, thereby forming a metal film 108 on the surface of the silicon substrate 101 where the silicon oxide layer 104 is formed as shown in FIG. A through electrode wiring 109 is formed of a metal filling the hole 106. For example, after the silicon substrate 101 is immersed in a palladium chloride solution, it is subsequently immersed in a nickel sulfate solution, and a nickel thin film is formed by electroless plating. By using this nickel layer as a seed layer and electrolytically plating copper, the metal film 108 can be formed. According to such a plating method, since the treatment is performed in a liquid phase as in the above-described electrodeposition method, a uniform film can be formed and the through holes 106 can be filled.

  The metal film 108 may be formed only by electroless plating of nickel, or the metal film 108 may be formed by electroplating gold or silver using a seed layer formed by electroless plating of nickel. Good. The metal film 108 is not limited to the metal described above, and may be composed of any metal as long as it is a metal that can be plated, or a combination of metals that can be formed.

  The formation of the metal film 108 is not limited to the plating method. For example, the metal film 108 is formed by applying a metal dispersion paste in which metal particles are dispersed, such as a well-known silver paste, so as to fill the through holes 106. Also good. In the application of the metal dispersion paste, for example, a coating film that fills the through hole 106 may be formed by applying the metal dispersion paste by sweeping with a squeegee. Moreover, you may apply | coat using the slit coater currently used by manufacture of a liquid crystal display device. Alternatively, coating and filling may be performed using a mask (screen) by a screen printing method. Further, the filled metal film 108 can be formed by applying pressure and heat transfer to the metal dispersion paste film applied to the base film by STP (Spin-coating film Transfer and hot Pressing) method ( (See Patent Document 3).

  Here, in each of the above-described techniques, the viscosity of the metal dispersion paste is adjusted by the ratio of the solvent and the dispersion medium, and after filling and coating, the solvent and the dispersion medium are volatilized and removed by heat treatment at an appropriate temperature. Process is required. In the above description, the silver paste is taken as an example. However, the present invention is not limited to this, and it is a metal dispersion paste in which nickel, cobalt, gold, and copper fine particles, ultrafine particles, or a mixture thereof is dispersed in a dispersion medium. May be. Needless to say, any metal may be used as long as it can be dispersed in the dispersion medium as fine particles.

  Next, the metal film 108 is patterned by a known lithography technique and etching technique to form the back surface pad electrode 110 connected to the through electrode wiring 109 as shown in FIG. 1F.

  Next, the buried oxide layer 102 is used as an etching stop layer, the surface silicon layer 103 is removed, and the buried oxide layer 102 is exposed as shown in FIG. 1G. For example, the surface silicon layer 103 may be selectively removed by RIE in which silicon is selectively etched. Also, according to wet etching using an etching solution such as potassium hydroxide aqueous solution or TMAH (Tetramethyl ammonium hydroxide), silicon oxide and other metals are not etched, so that only the surface silicon layer 103 can be etched.

  The removal of the surface silicon layer 103 may be performed in a region where the through electrode wiring 109 is formed. For example, in other regions where elements not shown are formed, a mask pattern or a passivation film may be formed and protected so that the surface silicon layer 103 is not removed.

  Next, the buried oxide layer 102 where the through electrode wiring 109 is formed is removed by a known photolithography technique and etching technique, and a through hole 111 is formed as shown in FIG. 1H. For example, the through hole 111 can be formed by wet etching using hydrofluoric acid. Thus, by removing a part of the buried oxide layer 102 and forming the through hole 111, one end of the through electrode wiring 109 is exposed on one surface side of the silicon substrate 101.

  Next, as shown in FIG. 1I, a surface pad electrode is formed by depositing gold by an electrolytic plating method using a resist pattern 112 formed by a known photolithography technique and connecting to the through electrode wiring 109 through the through hole 111. 113 is formed. For example, as described above, gold electroplating may be performed by using a seed layer formed by electroless plating of Ni. As a result of the above, a via that ensures conduction between the back surface side and the front surface side of the silicon substrate 101 is formed.

  Thereafter, as shown in FIG. 1J, bumps 114 and bumps 115 are formed on the back surface pad electrode 110 and the front surface pad electrode 113. As is well known, the bumps 114 and 115 may be formed by plating, or stud bumps may be used.

  According to this embodiment described above, a plurality of through-holes 106 can be formed in a uniform state even with the substrate 101 having a thickness of about 614 μm. Note that the present invention is not limited to the above-described thickness substrate, and may be a substrate thicker than this, and is applicable to a substrate thinner than this, for example, a substrate thinner than 300 μm. Needless to say.

  Here, as the insulating film formed on the wall surface of the hole or the through hole, a silicon oxide film formed by a plasma CVD method is generally used. When a thick substrate is used for the purpose of suppressing breakage or the like, the through hole for forming the through electrode wiring has a high aspect ratio. In order to form a uniform film on the inner wall of the through-hole having such a high aspect ratio by the CVD method, a so-called surface reaction-controlled temperature condition is used, and it is preferable to carry out at a lower temperature. Further, from the viewpoint of suppressing damage to elements such as transistors formed on the substrate, the processing temperature is required to be 400 ° C. or lower.

  On the other hand, in order to deposit a film by the CVD method, it is necessary to set the temperature higher than the temperature at which the source gas decomposes, and sometimes the low-temperature conditions as described above cannot be satisfied. The same applies to the case where the metal material is filled in the through hole by the CVD method. Also in the plating method, it is known that when a seed layer is formed by a vapor phase growth method such as a sputtering method, it is not easy to grow a uniform film on the inner wall of a through hole having a high aspect ratio.

  On the other hand, as described above, if the aspect ratio is lowered by making the substrate thinner, these problems can be solved to some extent. For example, a technique has been developed that eliminates the above-described problems caused by the high aspect ratio by using a silicon substrate having a thickness of about several tens to 200 μm. However, as described above, such a thin substrate is very easily damaged, and the process becomes complicated and the cost becomes very high. For these reasons, it is generally not easy to form a through electrode wiring on a thick substrate having a thickness exceeding 300 μm.

  On the other hand, according to the above-described embodiment, the insulating layer 107 is formed so as to cover the wall surface of the through-hole 106 by the electrodeposition method rather than the vapor phase growth method such as the CVD method. Even in a thick and high aspect ratio state, a uniform film can be easily formed. Further, the through electrode wiring 109 is formed not by vapor phase growth such as CVD but only by plating, and by applying a metal dispersion paste. For this reason, even if the substrate is thick and has a high aspect ratio, the through electrode wiring 109 can be uniformly formed in the through hole 106.

  In the above description, the SOI substrate is used. However, the present invention is not limited to this. For example, a silicon oxide film is formed on the surface of a silicon substrate by a thermal oxidation method or a CVD method, and a through hole penetrating the silicon substrate is formed using the silicon oxide film as an etching stop layer, and a through electrode wiring is formed in the through hole. May be formed. In this case, the silicon oxide film formed on the surface of the silicon substrate corresponds to the above-described buried oxide layer 102, and except for the removal of the surface silicon layer 103, the same as in the above-described embodiment, A through electrode wiring can be formed. Further, the insulating film is not limited to a silicon oxide film, and may be any insulating film that can be formed on the surface of a silicon substrate, such as a silicon nitride film. However, in this case, since the surface silicon layer 103 is not present, it is necessary to pay attention to the fact that the number of supporting layers is reduced and it is easily damaged.

  Also, according to the formation of the insulating layer by electrodeposition method and the formation of the through electrode wiring using the plating method or metal dispersion paste, the insulating layer is formed on the side wall of the opening formed on one surface of the silicon substrate, Thereafter, a through electrode wiring filling the inside of the opening can be formed, and thereafter, the other surface can be polished by CMP to expose the through electrode wiring. In this way, even when a thick silicon substrate is used, it is possible to form a through electrode wiring by forming an opening (through hole) with a high aspect ratio.

Further, the substrate is not limited to silicon, and a substrate made of an insulating material having a dielectric loss tangent smaller than 10 ⁻² such as ceramic, quartz, and glass may be used. Such an insulating material has excellent high-frequency characteristics. In the case of using such an insulating substrate, it is not necessary to form an insulating layer on the side wall after forming the opening, and the opening may be directly filled with metal. This metal filling may be formed by applying using a metal dispersion paste as described above. Further, a plating method such as electroless plating may be used.

  In the case of the insulating substrate as described above, as described above, the opening may be formed by the RIE method, or may be formed by machining with a micro drill. Moreover, when using ceramic, it is good also as a state by which the through-hole is previously formed, when shape | molding a board | substrate by baking.

It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating an example of the manufacturing method of the penetration electrode wiring in embodiment of this invention. It is process drawing for demonstrating the method of forming a through-hole in a silicon substrate and forming a through-electrode wiring. It is process drawing for demonstrating the method of forming a through-hole in a silicon substrate and forming a through-electrode wiring. It is process drawing for demonstrating the method of forming a through-hole in a silicon substrate and forming a through-electrode wiring. It is process drawing for demonstrating the method of forming a through-hole in a silicon substrate and forming a through-electrode wiring.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Silicon substrate, 102 ... Embedded oxide layer, 103 ... Surface silicon layer, 104 ... Silicon oxide layer (2nd insulating layer), 105 ... Opening part, 106 ... Through-hole, 107 ... Insulating layer (3rd insulating layer), DESCRIPTION OF SYMBOLS 108 ... Metal film, 109 ... Through-electrode wiring, 110 ... Back surface pad electrode, 111 ... Through-hole, 112 ... Resist pattern, 113 ... Front surface pad electrode, 114, 115 ... Bump.

Claims (6)

A first step of forming a second insulating layer having an opening on the other surface of the silicon substrate having the first insulating layer on one surface;
The silicon substrate is selectively etched using the second insulating layer as a mask and the first insulating layer as an etching stop layer, and reaches the one surface from the other surface of the silicon substrate through the opening. A second step of forming a through hole;
A third step of forming a third insulating layer covering the wall surface of the through hole;
A fourth step of forming the through-electrode wiring made of the conductive material by filling the through-hole with a conductive material after forming the third insulating layer;
And a fifth step of exposing the through electrode wiring on one surface side by removing a part of the first insulating layer. In the manufacturing method of the penetration electrode wiring according to claim 1,
The silicon substrate is an SOI substrate including a buried oxide layer and a silicon layer disposed on the buried oxide layer on one surface,
The first insulating layer is the buried oxide layer;
In the fifth step, a part of the silicon layer is also removed in addition to the buried oxide layer so that the through electrode wiring on one surface side is exposed. In the manufacturing method of the penetration electrode wiring according to claim 1 or 2,
In the third step, the third insulating layer is formed by electrodeposition. In the manufacturing method of the penetration electrode wiring according to any one of claims 1 to 3,
In the fourth step, the through-electrode wiring made of the metal is formed by filling the through-hole with metal by a plating method. In the manufacturing method of the penetration electrode wiring according to claim 4,
In the fourth step, after forming a seed layer by an electroless plating method, the metal is filled by an electrolytic plating method. In the manufacturing method of the penetration electrode wiring according to any one of claims 1 to 3,
In the fourth step, a metal-dispersed paste in which metal particles are dispersed is applied to fill the through-hole with metal to form a through-electrode wiring made of the metal. Method.

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