JP2005093954A - Substrate having through electrode, its manufacturing method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the necessity of forming a contact hole for establishing conduction with a conductive layer. <P>SOLUTION: A substrate 1 having a through electrode is fabricated from an SOI wafer 2 having an embedded insulating layer 20 between a support substrate layer 10 and a silicon layer 30. Etching is effected using a protection layer 11 as a mask to form a blind via hole 12 which has a depth that extends through the support substrate layer 10 and the embedded insulating layer 20 and reaches the silicon layer 30 (a depth that additionally allows formation of a recess 30a). An inner wall insulating layer 13 is applied onto the blind via hole 12 to form a conductive layer 14. Then, the silicon layer 30 is removed to allow the conductive layer 14 to expose to a rear. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate with a through electrode used for high-density three-dimensional mounting such as a silicon IC chip, a method for manufacturing the same, and an electronic device.

  Recently, in order to efficiently realize high-density three-dimensional mounting by stacking silicon IC chips or the like, it has been studied to form a through wiring on the substrate that allows the silicon substrate to be connected through.

  As a method of forming a through electrode for realizing such a through wiring on a substrate, conventionally, a procedure as shown in FIG. 3 is performed.

  First, as shown in FIG. 3A, a protective layer 111 for masking blind via holes is formed on a silicon wafer 102 having a thickness of about 300 to 600 μm, for example.

  Next, as shown in FIG. 3B, blind via holes 112 are formed in the silicon wafer 102 up to about 70 to 90% of its thickness.

  Next, as illustrated in FIG. 3C, an insulating layer 113 is formed on the inner wall of the formed blind via hole 112.

  Next, as shown in FIG. 3D, a blind via hole 112 in which the inner wall insulating layer 113 is formed is filled with a metal for penetrating wiring to form a conductive layer 114.

  Next, as shown in FIG. 3E, polishing is performed from the side opposite to the surface where the blind via hole 112 is formed on the silicon wafer 102 (back surface) to expose the metal portion where the conductive layer 114 is formed. At this time, the protective layer (oxide film) formed on the back surface is lost by polishing. Further, after polishing, the silicon other than the electrode portion (conductive layer 114) may be slightly polished (for example, several μm) by etching, for example.

  Next, as shown in FIG. 3F, an insulating layer 115 is formed for insulation on the back side.

Thereafter, as shown in FIG. 3G, a portion of the back insulating layer 115 corresponding to the electrode portion (conductive layer 114) is removed to form a contact hole 121 for conduction.
Japanese Patent Laid-Open No. 2002-064146 JP 2002-270563 A

The conventional through electrode forming method has the following problems. That is,
(1) In the blind via hole forming step shown in FIG. 3B, the etching depth varies.
(2) In the blind via hole forming step, as the diameter of the blind via hole 112 becomes smaller (for example, 30 μm or less), it becomes difficult to measure the etching depth with a depth measuring device such as a laser microscope. The depth cannot be verified.
(3) In the back surface polishing step shown in FIG. 3 (e), polishing must be performed with the shallowest blind via hole 112 as a reference.
(4) Since the protective layer (oxide film) formed on the back surface is removed in the back surface polishing step, a back surface insulating layer 115 forming step is required as shown in FIG.
(5) In the back surface polishing step, since the protective layer on the back side, that is, the insulating layer is once removed, the quality of the insulating layer formed again may be deteriorated. As a result, the withstand voltage (withstand voltage) on the back side is reduced. descend.

Therefore, in order to solve the above problems (1) to (5) under the present applicant, it is formed on one side of the silicon substrate layer (supporting substrate layer) 10 as described below with reference to FIG. A silicon wafer 2 in which the silicon oxide film 20 is formed as a buried insulating layer 20 by forming a single crystal silicon layer 30 (including pasting) on the surface of the silicon oxide film 20, that is, an SOI (Silicon On Insulator) wafer 2 Has developed a method for producing a substrate with a through electrode from Japan, and applied for a patent (Japanese Patent Application No. 2003-198023).
(A) A protective layer 11 for forming a blind via hole is formed on the SOI wafer 2. The SOI wafer 2 has, for example, a total thickness of 300 to 600 μm, a silicon substrate layer 10 of about 250 to 550 μm, and a buried insulating layer 20 of about 0.1 to 2 μm. The protective layer 11 is usually made of an oxide film (SiO ₂ ), a photoresist, or an oxide film + photoresist.
(B) The blind via hole 12 is formed. At this time, since the blind via hole 12 has a slower etching speed than the Si (silicon) buried insulating layer 20 (selection cost 100 or more), the hole in the outer peripheral portion reaches the buried insulating layer 20, and the etching of the portion is not performed. Even after stopping, the etching can be continued until the hole in the inner periphery reaches the layer. Therefore, blind via holes 12 with high depth uniformity are formed, and the depth is the depth at which the buried insulating layer is formed in the silicon wafer 2.
(C) The insulating layer 13 is formed on the inner wall of the formed blind via hole. As the formation method, a thermal oxidation method, a PE-CVD method, an anodic oxidation method or the like can be considered.
(D) A metal for penetrating wiring is filled in the blind via hole 12 in which the insulating layer 13 is formed, and the conductive layer 14 is formed. As a forming method, a molten metal suction method, a printing method, a CVD method, or the like immersed in the molten metal in a reduced pressure space can be considered.
(E) The silicon layer 30 is removed by polishing or etching from the opposite side (back side) to the buried via hole forming surface to the buried insulating layer 20. By this step, the buried insulating layer 20 formed so far in the silicon functions as the insulating layer on the outermost surface on the back surface side.
(F) The insulating layer immediately below the electrode portion is removed by patterning, etching, or polishing to form a conduction hole (contact hole 21).

Although the above-described problems (1) to (5) can be solved by the method shown in FIG. 4, the following problems occur in the method of FIG.
(A) When forming a conductive layer using the molten metal suction method in the step of “(d) conductive layer formation”, the filling is not performed completely by the principle, and as shown in FIG. In some cases, a gap (arrow A portion) is formed. This gap is several μm at the maximum.
(B) After removing the silicon layer 30 in the “(e) backside removal” step, the adhesion between the filled metal (conductive layer 14) and the oxide film (buried insulating layer 20) (arrow (B) in FIG. 5B) Since the adhesiveness of the part is poor, a gap may occur between them.
(C) When the contact hole 21 is formed in the step “(f) contact hole formation”, an unintended portion of the oxide film (the buried insulating layer 20) is etched by the gap as shown in FIG. Abnormal etching may occur.

  The problem of the present invention was made in view of the above circumstances, eliminating the disadvantages of the conventional substrate with a through electrode shown in FIG. 3, and making the depth of the blind via hole and the polishing amount on the back side constant, In addition, the process of forming the insulating layer on the back surface side is unnecessary, and it is possible to prevent a decrease in the withstand voltage (withstand voltage), and to eliminate the drawbacks of the substrate with through electrodes shown in FIG. A substrate with a through electrode having various advantages, such as a gap does not occur in the outer periphery of the substrate, an adhesion problem does not occur, and an abnormal etching problem does not occur, a manufacturing method thereof, and an electronic device using the substrate The purpose is to provide.

The invention of claim 1 for solving the above-mentioned problem is a substrate with through electrodes made from a silicon wafer having a buried insulating layer between a supporting substrate layer and a silicon layer,
A conductive layer is formed on the support substrate layer by applying an inner wall insulating layer to a blind via hole formed to a depth reaching the silicon layer through at least the entire thickness of the buried insulating layer using a protective layer as a mask, and then forming the conductive layer. The conductive layer is exposed by removing the layer.

The invention of claim 2 is a substrate with a through electrode made of a silicon wafer having a buried insulating layer between a support substrate layer and a silicon layer,
The support substrate layer is filled with a protective layer as a mask, penetrates the entire insulating layer thickness, reaches the silicon layer, and is formed to a depth where a recess is formed in the silicon layer. After the formation of the layer, the silicon layer is removed so that a portion corresponding to the recess of the conductive layer is exposed as a protruding portion outside the wafer.

According to a third aspect of the present invention, in the substrate with a through electrode according to the first or second aspect, the silicon oxide film is formed by forming a single crystal silicon layer on the surface of the silicon oxide film formed on one side of the support substrate layer as a silicon wafer. The present invention is characterized in that an SOI wafer configured as a buried insulating layer is used.

Invention of Claim 4 is a manufacturing method of the board | substrate with a penetration electrode using the silicon wafer which has a buried insulating layer between a support substrate layer and a silicon layer,
Forming a protective layer for masking a blind via hole on the surface of the support substrate layer; forming a blind via hole in the support substrate layer using the buried insulating layer as a stop layer; and reaching the buried insulating layer Further etching the buried insulating layer at the bottom of the blind via hole to form a blind via hole having a depth reaching the silicon layer through the entire buried insulating layer thickness, and forming an insulating layer on the inner wall of the formed blind via hole Process,
The method includes a step of filling the blind via hole in which the inner wall insulating layer is formed with a metal for penetrating wiring to form a conductive layer, and a step of removing the silicon layer to expose the conductive layer. .

The invention of claim 5 is a method of manufacturing a substrate with a through electrode using a silicon wafer having a buried insulating layer between a support substrate layer and a silicon layer,
Forming a protective layer for masking a blind via hole on the surface of the support substrate layer; forming a blind via hole in the support substrate layer using the buried insulating layer as a stop layer; and reaching the buried insulating layer Etching the buried insulating layer at the bottom of the blind via hole to form a blind via hole having a depth reaching the silicon layer; further etching the silicon layer at the bottom of the blind via hole reaching the silicon layer; Forming a recess in the layer; forming an insulating layer on the inner wall of the formed blind via hole; and filling the blind via hole in which the inner wall insulating layer is formed with a metal for penetrating wiring to form a conductive layer A step corresponding to the recess of the conductive layer by removing the silicon layer Characterized in that a and a step of exposing a wafer outer ridges.

  A sixth aspect of the present invention is an electronic device using the substrate with a through electrode according to the first, second, or third aspect.

  According to the present invention, the depth of the blind via hole and the polishing amount on the back surface side can be made constant as in the case of the substrate with through electrodes by the manufacturing method described in FIG. Since an insulating layer derived from an SOI substrate having a good quality can be used, the breakdown voltage (withstand voltage) is reduced in advance due to poor quality of an insulating layer such as a low-temperature oxide film formed in a separate process. There is an effect that can be prevented.

Furthermore, since the conductive layer in the present invention is formed by filling a metal into a blind via hole formed to a depth reaching at least the silicon layer through the buried insulating layer, the following effects can be obtained and the manufacturing described with reference to FIG. The problem of the method is solved.
(1) By simply removing the silicon layer on the back surface, the conductive layer is exposed to the outside on the back surface side, so that the through electrode can be formed without requiring a step of forming a contact hole.
(2) Since there is no step of forming a contact hole, there is no room for the problem of abnormal etching of the contact hole.
(3) For example, when a molten metal suction method in which the conductive layer is formed in a molten metal in a reduced pressure space is adopted as the conductive layer forming step, the blind via hole reaches the silicon layer. When this is formed, there is no room for a problem that a gap is generated between the conductive layer (filling metal) and the insulating layer.
(4) Further, there is no room for the problem that the adhesion between the filling metal and the oxide film is poor in the state after removing the silicon layer on the back surface in the back surface removing step, and therefore no gap is generated between them. .
(5) As in claim 2, the conductive layer is formed outside the wafer (outside of the wafer opposite to the blind via hole forming surface) by etching to a depth at which the recess is formed in the silicon layer. it can. That is, a through electrode (conductive layer) having a raised portion (bump) can be formed. The bump height can be arbitrarily controlled by appropriately setting the recess formed in the silicon layer.

  Hereinafter, a substrate with a through electrode, a manufacturing method thereof, and an electronic device using the same according to the present invention will be described with reference to the drawings.

  FIG. 1 is a partial sectional view of a substrate 1 with a through electrode according to an embodiment of the present invention. The substrate with a through electrode 1 of this embodiment has an internal insulating layer (hereinafter referred to as a buried insulating layer 20) between a supporting substrate layer 10 (hereinafter referred to as a silicon substrate layer) mainly made of silicon and a silicon layer 30. ) Is used. As a silicon wafer having such a buried insulating layer 20, for example, a single crystal or a polycrystal is formed on one surface of a silicon substrate layer 10 and generally on the surface of a silicon oxide film 20 (also referred to as a thermal oxide film) formed by thermal oxidation. The SOI (Silicon On Insulator) wafer 2 in which the silicon oxide film 20 is formed as the buried insulating layer 20 is formed by bonding or growing the silicon layer 30. In general, the quality of the thermal oxide film is good.

  This substrate 1 with through-electrodes penetrates the entire thickness of a buried insulating layer (silicon oxide film) 20 in a supporting substrate layer (silicon substrate layer) 10 using the protective layer 11 as a mask, and the silicon layer (single crystal silicon layer) 30. And after forming the conductive layer 14 on the blind via hole 12 formed to the depth at which the recess 30a is formed in the silicon layer 30 and applying the inner wall insulating layer 13, the silicon layer 30 is removed, A portion of the conductive layer 14 corresponding to the recess 30a is exposed as a protruding portion (bump) 14a outside the wafer, and this protruding portion 14a becomes a portion to which wiring is connected.

  FIG. 2 shows an embodiment of a manufacturing method for manufacturing the substrate 1 with through electrodes shown in FIG. 1, which is a process diagram shown in a sectional view, and is manufactured in the order of (a) to (g). This substrate 1 with a through electrode uses the SOI wafer 2 as a silicon wafer having a buried insulating layer 20 between a supporting substrate layer 10 and a silicon layer 30.

  First, as shown in FIG. 2A, an SOI wafer 2 is prepared, and a protective layer 11 for masking blind via holes is formed on the support substrate layer 10. The total thickness of the SOI wafer 2 is 300 to 600 μm, the thickness of the supporting substrate layer 10 forming the blind via hole is 250 to 550 μm, the thickness of the buried insulating layer 20 is about 0.1 to 2 μm, and the silicon layer 30 The thickness is about 5 to 50 μm. As a specific example of the SOI wafer 2, for example, a wafer having a total thickness of 400 μm, a buried insulating layer 20 thickness of 0.3 μm, and a silicon layer (BOX layer) 30 having a thickness of 30 μm is used.

  As the protective layer 11, either one or both of an oxide film such as silicon dioxide (SiO 2) and a photoresist are usually used. For example, the oxide film has a selectivity to silicon of about 100 to 200, and the photoresist is about 50 to 100. Therefore, considering the depth of the blind via hole to be formed, the kind of the protective layer 11 as an etching mask and Determine the thickness. That is, the diameter of the blind via hole to be formed is smaller than the total thickness of the SOI wafer 2 and is, for example, about 5 to 200 μm, the depth of the blind via hole is about 250 to 550 μm, and the shape of the blind via hole is The shape can be any shape, round or square, and the number of blind via holes can be any number as necessary.

Next, as shown in FIG. 2B, a blind via hole (Blind) is formed on the SOI wafer 2 described above.
Via Hole) 12 is formed. In this blind via hole forming process, for example, DRIE (Deep Reactive Ion Etching) method, laser processing method, micro drill processing method, PAECE (Photo
Any formation method such as an Assisted Electro-Chemical Etching method can be used.

  At this time, the blind via hole 12 is formed using the buried insulating layer 20 as an etching stop layer. That is, since the buried insulating layer 20 has a slower etching rate than silicon (selection ratio 100 or more), even after the blind via hole 12 in the outer peripheral portion of the substrate reaches the buried insulating layer 20 and etching of that portion stops, The etching can be continued until the blind via hole 12 in the inner periphery reaches the buried insulating layer 20. Thereby, the blind via hole 12 with high depth uniformity is formed over the entire SOI wafer 2, and the depth is the depth at which the buried insulating layer 20 is formed in the SOI wafer 2. As a result, the problems (1), (2), and (3) described above as problems of the conventional method of FIG. 3 are solved.

Next, as shown in FIG. 2C, the buried insulating layer 20 at the bottom of the blind via hole 12 is further etched to form the blind via hole 12 having a depth reaching the silicon layer 30.
In this case, the etching is performed by dry etching or wet etching.
In the case of wet etching, a mixed solution of BOE (Buffered Oxide Etchant, HF: NHF4 = 1: 6) hydrofluoric acid, nitric acid, and acetic acid can be used. At this time, the etching rate of the buried insulating layer 20 is about 0.1 μm / min.
In the case of dry etching, for example, carbon tetrafluoride (CF ₄ ) gas can be used.

Next, as shown in FIG. 2D, the silicon layer 30 at the bottom of the blind via hole 12 reaching the silicon layer 30 is further etched to form a recess 30a in the silicon layer 30 at the bottom.
At this time, by setting the etching depth of the silicon layer 30 as desired, the bump height after completion can be controlled as will be described later.
In this “Si additional etching” step (step of etching the silicon layer 30), dry etching is used. In this dry etching, for example, sulfur hexafluoride (SF ₆ ) gas, carbon octafluoride (C ₄ F ₈ ) gas, CF ₄ gas, oxygen (O ₂ ) gas, or a mixed gas thereof may be used. it can. For example, when the Deep-RIE method is used, a mixed gas of SF ₆ gas (130 sccm) + O ₂ gas (13 sccm) for 12 seconds and C ₄ F ₈ gas (85 sccm) for 9 seconds are switched. At this time, the RF output is 600 W, for example. The etching rate at this time is about 2 μm / min.

  Next, as shown in FIG. 2E, an insulating layer 13 is formed on the inner wall of the formed blind via hole 12. In this inner wall insulating layer forming step, for example, an arbitrary forming method such as a thermal oxidation method, a PE-CVD (plasma enhanced chemical vapor deposition) method, an anodic oxidation method, or a sputtering method can be used.

  Next, as shown in FIG. 2F, the blind via hole 12 in which the inner wall insulating layer 13 is formed is filled with a metal for penetrating wiring to form a conductive layer 14. In this conductive layer forming step, for example, an arbitrary forming method such as a molten metal suction method, a printing method, or a CVD (Chemical Vapor Deposition) method can be used.

Next, as shown in FIG. 2G, from the back surface side (opposite to the blind via hole forming surface) to the buried insulating layer 20, polishing or etching or a composite process of these portions of the silicon layer 30 and the outside of the conductive layer 14 is performed. The insulating layer portion (the portion along the surface of the recess 30a) is removed to expose the buried insulating layer 20, and at the same time, the portion of the conductive layer 14 corresponding to the recess 30a is exposed as the raised portion 14a outside the wafer. . In this way, the conductive layer 14 having the raised portions (bumps) 14a exposed on the back surface side is obtained. Therefore, unlike the substrate 1 ′ with a through electrode in FIG. 4, it is not necessary to bother to form the contact hole 21 for enabling conduction with the conductive layer.
This “rear surface portion removal” step is divided into a back surface silicon removal step and an insulating layer removal step (note that only the back surface silicon removal step may be considered).
The back side silicon removal process, that is, the etching process of the silicon layer 30 is performed by dry etching using, for example, SF ₆ gas, CF ₄ gas, oxygen gas, or a mixed gas thereof, or a hydrofluoric acid / nitric acid / acetic acid mixed solution, potassium hydroxide It can be performed by wet etching using an aqueous solution. It is also possible to employ physical polishing or the like.
The insulating layer removing step when the insulating layer is formed on the surface of the recess 30a of the silicon layer 30 and needs to be removed may be the same as the removing step of the buried insulating layer 20 described in FIG. . That is, in the case of wet etching, a mixed solution of BOE (Buffered Oxide Etchant, HF: NHF4 = 1: 6) hydrofluoric acid, nitric acid and acetic acid can be used. In the case of dry etching, for example, carbon tetrafluoride ( CF ₄ ) gas can be used.
It is also conceivable that the recess 30a is not formed in the back side silicon layer 30 in the blind via hole forming step. In this case, the outermost surface of the conductive layer 14 is flush with the surface of the buried insulating layer 20, but it is naturally not necessary to form a contact hole.

  Since the buried insulating layer 20 that has been formed in the silicon layer 30 until then by the backside silicon removing step functions as an insulating layer exposed on the backside, it has been described as a problem of the conventional method of FIG. The problems 3), (4), and (5) are solved.

As described above, according to the method for manufacturing the substrate with through electrodes 1, the problem with the conventional substrate with through electrodes described with reference to FIG. 3 is solved in the same manner as with the substrate 1 ′ with through electrodes described with reference to FIG. 4. That is,
[1] In the blind via hole forming step shown in FIG. 2B, there is no variation in the depth of the formed blind via hole 12.
[2] In the blind via hole forming step, even if the diameter of the blind via hole 12 is reduced, the depth can be made exactly constant regardless of the diameter.
[3] In the backside silicon removal step of FIG. 2G, the polishing amount can be made exactly constant.
[4] In the backside silicon removal step, since the buried insulating layer 20 functions as a new insulating layer, a separate step of forming the backside insulating layer becomes unnecessary.
[5] In the backside silicon removal step, the back side of the silicon substrate layer 10 is not exposed, so that the withstand voltage (withstand voltage) does not decrease.

According to the substrate 1 with a through electrode, the conductive layer 14 is filled and formed in the blind via hole 12 formed to a depth that penetrates the buried insulating layer, reaches the silicon layer 30, and further forms the recess 30a. There are effects like this.
<1> A through electrode can be formed without forming a contact hole.
<2> Since there is no step of forming a contact hole, there is no room for the problem of abnormal etching of the contact hole.
<3> When forming the conductive layer 14 using, for example, a molten metal suction method in the conductive layer forming step, there is no problem that a gap is generated between the conductive layer 14 and the insulating layer (the embedded insulating layer 20). .
<4> There is no room for the problem that the adhesion between the filling metal 14 and the oxide film (the buried insulating layer 20) is poor after the silicon layer 30 is removed in the back surface removal step, and therefore a gap is generated between them. There is nothing.
<5> By etching to a depth at which the recess 30a is formed in the silicon layer 30, the conductive layer 14 can be shaped out of the wafer (outside of the wafer opposite to the blind via hole forming surface). That is, a through electrode (conductive layer 14) having a raised portion (bump) 14a can be formed. The bump height can be arbitrarily controlled by appropriately setting the recess 30a formed in the silicon layer 30.

  In the above embodiment, the SOI wafer 2 in which the silicon oxide film 20 is formed as the buried insulating layer 20 by forming the single crystal silicon layer 30 on the surface of the silicon oxide film 20 formed on one side of the silicon substrate layer 10. However, the present invention is not limited to this, and an appropriate material other than the SOI wafer 2 may be used as long as it has a buried insulating layer 20 with good quality between the support substrate layer 10 and the silicon layer 30. It is possible.

  Furthermore, this invention is applied also to the electronic device using the above board | substrates 1 with a penetration electrode. Here, the electronic device refers to a device in which various semiconductor circuits or elements are formed or mounted on a substrate with a through electrode or on the substrate itself. Specifically, it refers to an LSI or a light emitting / receiving device. Or it includes the case where these devices are used as part of an assembled object.

It is a fragmentary sectional view of the board | substrate with a penetration electrode of one Example of this invention. It is process drawing shown in sectional drawing of one Example of the manufacturing method which manufactures the board | substrate with a penetration electrode of FIG. 1, and is manufactured in order of (a)-(g). It is process drawing shown with sectional drawing of the conventional manufacturing method which manufactures a board | substrate with a penetration electrode, and is manufactured in order of (a)-(g). BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the main subjects that this invention tends to solve, and is process drawing shown with sectional drawing of the manufacturing method of the board | substrate with a through-electrode which is not well-known, and manufactured in order of (a)-(f). Is done. (A), (b), and (c) are diagrams for explaining problems of the manufacturing method shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate with substrate 2 SOI (Silicon On Insulator) wafer 10 Support substrate layer (silicon substrate layer)
11 Protective layer 12 Blind via hole 13 Insulating layer (inner wall insulating layer)
14 conductive layer 14a ridge 20 buried insulating layer (silicon oxide film)
30 Silicon layer (single crystal silicon layer)
30a recess

Claims (6)

A substrate with a through electrode made from a silicon wafer having a buried insulating layer between a supporting substrate layer and a silicon layer,
A conductive layer is formed on the support substrate layer by applying an inner wall insulating layer to a blind via hole formed to a depth reaching the silicon layer through at least the entire thickness of the buried insulating layer using a protective layer as a mask, and then forming the conductive layer. A substrate with a through electrode, wherein the conductive layer is exposed by removing the layer. A substrate with a through electrode made from a silicon wafer having a buried insulating layer between a supporting substrate layer and a silicon layer,
The support substrate layer is filled with a protective layer as a mask, penetrates the entire insulating layer thickness, reaches the silicon layer, and is formed to a depth where a recess is formed in the silicon layer. After forming the layer, the silicon layer is removed to expose a portion of the conductive layer corresponding to the recess as a protruding portion outside the wafer.   The SOI wafer in which the silicon oxide film is formed as an embedded insulating layer by forming a single crystal silicon layer on the surface of a silicon oxide film formed on one side of a support substrate layer is used as the silicon wafer. Item 3. A substrate with through electrodes according to item 1 or 2. A method of manufacturing a substrate with a through electrode using a silicon wafer having a buried insulating layer between a support substrate layer and a silicon layer,
Forming a protective layer for masking blind via holes on the surface of the support substrate layer;
Forming a blind via hole in the support substrate layer using the buried insulating layer as a stop layer;
Further etching the buried insulating layer at the bottom of the blind via hole reaching the buried insulating layer to form a blind via hole having a depth reaching the silicon layer through the entire buried insulating layer thickness;
Forming an insulating layer on the inner wall of the formed blind via hole;
Filling the blind via hole in which the inner wall insulating layer is formed with a metal for penetrating wiring to form a conductive layer;
And a step of exposing the conductive layer by removing the silicon layer. A method of manufacturing a substrate with a through electrode using a silicon wafer having a buried insulating layer between a support substrate layer and a silicon layer,
Forming a protective layer for masking blind via holes on the surface of the support substrate layer;
Forming a blind via hole in the support substrate layer using the buried insulating layer as a stop layer;
Further etching the buried insulating layer at the bottom of the blind via hole reaching the buried insulating layer to form a blind via hole having a depth reaching the silicon layer;
Further etching the bottom silicon layer of the blind via hole reaching the silicon layer to form a recess in the bottom silicon layer;
Forming an insulating layer on the inner wall of the formed blind via hole;
Filling the blind via hole in which the inner wall insulating layer is formed with a metal for penetrating wiring to form a conductive layer;
Removing the silicon layer and exposing a portion corresponding to the recess of the conductive layer as a protruding portion outside the wafer. An electronic device using the substrate with a through electrode according to claim 1, 2 or 3.

Images