JP2007258233A - Semiconductor device, manufacturing method thereof, and circuit board - Google Patents

Semiconductor device, manufacturing method thereof, and circuit board Download PDF

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JP2007258233A
JP2007258233A JP2006077124A JP2006077124A JP2007258233A JP 2007258233 A JP2007258233 A JP 2007258233A JP 2006077124 A JP2006077124 A JP 2006077124A JP 2006077124 A JP2006077124 A JP 2006077124A JP 2007258233 A JP2007258233 A JP 2007258233A
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hole
semiconductor substrate
depth
semiconductor device
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Toshiro Mihashi
敏郎 三橋
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Oki Electric Industry Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which uses laser work in a forming process of a through-electrode. <P>SOLUTION: An oxide film 11 is formed on a main face 101 of a semiconductor substrate 10. The oxide film 11 is removed by a laser beam, and holes 20 are formed on the main face of the semiconductor substrate 10. The holes 20 are worked with prescribed thickness. The rear face of the semiconductor substrate 10 is polished and the through-electrode is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置の製造方法、特にレーザ光により形成された貫通孔を含む半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a through hole formed by laser light.

従来、レーザ光により形成された貫通孔を含む半導体装置の製造方法として、次のようなものがある。第１に、シリコン基板のパターン形成面にレーザ光を照射して貫通孔を形成することにより、パターン形成面の熱損傷を防止する（例えば、特許文献１参照）。
第２に、半導体基板上の樹脂膜にレーザ光を照射しその樹脂膜のパターン形成を行う。そして、樹脂膜をドライエッチングにより加工しその樹脂膜に開口を形成する。このため、リソグラフィ工程でパターン形成を行う場合に比べて、パターン形成が簡素化する（例えば、特許文献２参照）。
特開２００３−１２４１５４号公報（段落０００５参照） 特開２００５−１５６９９９号公報（段落００１４~００２５参照） Conventionally, as a method for manufacturing a semiconductor device including a through-hole formed by a laser beam, there is the following method. First, the pattern formation surface of the silicon substrate is irradiated with laser light to form a through hole, thereby preventing thermal damage to the pattern formation surface (see, for example, Patent Document 1).
Second, the resin film on the semiconductor substrate is irradiated with laser light to form a pattern on the resin film. Then, the resin film is processed by dry etching to form an opening in the resin film. For this reason, compared with the case where pattern formation is performed in a lithography process, pattern formation is simplified (for example, refer patent document 2).
JP2003-124154A (see paragraph 0005) JP 2005-156999 A (see paragraphs 0014-0025)

しかしながら、上述の２つの方法では、レーザ加工をパターン形成の過程で用いるものの、貫通電極を形成する過程ではレーザ加工が用いられていなかった。そのため、貫通電極の形成過程でレーザ加工を活用することが望まれていた。   However, in the above-described two methods, although laser processing is used in the process of pattern formation, laser processing is not used in the process of forming the through electrode. Therefore, it has been desired to utilize laser processing in the formation process of the through electrode.

この発明の半導体装置の製造方法は、前述の課題を解決するために、半導体基板の第１面上に、第１絶縁膜を形成するステップと、第１絶縁膜をレーザ光により除去し、半導体基板の第１面に孔部を形成するステップとを含む。さらに、孔部をエッチングにより所定の深さまで加工するステップと、第１面とは異なる半導体基板の第２面を研磨し、孔部内に、第１面および第２面の間を貫通する貫通電極を形成するステップとを含む。
この発明の半導体装置の製造方法は、レーザ加工およびエッチング加工により、所定の深さの孔部を半導体基板の第１面に形成する。そして、半導体基板の第２面を研磨して孔部を貫通させ、その孔部内に貫通電極を形成する。 In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a first surface of a semiconductor substrate, and removing the first insulating film with a laser beam. Forming a hole in the first surface of the substrate. Furthermore, the step of processing the hole to a predetermined depth by etching, the second surface of the semiconductor substrate different from the first surface is polished, and the through electrode that penetrates between the first surface and the second surface in the hole Forming a step.
In the semiconductor device manufacturing method of the present invention, a hole having a predetermined depth is formed on the first surface of the semiconductor substrate by laser processing and etching processing. Then, the second surface of the semiconductor substrate is polished to penetrate the hole, and a through electrode is formed in the hole.

この発明によれば、半導体基板の第１面に形成した孔部をレーザ光およびエッチングにより加工した後、半導体基板の第２面を研磨して貫通電極を形成するため、貫通電極の形成過程でレーザ加工を活用する半導体装置の製造方法が得られる。   According to this invention, the hole formed in the first surface of the semiconductor substrate is processed by laser light and etching, and then the second surface of the semiconductor substrate is polished to form the through electrode. A semiconductor device manufacturing method utilizing laser processing can be obtained.

（実施の形態１）
本発明の実施の形態１を図１Ａないし図２に基づいて説明する。
図１Ａないし図１Ｆは、本発明の実施の形態１における半導体装置の製造工程を示す図である。図１Ａないし図１Ｆには、半導体チップが組み込まれた半導体基板１０を含む半導体装置の一部の断面が示されている。半導体基板として、例えば、厚さが３５０μｍ程度のシリコン基板を用いる。なお、半導体基板１０には、トランジスタやメモリなどの回路を含む集積回路が半導体チップに形成されているものとする。
まず、半導体基板１０上に酸化膜（第１絶縁膜）１１を形成する（図１Ａ）。酸化膜１１は、例えばＳｉＯ２とし、ＣＶＤ(Chemical Vapor Deposition)法により形成する。酸化膜１１は、例えば２μｍ程度の厚さを有する。なお、酸化膜１１は、例えばＳｉＮであってもよい。 (Embodiment 1)
Embodiment 1 of the present invention will be described with reference to FIGS. 1A to 2.
1A to 1F are views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 1A to 1F show a cross section of a part of a semiconductor device including a semiconductor substrate 10 in which a semiconductor chip is incorporated. For example, a silicon substrate having a thickness of about 350 μm is used as the semiconductor substrate. Note that an integrated circuit including a circuit such as a transistor or a memory is formed on a semiconductor chip on the semiconductor substrate 10.
First, an oxide film (first insulating film) 11 is formed on the semiconductor substrate 10 (FIG. 1A). The oxide film 11 is made of, for example, SiO 2 and is formed by a CVD (Chemical Vapor Deposition) method. The oxide film 11 has a thickness of about 2 μm, for example. The oxide film 11 may be SiN, for example.

続いて、半導体基板１０上の酸化膜１１をレーザ光１００により除去し、半導体基板１０の主面（第１面）１０１に孔部２０を形成する（図１Ｂ）。主面１０１は、集積回路が形成された面を指す。レーザは、例えば、炭酸ガスレーザ、ＹＡＧレーザ、エキシマレーザなどを用いる。
具体的には、レーザ光１００を酸化膜１１の一面に向けて照射した場合、その照射された酸化膜１１がレーザ光１００のエネルギーによって飛散し、孔部２０が形成される。そして、レーザ光１００をさらに酸化膜１１の一面に照射し続けると、孔部２０の深さが次第に深くなる。他方、飛散した酸化膜１１は、孔部２０の開口周辺に付着して堆積し、堆積物（レーザドロース）２１を形成する。 Subsequently, the oxide film 11 on the semiconductor substrate 10 is removed by the laser beam 100, and a hole 20 is formed in the main surface (first surface) 101 of the semiconductor substrate 10 (FIG. 1B). The main surface 101 indicates a surface on which an integrated circuit is formed. As the laser, for example, a carbon dioxide laser, a YAG laser, an excimer laser, or the like is used.
Specifically, when the laser beam 100 is irradiated toward one surface of the oxide film 11, the irradiated oxide film 11 is scattered by the energy of the laser beam 100, and the hole 20 is formed. When the laser beam 100 is further irradiated onto one surface of the oxide film 11, the depth of the hole 20 gradually increases. On the other hand, the scattered oxide film 11 adheres to and deposits around the opening of the hole 20 to form a deposit (laser drose) 21.

このようにして形成された孔部２０の開口は、例えば円形であり、その直径は４μｍ程度でかつ深さは２μｍ程度とする。孔部２０の深さは、後述のエッチングにより孔部２０を所定の深さまで深堀エッチングするので、酸化膜１１を除去する程度の深さとすることが好ましい。
なお、孔部２０の開口の形状、開口の直径および深さは、後述する貫通電極の形状に応じ変更してもよい。
図１Ｂでは、パッシベーション膜が記載されていないが、パッシベーション膜が酸化膜１１上に形成されている場合、レーザ光１００をパッシベーション膜の一面に向けて照射し、そのパッシベーション膜および酸化膜１１を除去して、孔部２０を形成する。パッシベーション膜は、例えば、ＳｉＯ２、ＳｉＮ、ポリイミド樹脂などの材料で形成される。 The opening of the hole 20 formed in this way is, for example, circular, and has a diameter of about 4 μm and a depth of about 2 μm. The depth of the hole 20 is preferably deep enough to remove the oxide film 11 because the hole 20 is deep-etched to a predetermined depth by etching described later.
In addition, you may change the shape of the opening of the hole part 20, the diameter of an opening, and the depth according to the shape of the penetration electrode mentioned later.
In FIG. 1B, the passivation film is not described, but when the passivation film is formed on the oxide film 11, the laser beam 100 is irradiated toward one surface of the passivation film to remove the passivation film and the oxide film 11. Thus, the hole 20 is formed. The passivation film is formed of a material such as SiO 2 , SiN, or polyimide resin.

次に、図１Ｂの孔部２０をエッチングにより所定の深さｔ１まで加工する（図１Ｃ）。この深さは、後述する図１Ｅの工程で半導体基板１０が裏面研磨される際に、孔部２０が貫通することを考慮して設定される。
具体的には、図１Ｃの酸化膜１１をマスクとして、孔部２０をドライエッチングすることにより、半導体基板１０を深堀エッチングし、深孔部２２を形成する。ドライエッチングに用いられるエッチングガスとしては、例えば六フッ化硫黄（ＳＦ６）を用いる。
深孔部２２は、例えば円柱形状であり、その深さｔ１が６０μｍで、直径が４μｍ程度とする。つまり、上述した所定の深さｔ１は、半導体基板１０の主面１０１から、６０μｍになる。なお、深さｔ１は、孔部２０（深孔部２２）が、半導体基板の裏面１０２から露出するのであれば、６０μｍ以上となるように設定してもよい。このようにしても、後述する貫通電極を形成することができるからである。 Next, the hole 20 in FIG. 1B is processed to a predetermined depth t1 by etching (FIG. 1C). This depth is set in consideration of penetration of the hole 20 when the semiconductor substrate 10 is polished on the back surface in the step of FIG. 1E described later.
Specifically, by using the oxide film 11 of FIG. 1C as a mask, the hole 20 is dry-etched to deep-etch the semiconductor substrate 10 to form the deep hole 22. As an etching gas used for dry etching, for example, sulfur hexafluoride (SF6) is used.
The deep hole portion 22 has, for example, a cylindrical shape, and has a depth t1 of 60 μm and a diameter of about 4 μm. That is, the predetermined depth t <b> 1 described above is 60 μm from the main surface 101 of the semiconductor substrate 10. The depth t1 may be set to be 60 μm or more if the hole 20 (deep hole 22) is exposed from the back surface 102 of the semiconductor substrate. This is because a through electrode described later can be formed even in this way.

このようにして孔部２０がドライエッチングされると、孔部２０直下にある半導体基板１０の主面１０１から、シリコン（Ｓｉ）部分をエッチングする。このとき、孔部２０直下では、孔部２０の開口が外側に広がるようにシリコン（Ｓｉ）部分がエッチングされ、サイドエッチ部２３が形成される。このため、サイドエッチ部２３の直径（開口の最も大きい部分）は、孔部２０の開口の直径（４μｍ程度）よりも大きくなる。
他方、上述したドライエッチングにより、堆積物２１（図１Ｂ参照）が除去されるという効果を得る。堆積物２１は、後工程において、半導体基板１０から剥離し異物となるので、上記ドライエッチングにより堆積物２１が除去でき、有益である。
なお、実施の形態１では、エッチングは、ドライエッチングの場合で説明したが、水酸化カリウム（ＫＯＨ）水溶液などのエッチング溶液を用いたウェットエッチングを適用してもよい。 When the hole 20 is dry-etched in this way, a silicon (Si) portion is etched from the main surface 101 of the semiconductor substrate 10 immediately below the hole 20. At this time, the silicon (Si) portion is etched immediately below the hole 20 so that the opening of the hole 20 spreads outward, so that the side etch portion 23 is formed. For this reason, the diameter of the side-etched portion 23 (the portion with the largest opening) is larger than the diameter of the opening of the hole portion 20 (about 4 μm).
On the other hand, the deposit 21 (see FIG. 1B) is removed by the dry etching described above. Since the deposit 21 is peeled off from the semiconductor substrate 10 and becomes a foreign substance in a subsequent process, the deposit 21 can be removed by the dry etching, which is beneficial.
Note that although etching is described in Embodiment 1 in the case of dry etching, wet etching using an etching solution such as a potassium hydroxide (KOH) aqueous solution may be applied.

次に、深孔部２２（図１Ｃ参照）内に、銅（Ｃｕ）などの導電材を充填し、導電部３０を形成する（図１Ｄ）。導電部３０は、銅などの金属メッキで形成されている。導電材として、アルミニウム、金、銀または白金を適用し、導電部３０は、それらの導電材からなる金属メッキで形成してもよい。本実施の形態では、導電部３０は、銅メッキにより形成されているものとする。   Next, the deep hole portion 22 (see FIG. 1C) is filled with a conductive material such as copper (Cu) to form the conductive portion 30 (FIG. 1D). The conductive portion 30 is formed by metal plating such as copper. Aluminum, gold, silver or platinum may be used as the conductive material, and the conductive portion 30 may be formed by metal plating made of those conductive materials. In the present embodiment, the conductive portion 30 is formed by copper plating.

次に、半導体基板１０の裏面（第２面）１０２を研磨し、導電部３０を半導体基板１０の両面（主面１０１および裏面１０２を意味。以下同じ）で貫通させる（図１Ｅ）。具体的には、半導体基板１０の裏面の研磨は、導電部３０の深さが、半導体基板１０の主面１０１から、６０μｍになるように行う。すなわち、孔部２０（図１Ｂ参照）の深さｔ２が、半導体基板１０の主面１０１から、５０μｍになるようにする。
なお、ここでの研磨は、研削を含む意味である。研削には、所定の粒度の砥石を使用したり、研磨には研磨布やスラリーなどを使用したりしてもよい。
このようにすることにより、孔部２０（図１Ｂ参照）内に形成された導電部３０が、半導体基板１０の両面を貫通する貫通電極として形成されることとなる。 Next, the back surface (second surface) 102 of the semiconductor substrate 10 is polished, and the conductive portion 30 is passed through both surfaces of the semiconductor substrate 10 (the main surface 101 and the back surface 102; the same applies hereinafter) (FIG. 1E). Specifically, the back surface of the semiconductor substrate 10 is polished so that the depth of the conductive portion 30 is 60 μm from the main surface 101 of the semiconductor substrate 10. That is, the depth t2 of the hole 20 (see FIG. 1B) is set to 50 μm from the main surface 101 of the semiconductor substrate 10.
Here, the term “polishing” includes grinding. For grinding, a grindstone having a predetermined particle size may be used, or for polishing, a polishing cloth or slurry may be used.
By doing in this way, the electroconductive part 30 formed in the hole part 20 (refer FIG. 1B) will be formed as a penetration electrode which penetrates both surfaces of the semiconductor substrate 10. FIG.

次に、貫通電極３０の２つの露出面（半導体基板１０の両面側）にバンプ３１をそれぞれ形成する（図１Ｆ）。バンプ３１は、円筒形状で、金などの金属で形成されているものとするが、これに限られない。例えば、バンプ３１は凸状であってもよい。なお、バンプ３１を形成する前には、不図示のパッドと集積回路との間の再配線が行われる。
このようにしてバンプ３１を形成することにより、貫通電極３０と半導体基板３１が導通することとなる。なお、図１Ｆにおいて、バンプ３１の直径と貫通電極３０の直径とは、導通性能などの点から、ほぼ同一にしておくことが好ましい。 Next, bumps 31 are respectively formed on the two exposed surfaces of the through electrode 30 (both sides of the semiconductor substrate 10) (FIG. 1F). The bump 31 has a cylindrical shape and is formed of a metal such as gold, but is not limited thereto. For example, the bump 31 may be convex. Note that before the bumps 31 are formed, rewiring between pads (not shown) and the integrated circuit is performed.
By forming the bumps 31 in this way, the through electrodes 30 and the semiconductor substrate 31 become conductive. In FIG. 1F, it is preferable that the diameter of the bump 31 and the diameter of the through electrode 30 are substantially the same from the viewpoint of conduction performance.

以上のように、実施の形態１における半導体装置は、半導体基板１０の主面１０１に孔部２０を形成した後、エッチングにより孔部２０を所定の深さまで加工する。そして、半導体基板１０の裏面１０２を研磨し、孔部２０内に、貫通電極３０を形成する。このため、レーザ加工を貫通電極の形成過程（図１Ａないし図１Ｆ参照）で活用することが可能となる。よって、リソグラフィ技術を用いずに、貫通電極３０を形成することが可能となり、リソグラフィ技術を用いる場合に比べて、半導体装置の工程を削減することが可能となる。また、レーザ加工を活用することにより、半導体装置の製造コストを軽減することが可能となる。   As described above, in the semiconductor device according to the first embodiment, after forming the hole 20 in the main surface 101 of the semiconductor substrate 10, the hole 20 is processed to a predetermined depth by etching. Then, the back surface 102 of the semiconductor substrate 10 is polished, and the through electrode 30 is formed in the hole 20. For this reason, it becomes possible to utilize laser processing in the formation process of a penetration electrode (refer to Drawing 1A thru / or Drawing 1F). Therefore, the through electrode 30 can be formed without using the lithography technique, and the number of steps of the semiconductor device can be reduced as compared with the case of using the lithography technique. Further, by utilizing laser processing, the manufacturing cost of the semiconductor device can be reduced.

次に、上述した図１Ａから図１Ｆに示した製造工程により得られた複数の半導体基板１０に組み込まれた半導体チップを積層した半導体装置について説明する。
図２は、複数の半導体チップを積層した半導体装置の一部の構成例を示した図である。
図２に示した半導体装置は、個片化した２つの半導体チップ１０（半導体基板の一部）を含み、これらの半導体チップ１０が対向して配置されている。そして、最下層に位置する半導体チップ１０（図２中の下位に位置するもの）は、その上部に形成されたバンプ３１を介して、最下層の上位に位置する半導体チップ１０（図２中の上位に位置するもの）と係合している。これにより、２つの半導体チップ１０の導通経路が確保される。このようにすることにより、複数の半導体チップ１０を積層した半導体装置を得ることも可能となる。 Next, a semiconductor device in which semiconductor chips incorporated in a plurality of semiconductor substrates 10 obtained by the manufacturing steps shown in FIGS. 1A to 1F described above are stacked will be described.
FIG. 2 is a diagram illustrating a configuration example of a part of a semiconductor device in which a plurality of semiconductor chips are stacked.
The semiconductor device shown in FIG. 2 includes two separated semiconductor chips 10 (a part of a semiconductor substrate), and these semiconductor chips 10 are arranged to face each other. Then, the semiconductor chip 10 located in the lowermost layer (the one located in the lower part in FIG. 2) is connected to the semiconductor chip 10 located in the uppermost part in the lowermost layer via bumps 31 formed in the upper part (in FIG. 2). Engaging with the upper one). Thereby, the conduction | electrical_connection path | route of the two semiconductor chips 10 is ensured. By doing so, it is also possible to obtain a semiconductor device in which a plurality of semiconductor chips 10 are stacked.

さらに、最上位に位置する半導体チップ１０には、その下部にバンプ３１が形成され、そのバンプ３１が、接続パット４１に接続されている。接続パッド４１は、回路基板４０に設けられている。回路基板４０は、例えば、ガラスエポキシ基板などの有機系基板を用いる。回路基板４０には、所定の回路が形成されている。例えば、回路基板４０は、マザーボードなどである。これにより、複数の半導体チップ１０を実装した回路基板４０を得ることが可能となる。
なお、図２では、２つの半導体チップ１０の一部が記載されているが、３つ以上の半導体チップ１０を積層するようにしてもよい。また、回路基板４０は、１つの半導体チップ１０を実装していてもよい。 Further, a bump 31 is formed in the lower part of the semiconductor chip 10 located at the uppermost position, and the bump 31 is connected to the connection pad 41. The connection pad 41 is provided on the circuit board 40. As the circuit board 40, for example, an organic substrate such as a glass epoxy substrate is used. A predetermined circuit is formed on the circuit board 40. For example, the circuit board 40 is a motherboard or the like. Thereby, it is possible to obtain the circuit board 40 on which the plurality of semiconductor chips 10 are mounted.
In FIG. 2, a part of the two semiconductor chips 10 is illustrated, but three or more semiconductor chips 10 may be stacked. The circuit board 40 may be mounted with one semiconductor chip 10.

（実施の形態２）
本発明の実施の形態２を図３Ａないし図３Ｆに基づいて説明する。なお、実施の形態１と同一の部分は、実施の形態１と同一の符号（用語を含む）を付して、適宜、重複説明を省略する。
図３Ａないし図３Ｆは、本発明の実施の形態２における半導体装置の製造工程を示す図である。図３Ａないし図３Ｆにも、半導体基板１０を含む半導体装置の一部の断面が示されている。ここでは、図１Ａおよび図１Ｂに示した製造工程を経て、半導体基板１０の主面１０１に孔部２０（図１Ｂ参照）が形成されているものとして、以下、説明する。
図３Ａでは、孔部２０（図１Ｂ参照）がエッチングにより第１の深さｔ３になるまで加工する。この深さｔ３は、上述した図１Ｃの工程でドライエッチングされる際に、サイドエッジ部２３（図１Ｃ参照）の深さよりも深くなるように設定される。
具体的には、図３Ａでは、図３Ｃの酸化膜１１をマスクとして、孔部２０（図１Ｂ参照）をドライエッチングすることにより、半導体基板１０を深堀エッチングし、深孔部２２Ａ（深さｔ３の孔部２０）を形成する。
深孔部２２Ａは、例えば円柱形状であり、その深さｔ３が２０μｍで、直径が４μｍ程度とする。これにより、孔部２０（図１Ｂ参照）の深さｔ１は、半導体基板１０の主面１０１から、２０μｍになる。なお、孔部２０の深さｔ３は、２０μｍ以上としてもよい。 (Embodiment 2)
A second embodiment of the present invention will be described with reference to FIGS. 3A to 3F. Note that the same parts as those in the first embodiment are denoted by the same reference numerals (including terms) as those in the first embodiment, and redundant description is appropriately omitted.
3A to 3F are views showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. 3A to 3F also show a cross section of a part of the semiconductor device including the semiconductor substrate 10. Here, the following description will be made on the assumption that the hole 20 (see FIG. 1B) is formed in the main surface 101 of the semiconductor substrate 10 through the manufacturing steps shown in FIGS. 1A and 1B.
In FIG. 3A, the hole 20 (see FIG. 1B) is processed by etching until the first depth t3 is reached. The depth t3 is set to be deeper than the depth of the side edge portion 23 (see FIG. 1C) when dry etching is performed in the above-described step of FIG. 1C.
Specifically, in FIG. 3A, by using the oxide film 11 of FIG. 3C as a mask, the hole 20 (see FIG. 1B) is dry-etched to deep-etch the semiconductor substrate 10 to obtain a deep hole 22A (depth t3). Hole 20).
The deep hole portion 22A has, for example, a cylindrical shape, and has a depth t3 of 20 μm and a diameter of about 4 μm. As a result, the depth t1 of the hole 20 (see FIG. 1B) is 20 μm from the main surface 101 of the semiconductor substrate 10. In addition, the depth t3 of the hole 20 may be 20 μm or more.

次に、半導体基板１０の主面１０１、絶縁膜１１および深孔部２２Ａのすべての表面を酸化膜（第２絶縁膜）１２で覆う（図３Ｂ）。酸化膜１２は、例えばＳｉＯ２とし、ＣＶＤ法により形成する。酸化膜１２は、例えば２μｍ程度の厚さを有する。なお、酸化膜１２は、例えばＳｉＮであってもよい。 Next, all surfaces of the main surface 101, the insulating film 11, and the deep hole portion 22A of the semiconductor substrate 10 are covered with an oxide film (second insulating film) 12 (FIG. 3B). The oxide film 12 is made of, for example, SiO 2 and is formed by a CVD method. The oxide film 12 has a thickness of about 2 μm, for example. The oxide film 12 may be SiN, for example.

次に、深孔部２２Ａの内壁面２２１に酸化膜１２を形成する（図３Ｃ）。具体的には、ドライエッチングにより、酸化膜１２を全面エッチバックする。これにより、酸化膜１２が深孔部２２Ａの内壁面２２１以外の表面に覆われていた酸化膜１２が取り除かれ、内壁面２２１にのみ酸化膜１２が形成される。
なお、図３Ｂにおいて、不図示のパッシベーション膜が酸化膜１１上に形成されている場合、酸化膜１２は、パッシベーション膜上に形成されることになるが、この場合も、上述した全面エッチバックにより、深孔部２２Ａの内壁面２２１にのみ酸化膜１２が形成される。 Next, the oxide film 12 is formed on the inner wall surface 221 of the deep hole portion 22A (FIG. 3C). Specifically, the entire oxide film 12 is etched back by dry etching. Thereby, the oxide film 12 covered with the surface other than the inner wall surface 221 of the deep hole portion 22A is removed, and the oxide film 12 is formed only on the inner wall surface 221.
In FIG. 3B, when a passivation film (not shown) is formed on the oxide film 11, the oxide film 12 is formed on the passivation film. The oxide film 12 is formed only on the inner wall surface 221 of the deep hole portion 22A.

次に、酸化膜１２を内壁面２２１に形成した深孔部２２Ａをエッチングし、深孔部２２Ａを深さｔ４（第２の深さ）まで加工する（図３Ｄ）。
具体的には、図３Ｄでは、図３Ｃの酸化膜１１をマスクとして、深孔部２２Ａをドライエッチングすることにより、半導体基板１０を深堀エッチングし、深さｔ４の深孔部２２Ａを形成する。
このドライエッチングの際、内壁面２２１には、酸化膜１２が形成されているので、この酸化膜１２が、内壁面２２１の保護膜の機能を果たし、内壁面２２１のシリコン（Ｓｉ）部分のエッチングを阻止する。したがって、深孔部２２Ａは、図１Ｃに示した深孔部２２の場合と異なり、サイドエッチ部２３（図１Ｃ参照）を形成しない。
図３Ｄに示した深孔部２２Ａは、例えば円柱形状となる。そして、深孔部２２Ａは、深さｔ４が６０μｍで、直径が４μｍ程度とする。なお、深さｔ４は、孔部２０（深孔部２２Ａ）が、半導体基板の裏面１０２から露出するのであれば、半導体基板１０の主面１０１から、６０μｍ以上となるように設定してもよい。
なお、図３Ｄにおいて、上述したドライエッチングにより、堆積物２１（図１Ｂ参照）が除去される点は、図１Ｃに示した実施の形態１の場合と同様である。 Next, the deep hole portion 22A in which the oxide film 12 is formed on the inner wall surface 221 is etched to process the deep hole portion 22A to a depth t4 (second depth) (FIG. 3D).
Specifically, in FIG. 3D, the deep hole portion 22A is dry-etched using the oxide film 11 of FIG. 3C as a mask to deep-etch the semiconductor substrate 10 to form a deep hole portion 22A having a depth t4.
At the time of this dry etching, the oxide film 12 is formed on the inner wall surface 221, so this oxide film 12 functions as a protective film for the inner wall surface 221 and etches the silicon (Si) portion of the inner wall surface 221. To prevent. Accordingly, the deep hole portion 22A does not form the side etch portion 23 (see FIG. 1C), unlike the case of the deep hole portion 22 shown in FIG. 1C.
The deep hole portion 22A illustrated in FIG. 3D has, for example, a cylindrical shape. The deep hole portion 22A has a depth t4 of 60 μm and a diameter of about 4 μm. The depth t4 may be set to be 60 μm or more from the main surface 101 of the semiconductor substrate 10 as long as the hole 20 (deep hole 22A) is exposed from the back surface 102 of the semiconductor substrate. .
In FIG. 3D, the point that the deposit 21 (see FIG. 1B) is removed by the dry etching described above is the same as in the case of the first embodiment shown in FIG. 1C.

次に、深孔部２２Ａ（図１Ｄ参照）内に、銅（Ｃｕ）などの導電材を充填し、導電部３０Ａを形成する（図３Ｅ）。導電部３０Ａは、銅などの金属メッキで形成されている。導電材としては、アルミニウム、金、銀または白金を適用し、導電部３０Ａは、それらの導電材からなる金属メッキで形成してもよい。本実施の形態では、導電部３０Ａは、銅メッキにより形成されているものとする。   Next, the deep hole portion 22A (see FIG. 1D) is filled with a conductive material such as copper (Cu) to form the conductive portion 30A (FIG. 3E). The conductive portion 30A is formed by metal plating such as copper. As the conductive material, aluminum, gold, silver, or platinum may be applied, and the conductive portion 30A may be formed by metal plating made of those conductive materials. In the present embodiment, it is assumed that conductive portion 30A is formed by copper plating.

次に、半導体基板１０の裏面１０２を研磨し、導電部３０Ａを半導体基板１０の両面で貫通させる（図３Ｅ）。具体的には、半導体基板１０の裏面１０２の研磨は、導電部３０Ａの深さが、半導体基板１０の主面１０１から、５０μｍになるように行う。すなわち、孔部２０（図１Ｂ参照）の深さｔ５が、半導体基板１０の主面１０１から、５０μｍになるようにする。
このようにして、半導体基板１０の両面を貫通する貫通電極３０Ａが、図１Ｅに示した実施の形態１の場合と同様に、形成される。このとき形成された貫通電極３０Ａも、深孔部２２Ａと同様、サイドエッチ部２３（図１Ｃ参照）を有しない形状となる。 Next, the back surface 102 of the semiconductor substrate 10 is polished, and the conductive portion 30A is penetrated on both surfaces of the semiconductor substrate 10 (FIG. 3E). Specifically, the back surface 102 of the semiconductor substrate 10 is polished so that the depth of the conductive portion 30 </ b> A is 50 μm from the main surface 101 of the semiconductor substrate 10. That is, the depth t5 of the hole 20 (see FIG. 1B) is set to 50 μm from the main surface 101 of the semiconductor substrate 10.
In this manner, the through electrode 30A penetrating both surfaces of the semiconductor substrate 10 is formed in the same manner as in the first embodiment shown in FIG. 1E. Similarly to the deep hole portion 22A, the through electrode 30A formed at this time also has a shape that does not have the side etch portion 23 (see FIG. 1C).

次に、貫通電極３０Ａの２つの露出面（半導体基板１０の両面側）にバンプ３１をそれぞれ形成する（図３Ｆ）。
なお、その後、図３Ａないし図３Ｆに示した製造工程により得られた複数の半導体基板１０に組み込まれた半導体チップを図２に示したように積層してもよい。 Next, bumps 31 are respectively formed on the two exposed surfaces (both sides of the semiconductor substrate 10) of the through electrode 30A (FIG. 3F).
Thereafter, the semiconductor chips incorporated in the plurality of semiconductor substrates 10 obtained by the manufacturing steps shown in FIGS. 3A to 3F may be stacked as shown in FIG.

以上のように、実施の形態２における半導体装置は、実施の形態１における半導体装置と比較すると、サイドエッチ部２３（図１Ｃ参照）を有しない形状の貫通電極を有する。これにより、実施の形態２における半導体装置は、例えばリフロー時において、サイドエッチの影響を受けた貫通電極の形状に起因するボイドの発生量を抑止することが可能となる。   As described above, the semiconductor device in the second embodiment has a through electrode having a shape that does not have the side-etched portion 23 (see FIG. 1C) as compared with the semiconductor device in the first embodiment. Thereby, the semiconductor device according to the second embodiment can suppress the amount of voids generated due to the shape of the through electrode affected by the side etch, for example, during reflow.

なお、本発明は、上記実施の形態に限られるものではなく、種々の変形が可能である。例えば、半導体基板は、ガリウム砒素（ＧａＡｓ）やＩｎＰなどの半導体基板を用いてもよい。   The present invention is not limited to the above embodiment, and various modifications can be made. For example, a semiconductor substrate such as gallium arsenide (GaAs) or InP may be used as the semiconductor substrate.

本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 本発明の実施の形態１を示す半導体装置の製造工程の一部を示す図。FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device showing the first embodiment of the present invention; 半導体基板を積層した半導体装置の構成図。1 is a configuration diagram of a semiconductor device in which semiconductor substrates are stacked. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention. 本発明の実施の形態２を示す半導体装置の製造工程の一部を示す図。The figure which shows a part of manufacturing process of the semiconductor device which shows Embodiment 2 of this invention.

符号の説明Explanation of symbols

１０ 半導体基板（半導体チップ）
１１、１２ 酸化膜
２０ 孔部
３０ 導電部（貫通電極）
３１ マスク 10 Semiconductor substrate (semiconductor chip)
11, 12 Oxide film 20 Hole 30 Conductive part (through electrode)
31 mask

Claims (10)

半導体基板の第１面上に、第１絶縁膜を形成するステップと、
前記第１絶縁膜をレーザ光により除去し、前記半導体基板の第１面に孔部を形成するステップと、
前記孔部をエッチングにより所定の深さまで加工するステップと、
前記第１面とは異なる前記半導体基板の第２面を研磨し、前記加工した孔部内に、前記第１面および前記第２面の間を貫通する貫通電極を形成するステップと、を含む、
半導体装置の製造方法。 Forming a first insulating film on the first surface of the semiconductor substrate;
Removing the first insulating film with a laser beam and forming a hole in the first surface of the semiconductor substrate;
Processing the hole to a predetermined depth by etching;
Polishing a second surface of the semiconductor substrate different from the first surface, and forming a through electrode penetrating between the first surface and the second surface in the processed hole.
A method for manufacturing a semiconductor device. 前記加工するステップは、
前記孔部を前記エッチングにより第１の深さまで加工するステップと、
前記第１の深さまで加工した前記孔部の内壁面に第２絶縁膜を形成するステップと、
前記第２絶縁膜を形成した前記孔部を前記エッチングにより、前記第１の深さよりも深い第２の深さまで加工するステップと、を含む、
請求項１に記載の半導体装置の製造方法。 The processing step includes
Processing the hole to a first depth by the etching;
Forming a second insulating film on the inner wall surface of the hole processed to the first depth;
Processing the hole in which the second insulating film is formed to the second depth deeper than the first depth by the etching.
A method for manufacturing a semiconductor device according to claim 1. 前記貫通電極を形成するステップは、前記第２面を研磨する前に、前記加工した孔部内に、前記貫通電極を形成する導電材を充填するステップ、を含む、
請求項１または請求項２に記載の半導体装置の製造方法。 The step of forming the through electrode includes a step of filling a conductive material for forming the through electrode into the processed hole before polishing the second surface.
A method for manufacturing a semiconductor device according to claim 1. 前記第１の深さまで加工した前記孔部は、前記内壁面を含む表面を有し、
前記第２絶縁膜を形成するステップは、
前記孔部の前記表面を前記第２絶縁膜で覆うステップと、
前記内壁部以外の前記表面に覆った前記第２絶縁膜を取り除くステップと、を含む、
請求項２に記載の半導体装置の製造方法。 The hole processed to the first depth has a surface including the inner wall surface;
Forming the second insulating film comprises:
Covering the surface of the hole with the second insulating film;
Removing the second insulating film covering the surface other than the inner wall portion,
A method for manufacturing a semiconductor device according to claim 2. 前記貫通電極を形成するステップでは、前記孔部が、少なくとも、前記半導体基板の前記第２面を貫通するまで当該第２面を研磨する、
請求項１または請求項２に記載の半導体装置の製造方法。 In the step of forming the through electrode, the second surface is polished until the hole penetrates at least the second surface of the semiconductor substrate.
A method for manufacturing a semiconductor device according to claim 1. 前記孔部を所定の深さまで加工するステップでは、前記孔部の深さが、前記半導体基板の前記第１面から６０μｍ以上になるように加工し、
前記貫通電極を形成するステップでは、前記孔部の深さが、前記半導体基板の第１面から５０μｍになるように前記半導体基板の第２面を研磨する、
請求項１に記載の半導体装置の製造方法。 In the step of processing the hole to a predetermined depth, the hole is processed so that the depth of the hole is 60 μm or more from the first surface of the semiconductor substrate,
In the step of forming the through electrode, the second surface of the semiconductor substrate is polished so that the depth of the hole is 50 μm from the first surface of the semiconductor substrate.
A method for manufacturing a semiconductor device according to claim 1. 前記孔部を前記第１の深さまで加工するステップでは、前記孔部の深さが、前記半導体基板の第１面から２０μｍになるように加工し、
前記第２の深さまで加工するステップでは、前記孔部の深さが、前記半導体基板の第１面から６０μｍ以上になるように加工し、
前記貫通電極を形成するステップでは、前記孔部の深さが、前記半導体基板の第１面から５０μｍになるように前記半導体基板の前記第２面を研磨する、
請求項２に記載の半導体装置の製造方法。 In the step of processing the hole to the first depth, the depth of the hole is processed to be 20 μm from the first surface of the semiconductor substrate,
In the step of processing to the second depth, processing is performed so that the depth of the hole is 60 μm or more from the first surface of the semiconductor substrate,
In the step of forming the through electrode, the second surface of the semiconductor substrate is polished so that the hole has a depth of 50 μm from the first surface of the semiconductor substrate.
A method for manufacturing a semiconductor device according to claim 2. 前記半導体基板を、前記貫通電極を備えた複数の半導体チップに個片化するステップと、
前記複数の半導体チップを積層するステップと、をさらに含む、
請求項１ないし請求項７のいずれか１項に記載の半導体装置の製造方法。 Dividing the semiconductor substrate into a plurality of semiconductor chips provided with the through electrodes;
Laminating the plurality of semiconductor chips, and
The method for manufacturing a semiconductor device according to claim 1. 請求項１ないし請求項８のいずれか１項に記載の半導体装置の製造方法により製造された半導体装置。   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. 請求項９に記載の半導体装置を含む回路基板。   A circuit board comprising the semiconductor device according to claim 9.
JP2006077124A 2006-03-20 2006-03-20 Semiconductor device, manufacturing method thereof, and circuit board Pending JP2007258233A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182734A (en) * 2009-02-03 2010-08-19 Seiko Epson Corp Semiconductor device, method of manufacturing the same, and electronic equipment
JP2014236131A (en) * 2013-06-03 2014-12-15 富士通株式会社 Semiconductor device and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63190360A (en) * 1987-02-03 1988-08-05 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JP2004335526A (en) * 2003-04-30 2004-11-25 Elpida Memory Inc Method of manufacturing semiconductor device
JP2005072489A (en) * 2003-08-27 2005-03-17 Sharp Corp Semiconductor-device and manufacturing method thereof
JP2005327813A (en) * 2004-05-12 2005-11-24 Seiko Epson Corp Semiconductor device and its manufacturing method, electro-optical device and its manufacturing method and electronic apparatus
JP2006013454A (en) * 2004-05-25 2006-01-12 Canon Inc Through-hole forming method, semiconductor device, and manufacturing method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63190360A (en) * 1987-02-03 1988-08-05 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JP2004335526A (en) * 2003-04-30 2004-11-25 Elpida Memory Inc Method of manufacturing semiconductor device
JP2005072489A (en) * 2003-08-27 2005-03-17 Sharp Corp Semiconductor-device and manufacturing method thereof
JP2005327813A (en) * 2004-05-12 2005-11-24 Seiko Epson Corp Semiconductor device and its manufacturing method, electro-optical device and its manufacturing method and electronic apparatus
JP2006013454A (en) * 2004-05-25 2006-01-12 Canon Inc Through-hole forming method, semiconductor device, and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182734A (en) * 2009-02-03 2010-08-19 Seiko Epson Corp Semiconductor device, method of manufacturing the same, and electronic equipment
JP2014236131A (en) * 2013-06-03 2014-12-15 富士通株式会社 Semiconductor device and method of manufacturing the same

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