JP2014236131A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2014236131A
JP2014236131A JP2013117307A JP2013117307A JP2014236131A JP 2014236131 A JP2014236131 A JP 2014236131A JP 2013117307 A JP2013117307 A JP 2013117307A JP 2013117307 A JP2013117307 A JP 2013117307A JP 2014236131 A JP2014236131 A JP 2014236131A
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electrode
semiconductor substrate
insulating film
insulator
recess
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JP6146144B2 (en
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赤松　俊也
Toshiya Akamatsu
俊也 赤松
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent warpage of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a through electrode 12 in a hole that is formed toward a second surface from a first surface 72 of a semiconductor substrate 10 and not reaching the second surface 70; forming an insulating film 20 having an opening 22 on the second surface of the semiconductor substrate; forming a recess 24 surrounding the through electrode so as to expose an upper surface of the through electrode by removing the semiconductor substrate using the insulating film as a mask; and forming an insulator 26 embedded in the recess so as to expose the upper surface of the through electrode.

Description

本発明は、半導体装置およびその製造方法に関し、例えば半導体基板を貫通する貫通電極を有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a through electrode penetrating a semiconductor substrate and a manufacturing method thereof.

半導体チップを積層実装するため、半導体基板を貫通する貫通電極（例えばＴＳＶ：Through Silicon Via）を形成することが知られている。貫通電極と貫通孔の間に絶縁膜を形成することが知られている（例えば特許文献１）。   In order to stack and mount semiconductor chips, it is known to form through electrodes (for example, TSV: Through Silicon Via) penetrating a semiconductor substrate. It is known to form an insulating film between a through electrode and a through hole (for example, Patent Document 1).

特開２０１１−８２２９１号公報JP 2011-82291 A

しかしながら、貫通電極を形成した半導体基板の上面に形成された絶縁膜により、半導体基板が反ってしまうことがある。本半導体装置およびその製造方法は、半導体基板の反りを抑制することを特徴とする。   However, the semiconductor substrate may be warped by the insulating film formed on the upper surface of the semiconductor substrate on which the through electrode is formed. The semiconductor device and the manufacturing method thereof are characterized by suppressing warpage of the semiconductor substrate.

半導体基板の第１面から第２面に向けて形成され、前記第１面まで達していない穴内に貫通電極を形成する工程と、前記半導体基板の前記第２面上に開口を有する絶縁膜を形成する工程と、前記絶縁膜をマスクに前記半導体基板を除去することにより、前記貫通電極の上面が露出するように前記貫通電極を囲む凹部を形成する工程と、前記凹部内に前記貫通電極の上面が露出するように埋め込まれた絶縁体を形成する工程と、を含むことを特徴とする半導体装置の製造方法を用いる。   Forming a through electrode in a hole formed from the first surface of the semiconductor substrate toward the second surface and not reaching the first surface; and an insulating film having an opening on the second surface of the semiconductor substrate. Forming a recess surrounding the through electrode so that an upper surface of the through electrode is exposed by removing the semiconductor substrate using the insulating film as a mask, and forming the through electrode in the recess. Forming a buried insulator so that the upper surface is exposed. A method for manufacturing a semiconductor device is used.

半導体基板と、半導体基板を貫通する貫通電極と、前記半導体基板の表面上に形成された絶縁膜と、前記半導体基板の前記表面に前記貫通電極を囲むように形成された凹部内に前記貫通電極が露出するように埋め込まれた前記絶縁膜とは異なる絶縁体と、を具備することを特徴とする半導体装置を用いる。   A semiconductor substrate; a through electrode penetrating the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and the through electrode in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode. A semiconductor device comprising: an insulator different from the insulating film embedded so as to be exposed.

本半導体装置およびその製造方法によれば、半導体基板の反りを抑制することができる。   According to the present semiconductor device and the manufacturing method thereof, warping of the semiconductor substrate can be suppressed.

図１（ａ）から図１（ｅ）は、比較例１に係る半導体装置の製造方法を示す断面図であるFIG. 1A to FIG. 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. 図２は、比較例１における課題を説明する図である。FIG. 2 is a diagram illustrating a problem in the first comparative example. 図３（ａ）から図３（ｄ）は、比較例２に係る半導体装置の製造方法を示す断面図である。FIG. 3A to FIG. 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. 図４（ａ）および図４（ｂ）は、比較例２における課題を説明する図である。FIG. 4A and FIG. 4B are diagrams for explaining the problem in the second comparative example. 図５（ａ）から図５（ｅ）は、実施例１に係る半導体装置の製造方法を示す断面図である。FIG. 5A to FIG. 5E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. 図６は、実施例１に係る半導体装置の製造方法を示す平面図である。FIG. 6 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図７（ａ）および図７（ｂ）は、半導体基板のエッチングを示す断面図である。FIGS. 7A and 7B are cross-sectional views showing the etching of the semiconductor substrate. 図８（ａ）から図８（ｅ）は、実施例２に係る半導体装置の製造方法を示す断面図（その１）である。8A to 8E are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図９（ａ）から図９（ｄ）は、実施例２に係る半導体装置の製造方法を示す断面図（その２）である。FIG. 9A to FIG. 9D are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１０（ａ）から図１０（ｄ）は、実施例２に係る半導体装置の製造方法を示す断面図（その３）である。FIG. 10A to FIG. 10D are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１１（ａ）および図１１（ｂ）は、実施例２に係る半導体装置の製造方法を示す断面図（その４）である。FIG. 11A and FIG. 11B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１２（ａ）および図１２（ｂ）は、実施例２に係る半導体装置の製造方法を示す断面図（その５）である。12A and 12B are cross-sectional views (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１３（ａ）および図１３（ｂ）は、実施例２に係る半導体装置の製造方法を示す断面図（その６）である。FIG. 13A and FIG. 13B are cross-sectional views (part 6) illustrating the method for manufacturing the semiconductor device according to the second embodiment.

図１（ａ）から図１（ｅ）は、比較例１に係る半導体装置の製造方法を示す断面図である。図１（ａ）を参照し、半導体基板１０の第１面７２上に電極１４、金属端子１６および半田１８が形成されている。第１面７２から第２面７０にかけて貫通電極１２が形成されている。貫通電極１２は、半導体基板１０を貫通していない。   FIG. 1A to FIG. 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. With reference to FIG. 1A, the electrode 14, the metal terminal 16, and the solder 18 are formed on the first surface 72 of the semiconductor substrate 10. The through electrode 12 is formed from the first surface 72 to the second surface 70. The through electrode 12 does not penetrate the semiconductor substrate 10.

図１（ｂ）を参照し、半導体基板１０の第２面７０を研削または研磨し、貫通電極１２を露出させる。図１（ｃ）を参照し、半導体基板１０の第２面７０上に貫通電極１２を覆うように絶縁体５０を形成する。図１（ｄ）を参照し、絶縁体５０に開口５２を形成する。開口５２を介し貫通電極１２が露出する。図１（ｅ）を参照し、絶縁体５０上に開口５２を介し貫通電極１２に接続する端子５４を形成する。   Referring to FIG. 1B, the second surface 70 of the semiconductor substrate 10 is ground or polished to expose the through electrode 12. With reference to FIG. 1C, an insulator 50 is formed on the second surface 70 of the semiconductor substrate 10 so as to cover the through electrode 12. With reference to FIG. 1D, an opening 52 is formed in the insulator 50. The through electrode 12 is exposed through the opening 52. Referring to FIG. 1 (e), a terminal 54 connected to the through electrode 12 through the opening 52 is formed on the insulator 50.

図２は、比較例１における課題を説明する図である。図２を参照し、絶縁体５０の内部応力が大きい場合、半導体基板１０が薄くなると、矢印５６のように半導体基板１０の反りが大きくなる。絶縁体５０が樹脂の場合、内部応力が大きく半導体基板１０が反り易い。   FIG. 2 is a diagram illustrating a problem in the first comparative example. Referring to FIG. 2, when the internal stress of the insulator 50 is large, when the semiconductor substrate 10 becomes thin, the warp of the semiconductor substrate 10 increases as indicated by an arrow 56. When the insulator 50 is resin, the internal stress is large and the semiconductor substrate 10 is likely to warp.

図３（ａ）から図３（ｄ）は、比較例２に係る半導体装置の製造方法を示す断面図である。図３（ａ）を参照し、図１（ａ）と同様に、半導体基板１０に貫通電極１２を形成する。図３（ｂ）を参照し、半導体基板１０の第２面７０を比較例１の図１（ｂ）より多く研削または研磨する。図３（ｃ）を参照し、半導体基板１０の第２面７０上に貫通電極１２を覆うように絶縁体５０を形成する。図３（ｄ）を参照し、絶縁体５０をエッチングすることにより、貫通電極１２を露出させる。   FIG. 3A to FIG. 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. Referring to FIG. 3A, the through electrode 12 is formed in the semiconductor substrate 10 as in FIG. Referring to FIG. 3B, the second surface 70 of the semiconductor substrate 10 is ground or polished more than in FIG. With reference to FIG. 3C, the insulator 50 is formed on the second surface 70 of the semiconductor substrate 10 so as to cover the through electrode 12. With reference to FIG. 3D, the through electrode 12 is exposed by etching the insulator 50.

図４（ａ）および図４（ｂ）は、比較例２における課題を説明する図である。図４（ａ）を参照し、図３（ｄ）において、絶縁体５０の表面全体を矢印６２のようにドライエッチングする。図４（ｂ）を参照し、エッチング量が大きすぎると、領域６４のように、絶縁体５０の膜厚が薄くなる、または、半導体基板１０が露出してしまう。これにより、絶縁体５０が半導体基板１０の保護膜として機能しなくなってしまう。   FIG. 4A and FIG. 4B are diagrams for explaining the problem in the second comparative example. Referring to FIG. 4A, in FIG. 3D, the entire surface of the insulator 50 is dry-etched as indicated by an arrow 62. Referring to FIG. 4B, if the etching amount is too large, the insulator 50 becomes thin like the region 64 or the semiconductor substrate 10 is exposed. As a result, the insulator 50 does not function as a protective film for the semiconductor substrate 10.

図５（ａ）から図５（ｅ）は、実施例１に係る半導体装置の製造方法を示す断面図である。図６は、実施例１に係る半導体装置の製造方法を示す平面図である。図５（ａ）を参照し、図１（ａ）と同じように、例えばシリコン基板等の半導体基板１０の第１面７２上に電極１４、金属端子１６および半田１８を形成する。電極１４は、Ａｌ（アルミニウム）またはＣｕ（銅）等の金属を主に含む。金属端子１６は、Ｃｕ等の金属を主に含む。半田は、Ｓｎ−Ａｇ、Ｓｎ−Ｂｉ、Ｓｎ−Ａｇ−Ｃｕ等を主に含む。貫通電極１２が第１面７２から第２面７０に向けて形成されている。貫通電極１２は半導体基板１０を貫通していない。貫通電極１２は、Ｃｕ等の金属を主に含む。第２面７０上に絶縁膜２０を形成する。絶縁膜２０は、酸化シリコンまたは窒化シリコン等の無機絶縁体を主に含む。   FIG. 5A to FIG. 5E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment. Referring to FIG. 5A, as in FIG. 1A, the electrode 14, the metal terminal 16, and the solder 18 are formed on the first surface 72 of the semiconductor substrate 10 such as a silicon substrate. The electrode 14 mainly contains a metal such as Al (aluminum) or Cu (copper). The metal terminal 16 mainly contains a metal such as Cu. The solder mainly contains Sn—Ag, Sn—Bi, Sn—Ag—Cu, and the like. The through electrode 12 is formed from the first surface 72 toward the second surface 70. The through electrode 12 does not penetrate the semiconductor substrate 10. The through electrode 12 mainly contains a metal such as Cu. The insulating film 20 is formed on the second surface 70. The insulating film 20 mainly contains an inorganic insulator such as silicon oxide or silicon nitride.

図５（ｂ）を参照し、フォトリソグラフィ法およびエッチング法を用い絶縁膜２０に開口２２を形成する。開口２２は、上から視て貫通電極１２より大きく、貫通電極１２を含むように形成する。絶縁膜２０が酸化シリコンを主に含む場合、絶縁膜２０のエッチングには、例えばフッ酸系のウェットエッチングを用いる。絶縁膜２０が窒化シリコンを主に含む場合、絶縁膜２０のエッチングには、例えばドライエッチングを用いる。図５（ｃ）を参照し、絶縁膜２０をマスクに、半導体基板１０をエッチングし、凹部２４を形成する。凹部２４は開口２２により画定されている。半導体基板１０のエッチングは、例えば異方性エッチングを用いる。凹部２４により、貫通電極１２の先端が露出する。   Referring to FIG. 5B, an opening 22 is formed in the insulating film 20 using a photolithography method and an etching method. The opening 22 is larger than the through electrode 12 when viewed from above, and is formed so as to include the through electrode 12. When the insulating film 20 mainly contains silicon oxide, for example, hydrofluoric acid-based wet etching is used for etching the insulating film 20. When the insulating film 20 mainly contains silicon nitride, for example, dry etching is used for etching the insulating film 20. With reference to FIG. 5C, the semiconductor substrate 10 is etched using the insulating film 20 as a mask to form the recess 24. The recess 24 is defined by the opening 22. For example, anisotropic etching is used for etching the semiconductor substrate 10. The tip of the through electrode 12 is exposed by the recess 24.

図５（ｄ）を参照し、凹部２４に充填されるように、半導体基板１０の第２面７０上に絶縁体層２５を形成する。絶縁体層２５は、例えばエポキシ樹脂またはポリイミド樹脂等の樹脂を主に含む。貫通電極１２の先端は絶縁体層２５により覆われる。   With reference to FIG. 5D, the insulator layer 25 is formed on the second surface 70 of the semiconductor substrate 10 so as to fill the recess 24. The insulator layer 25 mainly includes a resin such as an epoxy resin or a polyimide resin. The tip of the through electrode 12 is covered with an insulator layer 25.

図５（ｅ）および図６を参照し、図５（ｅ）は図６のＡ−Ａ断面を示す。絶縁体層２５を全面エッチングする。絶縁体層２５が絶縁膜２０に対し選択的にエッチングされるように、エッチャントおよび条件を選択する。例えばＡｒ（アルゴン）またはＡｒとＯ２の混合ガスを用いたドライエッチングを用いる。これにより、半導体基板１０の第２面７０上の絶縁膜２０はほとんどエッチングされず、絶縁体層２５がエッチングされる。絶縁体層２５から絶縁体２６が形成される。よって、半導体基板１０の第２面７０が絶縁膜２０に覆われた状態で貫通電極１２の先端が絶縁体２６から露出する。貫通電極１２の先端が絶縁膜２０より低く、絶縁膜２０および絶縁体２６から形成される窪みの底に貫通電極１２が露出する。このように、半導体基板１０は第１面７２に露出しない。 5 (e) and 6 are referred to, and FIG. 5 (e) shows an AA cross section of FIG. The entire surface of the insulator layer 25 is etched. Etchant and conditions are selected so that the insulator layer 25 is selectively etched with respect to the insulating film 20. For example, dry etching using Ar (argon) or a mixed gas of Ar and O 2 is used. Thereby, the insulating film 20 on the second surface 70 of the semiconductor substrate 10 is hardly etched, and the insulator layer 25 is etched. An insulator 26 is formed from the insulator layer 25. Therefore, the tip of the through electrode 12 is exposed from the insulator 26 in a state where the second surface 70 of the semiconductor substrate 10 is covered with the insulating film 20. The tip of the through electrode 12 is lower than the insulating film 20, and the through electrode 12 is exposed at the bottom of the recess formed from the insulating film 20 and the insulator 26. As described above, the semiconductor substrate 10 is not exposed to the first surface 72.

図７（ａ）および図７（ｂ）は、半導体基板のエッチングを示す断面図である。図７（ａ）を参照し、図５（ｃ）のエッチングの例について説明する。単結晶シリコンには、腐食作用が結晶方向に沿って進む性質がある。このため、エッチング液の選択により、異方性エッチングを行なうことができる。これにより凹部２４を形成できる。また、シリコン基板には（１００）または（１１０）基板があり、基板の方位およびエッチング液を選択することで凹部２４の形状等を制御できる。   FIGS. 7A and 7B are cross-sectional views showing the etching of the semiconductor substrate. With reference to FIG. 7A, an example of etching in FIG. 5C will be described. Single crystal silicon has the property that the corrosive action proceeds along the crystal direction. For this reason, anisotropic etching can be performed by selecting an etching solution. Thereby, the recessed part 24 can be formed. Further, the silicon substrate includes a (100) or (110) substrate, and the shape and the like of the recess 24 can be controlled by selecting the orientation of the substrate and the etching solution.

図７（ａ）において、半導体基板１０として、（１００）面が主面の単結晶シリコン基板を用いる。エッチング液としてＫＯＨ等のアルカリ系エッチング液を用いる。上方向が＜１００＞方向であり、奥行き方向が＜１１０＞方向である。（１００）面からエッチングすると、（１１１）面がエッチングされにくくなる。このため（１１１）面によりエッチングが停止する。（１１１）面と（１００）面とのなす角度θは、５４．７°である。   In FIG. 7A, a single crystal silicon substrate having a (100) plane as a main surface is used as the semiconductor substrate 10. An alkaline etching solution such as KOH is used as the etching solution. The upward direction is the <100> direction, and the depth direction is the <110> direction. Etching from the (100) plane makes it difficult to etch the (111) plane. For this reason, the etching is stopped by the (111) plane. The angle θ formed by the (111) plane and the (100) plane is 54.7 °.

図７（ｂ）を参照し、実施例１における寸法の例を説明する。上図は、凹部２４の上面図、下図は断面図である。貫通電極１２の直径Ｌ１が１０μｍ、貫通電極１２のピッチＬ２が５０μｍである。貫通電極１２の側面の半導体基板１０の第２面７０から深さＤ１までが凹部２４に露出する場合、貫通電極１２と凹部２４の間隔Ｌ４は、３．５μｍ程度あれば、十分である。このため、凹部２４の幅Ｌ３は、１７μｍとなる。このように、異方性エッチングにより、凹部２４を形成することにより、凹部２４を精度よく形成することができる。   With reference to FIG.7 (b), the example of the dimension in Example 1 is demonstrated. The upper view is a top view of the recess 24, and the lower view is a cross-sectional view. The diameter L1 of the through electrode 12 is 10 μm, and the pitch L2 of the through electrode 12 is 50 μm. When the side surface of the through electrode 12 from the second surface 70 of the semiconductor substrate 10 to the depth D1 is exposed in the recess 24, it is sufficient that the distance L4 between the through electrode 12 and the recess 24 is about 3.5 μm. For this reason, the width L3 of the recess 24 is 17 μm. As described above, by forming the recess 24 by anisotropic etching, the recess 24 can be formed with high accuracy.

実施例１によれば、図５（ａ）のように、半導体基板１０の第１面７２から第２面７０に向けて形成され、第２面７０まで達していない穴内に貫通電極を形成する。図５（ｂ）のように、半導体基板１０の第２面７０上に開口２２を有する絶縁膜２０を形成する。図５（ｃ）のように、絶縁膜２０をマスクに半導体基板１０を除去することにより、貫通電極１２の上面が露出するように貫通電極１２を囲む凹部２４を形成する。図５（ｄ）および図５（ｅ）のように、凹部２４内に貫通電極１２の上面が露出するように埋め込まれた絶縁体２６を形成する。以上により、図５（ｅ）および図６のように、半導体基板１０の第２面７０上に絶縁膜２０が形成される。また、半導体基板１０の第２面７０に貫通電極１２を囲むように形成された凹部２４内に貫通電極１２が露出するように埋め込まれた絶縁体２６が形成される。   According to the first embodiment, as shown in FIG. 5A, the through electrode is formed in the hole formed from the first surface 72 of the semiconductor substrate 10 toward the second surface 70 and not reaching the second surface 70. . As shown in FIG. 5B, the insulating film 20 having the opening 22 is formed on the second surface 70 of the semiconductor substrate 10. As shown in FIG. 5C, by removing the semiconductor substrate 10 using the insulating film 20 as a mask, a recess 24 surrounding the through electrode 12 is formed so that the upper surface of the through electrode 12 is exposed. As shown in FIGS. 5D and 5E, the insulator 26 embedded in the recess 24 so as to expose the upper surface of the through electrode 12 is formed. Thus, the insulating film 20 is formed on the second surface 70 of the semiconductor substrate 10 as shown in FIGS. In addition, an insulator 26 embedded in the second surface 70 of the semiconductor substrate 10 so as to expose the through electrode 12 is formed in a recess 24 formed so as to surround the through electrode 12.

エッチング選択性を得るために、絶縁膜２０と絶縁体２６とは異なる材料である。例えば、絶縁膜２０の内部応力を絶縁体２６の内部応力より小さくする。これにより、図２のような半導体基板１０の反りを抑制できる。例えば、絶縁膜２０を無機絶縁膜とし、絶縁体２６を樹脂絶縁体とすることにより、絶縁膜２０の内部応力を絶縁体２６より小さくできる。また、絶縁膜２０および絶縁体２６が半導体基板１０の第２面７０を覆っているため、図４（ｂ）のような、第２面７０における半導体基板１０の露出を抑制できる。   In order to obtain etching selectivity, the insulating film 20 and the insulator 26 are different materials. For example, the internal stress of the insulating film 20 is made smaller than the internal stress of the insulator 26. Thereby, the curvature of the semiconductor substrate 10 as shown in FIG. 2 can be suppressed. For example, when the insulating film 20 is an inorganic insulating film and the insulator 26 is a resin insulator, the internal stress of the insulating film 20 can be made smaller than that of the insulator 26. Moreover, since the insulating film 20 and the insulator 26 cover the second surface 70 of the semiconductor substrate 10, the exposure of the semiconductor substrate 10 on the second surface 70 as shown in FIG. 4B can be suppressed.

絶縁体２６を形成する際には、図５（ｄ）のように、凹部２４内、絶縁膜２０上および貫通電極１２上に絶縁体層２５を形成する。図５（ｅ）のように、絶縁体層２５を絶縁膜２０および貫通電極１２に対し選択的にエッチングする。これにより、絶縁体２６を形成することができる。   When forming the insulator 26, as shown in FIG. 5D, the insulator layer 25 is formed in the recess 24, on the insulating film 20 and on the through electrode 12. As shown in FIG. 5E, the insulator layer 25 is selectively etched with respect to the insulating film 20 and the through electrode 12. Thereby, the insulator 26 can be formed.

図８（ａ）から図１３（ｂ）は、実施例２に係る半導体装置の製造方法を示す断面図である。図８（ａ）を参照し、半導体基板１０の第１面７２に電子回路３２を形成する。半導体基板１０上に絶縁膜３０を形成する。電子回路３２は、半導体基板１０に形成されたトランジスタおよび絶縁膜３０内に形成された配線を含む。絶縁膜３０は例えば酸化シリコン膜であり、多層配線の層間絶縁膜を含む。   8A to 13B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. With reference to FIG. 8A, the electronic circuit 32 is formed on the first surface 72 of the semiconductor substrate 10. An insulating film 30 is formed on the semiconductor substrate 10. The electronic circuit 32 includes a transistor formed in the semiconductor substrate 10 and a wiring formed in the insulating film 30. The insulating film 30 is a silicon oxide film, for example, and includes an interlayer insulating film of multilayer wiring.

図８（ｂ）を参照し、第１面７２から絶縁膜３０および半導体基板１０に穴４８を形成する。穴４８の深さは、例えば５０μｍよりやや浅い。図８（ｃ）を参照し、穴４８内に貫通電極１２を形成する。貫通電極１２は、例えばＣｕを主に含み、めっき法を用い形成する。図８（ｄ）を参照し、絶縁膜３０および貫通電極１２上に絶縁膜３６を形成する。絶縁膜３６および３０内に配線３４を形成する。絶縁膜３６は、例えば酸化シリコン膜または樹脂膜であり、電子回路３２の保護膜である。配線３４は、例えばＡｌまたはＣｕを主に含む金属である。図８（ｅ）を参照し、絶縁膜３６上に、電極１４、金属端子１６および半田１８を形成する。   With reference to FIG. 8B, holes 48 are formed in the insulating film 30 and the semiconductor substrate 10 from the first surface 72. The depth of the hole 48 is slightly shallower than 50 μm, for example. With reference to FIG. 8C, the through electrode 12 is formed in the hole 48. The through electrode 12 mainly contains Cu, for example, and is formed using a plating method. With reference to FIG. 8D, an insulating film 36 is formed on the insulating film 30 and the through electrode 12. A wiring 34 is formed in the insulating films 36 and 30. The insulating film 36 is, for example, a silicon oxide film or a resin film, and is a protective film for the electronic circuit 32. The wiring 34 is a metal mainly containing, for example, Al or Cu. With reference to FIG. 8E, the electrode 14, the metal terminal 16, and the solder 18 are formed on the insulating film 36.

図９（ａ）を参照し、半導体基板１０の第１面７２側を接着剤３７を介し支持基板３８に貼り付ける。支持基板３８は例えばシリコン基板である。図９（ｂ）を参照し、半導体基板１０の第２面７０を研磨または研削する。半導体基板１０の膜厚を例えば５０μｍとする。貫通電極１２は、半導体基板１０を貫通していない。図９（ｃ）を参照し、半導体基板１０の第２面７０上に絶縁膜２０を形成する。図９（ｄ）を参照し、絶縁膜２０に開口２２を形成する。   With reference to FIG. 9A, the first surface 72 side of the semiconductor substrate 10 is attached to the support substrate 38 via the adhesive 37. The support substrate 38 is a silicon substrate, for example. Referring to FIG. 9B, the second surface 70 of the semiconductor substrate 10 is polished or ground. The film thickness of the semiconductor substrate 10 is 50 μm, for example. The through electrode 12 does not penetrate the semiconductor substrate 10. With reference to FIG. 9C, the insulating film 20 is formed on the second surface 70 of the semiconductor substrate 10. With reference to FIG. 9D, an opening 22 is formed in the insulating film 20.

図１０（ａ）を参照し、絶縁膜２０をマスクに半導体基板１０に凹部２４を形成する。図１０（ｂ）を参照し、絶縁膜２０上に絶縁体層２５を形成する。図１０（ｃ）を参照し、絶縁体層２５を選択的にエッチングし、貫通電極１２の先端を露出させる。図１０（ｄ）を参照し、接着剤３７を溶解させ、支持基板３８を半導体基板１０から剥離する。以上により半導体チップ８０が完成する。   Referring to FIG. 10A, a recess 24 is formed in the semiconductor substrate 10 using the insulating film 20 as a mask. With reference to FIG. 10B, an insulating layer 25 is formed on the insulating film 20. Referring to FIG. 10C, the insulator layer 25 is selectively etched to expose the tip of the through electrode 12. Referring to FIG. 10 (d), the adhesive 37 is dissolved, and the support substrate 38 is peeled from the semiconductor substrate 10. Thus, the semiconductor chip 80 is completed.

図１１（ａ）を参照し、配線基板８２を準備する。配線基板８２は、絶縁基板８４の下面に電極８６が形成され、上面に電極９２が形成されている。絶縁基板８４内には配線９０が形成され、電極８６と９２とが配線９０により電気的に接続されている。電極９２上には半田９４が形成されている。絶縁基板８４は例えば樹脂基板である。配線９０、電極８６および９２は、例えばＣｕ等の金属を含む。半導体チップ８０はボンダヘッド４０により支持されている。半導体チップ８０ａの第１面７２が絶縁基板８４の上面に配置される。半導体チップ８０ａは図１０（ｄ）の半導体チップ８０と同じであり説明を省略する。図１１（ｂ）を参照し、位置合わせをし、半導体チップ８０と配線基板８２を接触させる。半田１８と半田９４とが接触する。加熱することにより、半田１８と９４とが接合する。   Referring to FIG. 11A, a wiring board 82 is prepared. The wiring substrate 82 has an electrode 86 formed on the lower surface of the insulating substrate 84 and an electrode 92 formed on the upper surface. A wiring 90 is formed in the insulating substrate 84, and the electrodes 86 and 92 are electrically connected by the wiring 90. Solder 94 is formed on the electrode 92. The insulating substrate 84 is, for example, a resin substrate. The wiring 90 and the electrodes 86 and 92 include a metal such as Cu, for example. The semiconductor chip 80 is supported by the bonder head 40. The first surface 72 of the semiconductor chip 80 a is disposed on the upper surface of the insulating substrate 84. The semiconductor chip 80a is the same as the semiconductor chip 80 in FIG. Referring to FIG. 11B, alignment is performed, and the semiconductor chip 80 and the wiring board 82 are brought into contact with each other. The solder 18 and the solder 94 come into contact with each other. By heating, the solders 18 and 94 are joined.

図１２（ａ）を参照し、ボンダヘッド４０を用い、半導体チップ８０ｂを半導体チップ８０ａ上に接触させる。半導体チップ８０ｂの半田１８が半導体チップ８０ａの貫通電極１２上に接触する。半導体チップ８０ａの第２面７０（上面）には、窪みが形成され、窪みの底に貫通電極１２の先端が露出する。このため、半導体チップ８０ｂの半田１８は、半導体チップ８０ａの貫通電極１２の先端に案内され半導体チップ８０ａと８０ｂとの位置合わせが容易となる。半田１８を加熱することにより、半田１８と貫通電極１２とが接合する。図１２（ｂ）を参照し、ボンダヘッド４０を用い、半導体チップ８０ｃを半導体チップ８０ｂ上に接触させる。半導体チップ８０ｃは、貫通電極１２が形成されていない以外は半導体チップ８０と同じである。半導体チップ８０ｃの半田１８が半導体チップ８０ｂの貫通電極１２上に接触する。半田１８を加熱することにより、半田１８と貫通電極１２とが接合する。半田１８の加熱は、半導体チップ１８ａから１８ｃを積層した後、一度に行なってもよい。   Referring to FIG. 12A, using the bonder head 40, the semiconductor chip 80b is brought into contact with the semiconductor chip 80a. The solder 18 of the semiconductor chip 80b comes into contact with the through electrode 12 of the semiconductor chip 80a. A recess is formed in the second surface 70 (upper surface) of the semiconductor chip 80a, and the tip of the through electrode 12 is exposed at the bottom of the recess. For this reason, the solder 18 of the semiconductor chip 80b is guided to the tip of the through electrode 12 of the semiconductor chip 80a, and the alignment between the semiconductor chips 80a and 80b becomes easy. By heating the solder 18, the solder 18 and the through electrode 12 are joined. Referring to FIG. 12B, using the bonder head 40, the semiconductor chip 80c is brought into contact with the semiconductor chip 80b. The semiconductor chip 80c is the same as the semiconductor chip 80 except that the through electrode 12 is not formed. The solder 18 of the semiconductor chip 80c comes into contact with the through electrode 12 of the semiconductor chip 80b. By heating the solder 18, the solder 18 and the through electrode 12 are joined. The solder 18 may be heated at once after the semiconductor chips 18a to 18c are stacked.

図１３（ａ）を参照し、半田ボール９８を形成する。半田ボール９８は、例えばＳｎ−Ａｇを主に含む。図１３（ｂ）を参照し、電極８６に半田ボール９８を設ける。実施例２においては、３つの半導体チップを積層する例を説明したが、２層または４層以上積層してもよい。半導体チップ８０ａから８０ｃ間および半導体チップ８０ａと配線基板８２との間にアンダーフィルを形成する工程を省略しているが、半導体チップ８０ａから８０ｃ間および半導体チップ８０ａと配線基板８２との間にアンダーフィルを形成してもよい。   Referring to FIG. 13A, solder balls 98 are formed. The solder ball 98 mainly contains, for example, Sn-Ag. With reference to FIG. 13B, solder balls 98 are provided on the electrodes 86. In the second embodiment, an example in which three semiconductor chips are stacked has been described. However, two or more layers may be stacked. Although the step of forming an underfill between the semiconductor chips 80a and 80c and between the semiconductor chip 80a and the wiring substrate 82 is omitted, the underfill is omitted between the semiconductor chips 80a and 80c and between the semiconductor chip 80a and the wiring substrate 82. A fill may be formed.

実施例２のように、半導体チップ８０を配線基板８２上に実装することができる。また、半導体チップ８０を、積層することもできる。半導体チップ８０を積層し、貫通電極１２を用い半導体チップ間を電気的に接続することにより、チップ間接続距離を短くすることができ、処理速度を向上できる。また、高密度実装が可能となる。さらに、低消費電力が可能となる。   As in the second embodiment, the semiconductor chip 80 can be mounted on the wiring board 82. In addition, the semiconductor chips 80 can be stacked. By stacking the semiconductor chips 80 and electrically connecting the semiconductor chips using the through electrodes 12, the inter-chip connection distance can be shortened and the processing speed can be improved. In addition, high-density mounting is possible. Furthermore, low power consumption is possible.

以上、本発明の実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

なお、以上の説明に関して更に以下の付記を開示する。
（付記１）半導体基板の第１面から第２面に向けて形成され、前記第１面まで達していない穴内に貫通電極を形成する工程と、前記半導体基板の前記第２面上に開口を有する絶縁膜を形成する工程と、前記絶縁膜をマスクに前記半導体基板を除去することにより、前記貫通電極の上面が露出するように前記貫通電極を囲む凹部を形成する工程と、前記凹部内に前記貫通電極の上面が露出するように埋め込まれた絶縁体を形成する工程と、を含むことを特徴とする半導体装置の製造方法。
（付記２）前記絶縁体を形成する工程は、前記凹部内、前記絶縁膜上および前記貫通電極上に絶縁体層を形成する工程と、前記絶縁体層を前記絶縁膜および前記貫通電極に対し選択的にエッチングする工程を含むことを特徴とする付記１記載の半導体装置の製造方法。
（付記３）前記凹部を形成する工程は、前記半導体基板を異方性エッチングすることにより前記凹部を形成する工程を含むことを特徴とする付記１または２記載の半導体装置の製造方法。
（付記４）前記絶縁膜の内部応力は前記絶縁体の内部応力より小さいことを特徴とする付記１から３のいずれか一項記載の半導体装置の製造方法。
（付記５）前記絶縁膜は無機絶縁膜であり、前記絶縁体は樹脂絶縁体であることを特徴とする付記１から３のいずれか一項記載の半導体装置の製造方法。
（付記６）前記無機絶縁膜は酸化シリコン膜または窒化シリコン膜であることを特徴とする付記５記載の半導体装置の製造方法。
（付記７）半導体基板と、半導体基板を貫通する貫通電極と、前記半導体基板の表面上に形成された絶縁膜と、前記半導体基板の前記表面に前記貫通電極を囲むように形成された凹部内に前記貫通電極が露出するように埋め込まれた前記絶縁膜とは異なる絶縁体と、を具備することを特徴とする半導体装置。
（付記８）前記凹部は前記絶縁膜に形成された開口により画定されていることを特徴とする付記７記載の半導体装置。 In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1) A step of forming a through electrode in a hole formed from the first surface of the semiconductor substrate toward the second surface and not reaching the first surface; and an opening on the second surface of the semiconductor substrate A step of forming an insulating film, a step of forming a recess surrounding the through electrode so that an upper surface of the through electrode is exposed by removing the semiconductor substrate using the insulating film as a mask; And a step of forming an insulator embedded so that the upper surface of the through electrode is exposed.
(Supplementary Note 2) The step of forming the insulator includes a step of forming an insulator layer in the recess, on the insulating film and on the through electrode, and the insulator layer on the insulating film and the through electrode. The method for manufacturing a semiconductor device according to appendix 1, wherein a step of selectively etching is included.
(Additional remark 3) The process of forming the said recessed part includes the process of forming the said recessed part by anisotropically etching the said semiconductor substrate, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.
(Additional remark 4) The internal stress of the said insulating film is smaller than the internal stress of the said insulator, The manufacturing method of the semiconductor device as described in any one of Additional remark 1 to 3 characterized by the above-mentioned.
(Additional remark 5) The said insulating film is an inorganic insulating film, The said insulator is a resin insulator, The manufacturing method of the semiconductor device as described in any one of additional marks 1 to 3 characterized by the above-mentioned.
(Additional remark 6) The said inorganic insulating film is a silicon oxide film or a silicon nitride film, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) Semiconductor substrate, through electrode penetrating the semiconductor substrate, insulating film formed on the surface of the semiconductor substrate, and in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode And an insulator different from the insulating film embedded so as to expose the through electrode.
(Additional remark 8) The said recessed part is demarcated by the opening formed in the said insulating film, The semiconductor device of Additional remark 7 characterized by the above-mentioned.

１０ 半導体基板
１２ 貫通電極
１４ 電極
１６ 金属端子
１８ 半田
２０ 絶縁膜
２２ 開口
２４ 凹部
２５ 絶縁体層
２６ 絶縁体
３０、３６ 絶縁膜
３２ 電子回路
３４ 配線
７０ 第２面
７２ 第１面 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Through-electrode 14 Electrode 16 Metal terminal 18 Solder 20 Insulating film 22 Opening 24 Recessed part 25 Insulator layer 26 Insulator 30, 36 Insulating film 32 Electronic circuit 34 Wiring 70 2nd surface 72 1st surface

Claims (5)

半導体基板の第１面から第２面に向けて形成され、前記第２面まで達していない穴内に貫通電極を形成する工程と、
前記半導体基板の前記第２面上に開口を有する絶縁膜を形成する工程と、
前記絶縁膜をマスクに前記半導体基板を除去することにより、前記貫通電極の上面が露出するように前記貫通電極を囲む凹部を形成する工程と、
前記凹部内に前記貫通電極の上面が露出するように埋め込まれた絶縁体を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming a through electrode in a hole formed from the first surface to the second surface of the semiconductor substrate and not reaching the second surface;
Forming an insulating film having an opening on the second surface of the semiconductor substrate;
Removing the semiconductor substrate using the insulating film as a mask to form a recess surrounding the through electrode so that an upper surface of the through electrode is exposed;
Forming an insulator embedded in the recess so that an upper surface of the through electrode is exposed;
A method for manufacturing a semiconductor device, comprising: 前記絶縁体を形成する工程は、前記凹部内、前記絶縁膜上および前記貫通電極上に絶縁体層を形成する工程と、
前記絶縁体層を前記絶縁膜および前記貫通電極に対し選択的にエッチングする工程を含むことを特徴とする請求項１記載の半導体装置の製造方法。 Forming the insulator includes forming an insulator layer in the recess, on the insulating film and on the through electrode;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of selectively etching the insulator layer with respect to the insulating film and the through electrode. 前記凹部を形成する工程は、前記半導体基板を異方性エッチングすることにより前記凹部を形成する工程を含むことを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the recess includes a step of forming the recess by anisotropically etching the semiconductor substrate. 半導体基板と、半導体基板を貫通する貫通電極と、前記半導体基板の表面上に形成された絶縁膜と、前記半導体基板の前記表面に前記貫通電極を囲むように形成された凹部内に前記貫通電極が露出するように埋め込まれた前記絶縁膜とは異なる絶縁体と、を具備することを特徴とする半導体装置。   A semiconductor substrate; a through electrode penetrating the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and the through electrode in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode. A semiconductor device comprising: an insulator different from the insulating film embedded so as to be exposed. 前記凹部は前記絶縁膜に形成された開口により画定されていることを特徴とする請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein the recess is defined by an opening formed in the insulating film.
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