CN210467823U - Rewiring layer - Google Patents
Rewiring layer Download PDFInfo
- Publication number
- CN210467823U CN210467823U CN201921627360.9U CN201921627360U CN210467823U CN 210467823 U CN210467823 U CN 210467823U CN 201921627360 U CN201921627360 U CN 201921627360U CN 210467823 U CN210467823 U CN 210467823U
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- diffusion barrier
- rewiring
- metal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a rewiring layer, rewiring layer includes: a silicon layer covering the upper surface of the substrate; the patterned diffusion barrier layer is positioned on the surface of the silicon layer, and the metal seed layer is positioned on the surface of the diffusion barrier layer; the metal electrode layer is positioned on the surface of the metal seed layer; and the bonding wire is used for electrically leading out the metal electrode layer. The utility model discloses in rewiring layer, increase the silicon layer for the substrate surface after the chemical mechanical polishing is more level and more smooth, thereby reduces the gold pad because of the coarse surface defect who leads to of substrate, improves the bonding yield.
Description
Technical Field
The utility model relates to a semiconductor technology encapsulates the field, especially relates to a rewiring layer.
Background
Low cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size. Currently, advanced packaging methods include: wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Packaging (FOWLP), Flip Chip (Flip Chip), and stack Packaging (POP).
For a multi-layer stacked packaging structure, preparation of multiple plastic packaging and multiple rewiring layers is involved, when the plastic packaging layer is prepared again for rewiring, a thicker plastic packaging layer is often formed on a wafer, and the plastic packaging layer after chemical mechanical polishing has a rough surface, so that the flatness of a bonding pad formed on the basis of the thicker plastic packaging layer is influenced, and even the defect or bonding failure of the surface of the bonding pad is caused.
Therefore, it is an urgent problem to be solved by those skilled in the art to improve the pad surface flatness and bonding yield of the re-wiring layer.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a rewiring layer for solving the problems of gold pad surface defects and bonding failures caused by uneven substrate in the prior art.
To achieve the above and other related objects, the present invention provides a rewiring layer,
the utility model also provides a rewiring layer, rewiring layer includes:
a silicon layer covering the upper surface of the substrate;
the patterned diffusion barrier layer is positioned on the surface of the silicon layer, and the metal seed layer is positioned on the surface of the diffusion barrier layer;
the metal electrode layer is positioned on the surface of the metal seed layer;
and the bonding wire is used for electrically leading out the metal electrode layer.
Optionally, the substrate is a plastic package wafer after chemical mechanical polishing.
Optionally, the thickness of the silicon layer is 1-5 μm.
Optionally, the roughness of the silicon layer is 1-3 μm.
Optionally, a polyimide layer is further disposed between the silicon layer and the diffusion barrier layer.
Optionally, the thickness of the polyimide layer is 5-10 μm.
As described above, the utility model discloses in rewiring layer, increase the silicon layer for the surface of substrate after the chemical mechanical polishing is more level and smooth, thereby reduces the gold pad because of the coarse surface defect who leads to of substrate, improves the bonding yield.
Drawings
Fig. 1 shows a flow chart of the method for manufacturing the redistribution layer according to the present invention.
FIG. 2 is a schematic view of a substrate in an embodiment.
FIG. 3 is a schematic diagram illustrating the formation of a silicon layer on the upper surface of the substrate in one embodiment.
Fig. 4 is a schematic diagram illustrating the formation of a diffusion barrier layer and a metal seed layer on the upper surface of the substrate in an embodiment.
FIG. 5 is a schematic diagram illustrating the formation of a photoresist layer on the top surface of the metal seed layer in an embodiment.
FIG. 6 is a schematic diagram illustrating the formation of a metal electrode layer in an embodiment.
FIG. 7 is a schematic view showing the removal of the photoresist layer in the embodiment.
Fig. 8 is a schematic view showing the removal of the metal seed layer and the diffusion barrier layer in the example.
Fig. 9 is a schematic diagram of bonding wire bonding in the embodiment.
Description of the element reference numerals
10 substrate
11 wafer
12 plastic packaging layer
13 silicon layer
14 diffusion barrier layer
15 Metal seed layer
16 photo resist layer
17 metal electrode layer
18 bonding wire
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
The embodiment provides a rewiring layer and a preparation method thereof.
As shown in fig. 9, the present embodiment provides a rewiring layer, the structure of which includes: a silicon layer 13 located on the substrate 10, an imaged diffusion barrier layer 14 and a metal seed layer 15 located on the surface of the silicon layer 13, a metal electrode layer 17 located on the metal seed layer 15, and a bonding wire 18 for electrically leading out the metal electrode layer 17.
For example, a polyimide layer (not shown) is further included between the silicon layer 13 and the diffusion barrier layer 14, and the thickness of the polyimide layer (not shown) is 5-10 μm.
As an example, the substrate 10 is a plastic package wafer after chemical mechanical polishing, and includes a wafer 11 and a plastic package layer 12.
As an example, the thickness of the silicon layer 18 is 1 to 5 μm.
As an example, the material of the diffusion barrier layer 14 includes one or more of Ti, TiN, Ta, TaN, TiW, Cr, the material of the metal seed layer 15 includes copper, and the material of the metal electrode layer 17 includes Ni/Au.
The embodiment also provides a preparation method of the rewiring layer.
Referring to fig. 1, the method for manufacturing the redistribution layer includes the following steps:
1) providing a substrate;
2) forming a silicon layer on the upper surface of the substrate;
3) sequentially forming a diffusion barrier layer and a metal seed layer on the upper surface of the silicon layer;
4) forming a graphical photoresist layer on the upper surface of the metal seed layer through gluing, exposing and developing processes;
5) forming a metal electrode layer on the upper surface of the metal seed layer which is not covered by the photoresist layer;
6) removing the photoresist layer, and removing the metal seed layer and the diffusion barrier layer which are not covered by the metal electrode layer;
7) and bonding the bonding wire with the metal electrode layer, and electrically leading out.
The technical solution of this embodiment will be described in further detail with reference to the accompanying drawings, and this embodiment is a method for manufacturing a redistribution layer based on a multilayer package structure.
As shown in fig. 2, step 1) is performed, where the substrate 10 provided in this embodiment is a plastic package wafer with a plastic package layer formed thereon, and the plastic package wafer at least includes a wafer 11 and a plastic package layer 12 located on an upper surface of the wafer 11.
In other embodiments, the substrate 10 may also be a single material wafer or a composite structure formed by a wafer and an adhesive layer.
As shown in fig. 3, step 2) is performed to form a silicon layer 13 on the upper surface of the substrate 10.
The method of manufacturing the silicon layer 13 includes a sputtering method. The silicon layer 13 is formed with the substrate surface by a sputtering method. The thickness of the silicon layer 13 is generally 1 to 5 μm, and the roughness of the silicon layer is 1 to 3 μm.
The reason for forming the silicon layer on the surface of the substrate is that the plastic package wafer is subjected to chemical mechanical polishing in the forming process, and after the chemical mechanical polishing, the surface roughness of the plastic package wafer is large, which affects the surface flatness of the metal electrode layer on the surface of the plastic package wafer formed subsequently, and even causes the bonding failure of the metal electrode layer. The surface of the plastic packaging layer is sputtered with a silicon layer, so that the flatness of the surface of the plastic packaging layer can be improved, and further, the flatness and bonding yield of the metal electrode layer can be improved. Of course, when the substrate surface is not flat due to other conditions, the flatness can be improved by adding a silicon layer.
As shown in fig. 4, step 3) is performed to form a diffusion barrier layer 14 and a metal seed layer 15 on the surface of the silicon layer 13.
The material of the diffusion barrier layer 14 may be one or more of Ti, TiN, Ta, TaN, TiW, Cr. The metal seed layer in the rewiring layer is mostly made of Cu material, and Cu has high diffusion coefficient in a silicon substrate or a low-dielectric-constant medium. Therefore, in order to avoid the diffusion of Cu, it is necessary to first prepare a diffusion barrier layer on the substrate to prevent the diffusion of Cu to the substrate and to increase the adhesion of Cu to the substrate.
In the present embodiment, Ti is used as the diffusion barrier layer, and the conventional sputtering method is used to form the diffusion barrier layer 13.
The reason for forming the metal seed layer 15 is that a redistribution layer of the device is generally prepared by an electroplating method, and the key of the electroplating formation is to generate current through a metal layer on the surface to deposit metal, for most substrates, the metal layer is generally made of a semiconductor material or a composite material of a semiconductor and a polymer, and is non-conductive, so that the electroplating of the redistribution layer cannot be performed, and therefore, a metal layer needs to be formed on the surface of the non-conductive substrate to be used as a metal seed layer for electroplating.
The material of the metal seed layer 15 may be copper or copper alloy, or may be aluminum or aluminum alloy. In this embodiment, copper is selected as the material of the metal seed layer.
The diffusion barrier layer 14 and the metal seed layer 15 may be formed by a physical or chemical method such as sputtering, electrochemical plating, physical vapor deposition, or chemical vapor deposition.
As shown in fig. 5, step 4) is performed to form a patterned photoresist layer 16 by applying photoresist, exposing, and developing.
And uniformly coating the photoresist on the surface of the metal seed layer 15, transferring the substrate covered with the photoresist from a coater into a baking oven for coating and baking to evaporate water in the photoresist and fix the photoresist. The ultraviolet light is irradiated to the surface of the substrate coated with the photoresist through the pattern on the photomask plate, the photoresist is deformed after being irradiated by the ultraviolet light, the photoresist is corroded by the developing solution, and after being cleaned, the pattern which is consistent with or complementary to the pattern on the photomask plate is left, so that the patterned photoresist layer 16 is formed.
As shown in fig. 6, step 5) is performed to form a metal electrode layer 17 on the upper surface of the metal seed layer 15 uncovered by the photoresist layer 16.
The thickness of the metal electrode layer 17 is preferably less than or equal to the thickness of the photoresist layer 16 so that the line width of the metal electrode layer 17 can be precisely controlled.
The metal electrode layer 17 is made of Ni/Au. The metal electrode layer 17 may be formed by an electroless plating method or an electroplating method. In this embodiment, the metal electrode layer 17 is formed by an electroplating method. The specific method comprises the following steps: a nickel layer with low stress and about 3-5 mu m is plated on the metal seed layer by an electric applying mode, and then a thin gold layer with about 0.01-005 mu m is plated on the nickel layer. Under the condition of a certain electroplating solution, the control of the thickness of the plating layer is realized by controlling the electroplating time.
As shown in fig. 7 and 8, step 6) is performed to remove the patterned photoresist layer 16, and to remove the metal seed layer 15 and the diffusion barrier layer 14 which are not covered by the metal electrode layer 16.
In practical production, ashing treatment is generally performed in a mixed process gas of oxygen and fluorine at a process temperature higher than 200 ℃ to remove the photoresist layer.
As an example, a method of removing the metal seed layer 15 and the diffusion barrier layer 14 uncovered by the metal electrode layer includes dry etching or wet etching. In the present embodiment, the metal seed layer 15 and the diffusion barrier layer 14 that are not covered by the metal electrode layer 16 are removed by using a wet etching process, which is a common etching means due to fast etching rate and low cost. Different etching solutions are required to be selected because the metal seed layer and the diffusion barrier layer are made of different materials, namely different etching ratios. Those skilled in the art can do this as needed. Of course, in other embodiments, other processes may be used to remove the metal seed layer 15 and the diffusion barrier layer 14.
As shown in fig. 9, the bonding wire 18 is bonded to the metal electrode layer 17 to electrically extract the metal electrode layer.
The bonding method is, for example, any one of ultrasonic bonding, thermocompression bonding, and thermosonic bonding. In this embodiment, a thermocompression bonding method is selected for bonding.
Through the steps S1-S7, the preparation of the rewiring layer is finally and completely realized.
In this embodiment, the surface flatness of the plastic package wafer is provided by additionally arranging the silicon layer on the surface of the plastic package wafer, so that the surface flatness of the metal electrode layer can be improved, and the bonding yield can be improved.
To sum up, the utility model discloses a rewiring layer, rewiring layer includes the silicon layer that covers on the upper surface of substrate; the patterned diffusion barrier layer is positioned on the surface of the silicon layer, and the metal seed layer is positioned on the surface of the diffusion barrier layer; the metal electrode layer is positioned on the surface of the metal seed layer; and the bonding wire is used for electrically leading out the metal electrode layer. The silicon layer is additionally arranged on the surface of the plastic package wafer to provide the surface flatness of the plastic package wafer, so that the surface flatness of the metal electrode layer can be improved, and the bonding yield is improved.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A rewiring layer, wherein the rewiring layer comprises:
a silicon layer covering the upper surface of the substrate;
the patterned diffusion barrier layer is positioned on the surface of the silicon layer, and the metal seed layer is positioned on the surface of the diffusion barrier layer;
the metal electrode layer is positioned on the surface of the metal seed layer;
and the bonding wire is used for electrically leading out the metal electrode layer.
2. The redistribution layer of claim 1 wherein said substrate is a plastic encapsulated wafer after chemical mechanical polishing.
3. The rewiring layer of claim 1, wherein the silicon layer has a thickness of 1-5 μm.
4. The rewiring layer of claim 1, wherein the silicon layer has a roughness of 1-3 μm.
5. The redistribution layer of claim 1 wherein a polyimide layer is further disposed between said silicon layer and said diffusion barrier layer.
6. The rewiring layer of claim 5 wherein the polyimide layer has a thickness of 5-10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921627360.9U CN210467823U (en) | 2019-09-27 | 2019-09-27 | Rewiring layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921627360.9U CN210467823U (en) | 2019-09-27 | 2019-09-27 | Rewiring layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210467823U true CN210467823U (en) | 2020-05-05 |
Family
ID=70436087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921627360.9U Active CN210467823U (en) | 2019-09-27 | 2019-09-27 | Rewiring layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210467823U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111892015A (en) * | 2020-07-15 | 2020-11-06 | 杭州见闻录科技有限公司 | Wafer-level packaging method and packaging structure of MEMS device |
-
2019
- 2019-09-27 CN CN201921627360.9U patent/CN210467823U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111892015A (en) * | 2020-07-15 | 2020-11-06 | 杭州见闻录科技有限公司 | Wafer-level packaging method and packaging structure of MEMS device |
| CN111892015B (en) * | 2020-07-15 | 2021-05-25 | 见闻录(浙江)半导体有限公司 | Wafer-level packaging method and packaging structure of MEMS device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI402939B (en) | Through-silicon vias and methods for forming the same | |
| CN106057760B (en) | Semiconductor devices and forming method thereof | |
| US10553458B2 (en) | Chip packaging method | |
| WO2022012538A1 (en) | Multi-chip 3d package structure and manufacturing method therefor | |
| US11107758B2 (en) | Fan-out package structure and method | |
| US8508046B2 (en) | Circuit substrate and method of manufacturing same | |
| JP4106438B2 (en) | Multilayer fine wiring interposer and manufacturing method thereof | |
| CN101645407A (en) | Under bump metal layer, wafer level chip scale package structure and forming method thereof | |
| CN114937614A (en) | Preparation method of wiring layer structure | |
| CN210467823U (en) | Rewiring layer | |
| WO2024120422A1 (en) | Novel packaging substrate having interposer function, and manufacturing method therefor | |
| CN210040131U (en) | Rewiring layer | |
| CN210403718U (en) | Rewiring layer | |
| CN101814477A (en) | Utilize the silicon through hole that interconnection structure forms after the passivation | |
| US9018750B2 (en) | Thin film structure for high density inductors and redistribution in wafer level packaging | |
| CN112582333A (en) | Rewiring layer and preparation method thereof | |
| CN112259466A (en) | Preparation method of rewiring layer | |
| CN101188204B (en) | Semiconductor device and manufacturing method therefor | |
| CN116469832A (en) | Board level packaging method | |
| US11876040B2 (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
| CN112582334A (en) | Rewiring layer and preparation method thereof | |
| CN112259465A (en) | Rewiring layer and preparation method thereof | |
| CN211088206U (en) | Rewiring layer | |
| CN212209479U (en) | Rewiring layer | |
| CN112289688B (en) | Preparation method of rewiring layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |