WO2022012538A1

WO2022012538A1 - Multi-chip 3d package structure and manufacturing method therefor

Info

Publication number: WO2022012538A1
Application number: PCT/CN2021/106025
Authority: WO
Inventors: 霍炎; 涂旭峰
Original assignee: 矽磐微电子(重庆)有限公司
Priority date: 2020-07-13
Filing date: 2021-07-13
Publication date: 2022-01-20
Also published as: CN111883521A; CN111883521B

Abstract

The present application provides a multi-chip 3D package structure and a manufacturing method therefor. In the package structure, a first bare chip and a second bare chip, which are arranged back to back, and a conductive column are packaged in a plastic packaging layer, wherein the first bare chip comprises a plurality of first bonding pads located on an active surface, the active surface of the first bare chip is covered with a protective layer exposing the first bonding pads, and the second bare chip comprises a plurality of second bonding pads positioned on the active surface; the protective layer, the first bonding pads, a first end of the conductive column and the front surface of the plastic packaging layer are provided with one or more first rewiring layers for carrying out circuit layout on the first bonding pads, and the first rewiring layers are led to the back surface of the plastic packaging layer by means of the conductive column; and the active surface of the second bare chip, a second end of the conductive column and the back surface of the plastic packaging layer are provided with one or more second rewiring layers for carrying out circuit layout on the second bonding pads, the second rewiring layers are electrically connected to the first rewiring layers by means of the conductive column, and the second rewiring layers are provided with pins.

Description

Multi-chip 3D packaging structure and fabrication method thereof

technical field

The present application relates to the technical field of chip packaging, and in particular, to a multi-chip 3D packaging structure and a manufacturing method thereof.

Background technique

In recent years, with the continuous development of circuit integration technology, electronic products are developing in the direction of miniaturization, intelligence, high integration, high performance and high reliability. Packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product.

SUMMARY OF THE INVENTION

The purpose of the invention of the present application is to provide a multi-chip 3D packaging structure and a manufacturing method thereof, so as to meet the requirements of small volume, compact structure and high integration of the packaging structure.

In order to achieve the above object, a first aspect of the present application provides a multi-chip 3D packaging structure, comprising: a first die and a second die, the first die includes a plurality of first pads, the first pads The pad is located on the active surface of the first die, the second die includes a plurality of second pads, the second pads are located on the active surface of the second die, the first die is connected to the the second die is arranged back-to-back; a protective layer covers the active surface of the first die, the protective layer exposes at least part of the first pad; and a conductive column is located between the first die and the the side of the second die, the conductive post includes opposite first ends and a second end; a plastic encapsulation layer covers the first die, the second die and the conductive post, the The front side of the plastic packaging layer exposes the protective layer, the exposed portion of the first pad and the first end of the conductive pillar, and the back side of the plastic packaging layer exposes the active surface of the second die and the conductive pillar the second end of the first redistribution layer, located on the protective layer, the exposed portion of the first pad, the first end of the conductive post and the front surface of the plastic encapsulation layer; The first pad is used for circuit layout, the first redistribution layer is led to the back of the plastic sealing layer through the conductive column, and the first redistribution layer includes one or more layers; the first dielectric layer, The first redistribution layer is embedded; the second redistribution layer is located on the active surface of the second bare chip, the second end of the conductive column and the back surface of the plastic packaging layer, and is used for each of the The second pad performs circuit layout, the second redistribution layer is electrically connected to the first redistribution layer through the conductive posts, and the second redistribution layer includes one or more layers; pins, connected on the second redistribution layer; the second dielectric layer at least embeds the second redistribution layer, and the pins are exposed outside the second dielectric layer.

A second aspect of the present application provides a multi-chip 3D packaging structure, including: a first die and a second die, the first die includes a plurality of first pads, the first pads are located on the first die The active surface of a die, the second die includes a plurality of second pads, the second pads are located on the active surface of the second die, the first die and the second die back-to-back arrangement; a protective layer covering the active surface of the first die, the protective layer exposing at least part of the first pad; a plastic encapsulation layer covering the first die and the second die The front side of the plastic encapsulation layer exposes the protective layer and the exposed part of the first pad, the back side of the plastic encapsulation layer exposes the active surface of the second die, and the plastic encapsulation layer has conductive plugs , the conductive plug is located on the side of the first die and the second die; the first redistribution layer is located on the protective layer, the exposed part of the first pad, the conductive plug One end of the plug and the front surface of the plastic sealing layer are used for circuit layout of each of the first pads, and the first redistribution layer is led to the back surface of the plastic sealing layer through the conductive plug, and the The first redistribution layer includes one or more layers; the first dielectric layer embeds the first redistribution layer; the second redistribution layer is located on the active surface of the second bare chip, the conductive plug The other end of the plug and the back surface of the plastic sealing layer are used for circuit layout of each of the second pads, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive plug , the second rewiring layer includes one or more layers; pins are connected to the second rewiring layer; a second dielectric layer at least embeds the second rewiring layer, and the pins exposed to the second dielectric layer.

A third aspect of the present application provides a method for manufacturing a multi-chip 3D package structure, including: providing a carrier board and at least one group of components to be packaged carried on the carrier board, each group of components to be packaged includes: A die and a second die, the first die includes a plurality of first pads, the first pads are located on the active surface of the first die, and the active surface of the first die is covered with a protective layer, the second die includes a plurality of second pads, the second pads are located on the active surface of the second die; and a conductive column, the conductive column includes opposite first ends and second wherein, the active surface of the second die and the second ends of the conductive pillars face the carrier, and the conductive pillars are located on the sides of the first die and the second die; A plastic sealing layer is formed on the surface of the carrier board to embed the components to be packaged; the plastic sealing layer is thinned until the first ends of the protective layer and the conductive pillars are exposed; an opening is formed in the protective layer , to expose at least part of the first pad; a first redistribution layer is formed on the protective layer, the first pad, the first end of the conductive post and the front surface of the plastic encapsulation layer, so The first redistribution layer is used for circuit layout of each of the first pads. layer or more; forming a first dielectric layer burying the first redistribution layer; removing the carrier to expose the active surface of the second die, the second ends of the conductive pillars and all the backside of the plastic encapsulation layer; a second redistribution layer is formed on the active surface of the second die, the second end of the conductive post and the backside of the plastic encapsulation layer, and the second redistribution layer is used to connect the Circuit layout is performed on each of the second pads, the second redistribution layer is electrically connected to the first redistribution layer through the conductive pillars, and the second redistribution layer includes one or more layers; Pins are formed on the second redistribution layer and a second dielectric layer at least embedded in the second redistribution layer is formed, and the pins are exposed outside the second dielectric layer.

A fourth aspect of the present application provides a method for manufacturing a multi-chip 3D packaging structure, including: providing a carrier board and at least one group of components to be packaged carried on the carrier board, each group of components to be packaged includes: A first die and a second die, the first die includes a plurality of first pads, the first pads are located on the active surface of the first die, and the active surface of the first die covers There is a protective layer, the second die includes a plurality of second pads, and the second pads are located on the active surface of the second die; wherein, the active surface of the second die faces the carrier board ; forming a plastic encapsulation layer to embed the to-be-packaged component on the surface of the carrier board; thinning the plastic encapsulation layer until the protective layer is exposed; forming an opening in the protective layer to expose the first solder at least part of the pad; a first redistribution layer is formed on the protective layer, the exposed part of the first pad and the front surface of the plastic encapsulation layer, the first redistribution layer is used for each of the first redistribution layers The pads are used for circuit layout, and the first redistribution layer includes one or more layers; a first dielectric layer that embeds the first redistribution layer is formed; the carrier plate is removed to expose the second bare The active side of the sheet and the back side of the plastic sealing layer; a conductive plug is formed in the plastic sealing layer through the back side of the plastic sealing layer, so as to lead the first redistribution layer to the back side of the plastic sealing layer, the The conductive plug includes opposite first ends and second ends; a second redistribution layer is formed on the active surface of the second die, the second end of the conductive plug and the back surface of the plastic encapsulation layer, so that the The second redistribution layer is used for circuit layout of each of the second pads, the second redistribution layer is electrically connected to the first redistribution layer through the conductive plug, and the second redistribution layer is The layer includes one or more layers; leads are formed on the second redistribution layer and a second dielectric layer at least embedded in the second redistribution layer is formed, and the leads are exposed on the second redistribution layer. outside the dielectric layer.

In the multi-chip 3D packaging structure of the present application, the first redistribution layer is combined with the second redistribution layer, and through the circuit layout on two sides, compared with the circuit layout on only one side, the density of wiring can be improved, forming More complex wiring and smaller multi-chip 3D package structure. The multi-chip 3D package structure realizes external circuit connection through pins, and the performance is reliable. In addition, the layout of the conductive pillars, the first redistribution layer, and the second redistribution layer is free and flexible, and is not limited by the size of the substrate.

In addition, due to the existence of the protective layer, the first redistribution layer can be directly formed on the front side of the protective layer and the plastic sealing layer after the plastic sealing process, instead of forming a dielectric layer on the entire panel; in panel packaging, due to the large panel area , it is difficult to form a dielectric layer on a large-area panel, and more materials are used for the dielectric layer, and the existence of the protective layer reduces the process difficulty and cost of packaging.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.

Description of drawings

1 is a schematic cross-sectional structural diagram of a multi-chip 3D packaging structure according to a first embodiment of the present application;

Fig. 2 is the flow chart of the manufacturing method of the multi-chip 3D packaging structure in Fig. 1;

3 to 9 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2;

10 is a schematic cross-sectional structural diagram of a multi-chip 3D packaging structure according to a second embodiment of the present application;

FIG. 11 is a flowchart of a method for manufacturing the multi-chip 3D packaging structure in FIG. 10;

12 to 18 are schematic diagrams of intermediate structures corresponding to the process in FIG. 11 .

detailed description

In order to make the above objects, features and advantages of the present application more obvious and easy to understand, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional structural diagram of a multi-chip 3D packaging structure according to a first embodiment of the present application.

Referring to FIG. 1 , the multi-chip 3D packaging structure 1 includes:

The first bare chip 11 and the second bare chip 12, wherein the first bare chip 11 includes a plurality of first pads 111, the first pads 111 are located on the active surface 11a of the first bare chip 11, and the second bare chip 12 includes a plurality of first pads 111 The second pad 121, the second pad 121 is located on the active surface 12a of the second die 12, and the first die 11 and the second die 12 are arranged back-to-back;

The protective layer 110 covers the active surface 11a of the first die 11, and the protective layer 110 exposes at least part of the first pad 111;

The conductive pillars 13 are located at the sides of the first die 11 and the second die 12, and the conductive pillars 13 include opposite first ends 13a and second ends 13b;

The plastic encapsulation layer 14 covers the first die 11 , the second die 12 and the conductive pillars 13 . The front surface 14 a of the plastic encapsulation layer 14 exposes the protective layer 110 , the exposed portion of the first pad 111 and the first end 13 a of the conductive pillars 13 , the back surface 14b of the plastic encapsulation layer 14 exposes the active surface 12a of the second die 12 and the second end 13b of the conductive pillar 13;

The first redistribution layer 15 is located on the protective layer 110 , the exposed portion of the first pad 111 , the first end 13 a of the conductive post 13 and the front surface 14 a of the plastic sealing layer 14 , and is used for circuit layout of each first pad 111 , the first redistribution layer 15 is led to the back surface 14b of the plastic sealing layer 14 through the conductive column 13;

the first dielectric layer 16, burying the first redistribution layer 15;

The second redistribution layer 17 is located on the active surface 12a of the second die 12, the second end 13b of the conductive pillar 13, and the back surface 14b of the plastic encapsulation layer 14, and is used for circuit layout of each second pad 121. The second The redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive pillars 13;

The pin 18 is connected to the second redistribution layer 17;

The second dielectric layer 19 at least embeds the second redistribution layer 17 , and the pins 18 are exposed outside the second dielectric layer 19 .

Referring to FIG. 1 , in this embodiment, in the stacking direction of the first die and the second die, the orthographic projection area of the second die 12 is larger than the orthographic projection area of the first die 11 , In order to reduce the area of the multi-chip 3D packaging structure. In some embodiments, in the stacking direction of the first die and the second die, the orthographic projection area of the first die 11 may also be larger than the orthographic projection area of the second die 12 .

The first die 11 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE). The second die 12 may be a control chip for controlling the first die 11 . In other embodiments, the first die 11 and the second die 12 may be dies that require electrical interconnection and have other functions. The present application does not limit the functions of the first die 11 and the second die 12 .

The first die 11 includes an opposite active surface 11a and a back surface 11b. The first pad 111 is provided on the active surface 11a. The first die 11 may contain a variety of devices formed on the semiconductor substrate, and electrical interconnect structures that are electrically connected to the respective devices. The first pads 111 are connected with the electrical interconnection structure to input and/or output electrical signals of the respective devices.

The second die 12 includes opposing active surfaces 12a and back surfaces 12b. The second pad 121 is provided on the active surface 12a. The second die 12 may contain various devices formed on the semiconductor substrate, as well as electrical interconnect structures that electrically connect the various devices. The second pads 121 are connected with an electrical interconnection structure to input and/or output electrical signals of the respective devices.

The back-to-back arrangement of the first die 11 and the second die 12 means that the back surface 11 b of the first die 11 and the back surface 12 b of the second die 12 are attached together.

The protective layer 110 is an insulating material, which may be an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride.

The material of the conductive pillar 13 may be a metal with excellent conductivity such as copper.

The number of the conductive pillars 13 may be one or more, and the number and position of the conductive pillars 13 may be determined according to a predetermined circuit layout.

The material of the plastic sealing layer 14 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic sealing layer 14 can also be various polymers or composite materials of resin and polymer.

The plastic sealing layer 14 includes a front side 14a and a back side 14b opposite to each other. In this embodiment, the front surface 14 a of the plastic encapsulation layer 14 exposes the protective layer 110 , the first pads 111 and the first ends 13 a of the conductive pillars 13 .

In the embodiment shown in FIG. 1 , the first redistribution layer 15 includes several metal blocks 15a with one layer. The plurality of metal blocks 15a are selectively electrically connected to a plurality of first pads 111 to realize the circuit layout of the first pads 111; The electrical signals of the first bare chip 11 are led to the back surface 14b of the plastic encapsulation layer 14 . The layout of the first redistribution layer 15 may be determined according to a predetermined circuit layout.

In some embodiments, the first redistribution layer 15 may further include two or more layers, that is, the metal blocks 15a having two or more layers.

The second redistribution layer 17 includes several metal blocks 17a having one layer. The plurality of metal blocks 17a are selectively electrically connected to a plurality of second pads 121 to implement the circuit layout of the second pads 121; The electrical connection between the second redistribution layer 17 and the first redistribution layer 15 is achieved. The layout of the second redistribution layer 17 may be determined according to a predetermined circuit layout.

In some embodiments, the second redistribution layer 17 may further include two or more layers, that is, the metal blocks 17a having two or more layers.

The pins 18 on the second redistribution layer 17 may be metal bumps.

The materials of the first dielectric layer 16 and the second dielectric layer 19 may be insulating resin materials or inorganic materials. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride. Compared with inorganic materials, the tensile stress of the insulating resin material is smaller, which can prevent warpage of the surface of the multi-chip 3D packaging structure 1 .

Referring to FIG. 1 , the multi-chip 3D packaging structure 1 in this embodiment realizes the connection between multiple chips and external circuits through pins 18 .

In the multi-chip 3D packaging structure 1, on the one hand, the circuit layout is realized on the front side 14a of the plastic sealing layer 14 through the first redistribution layer 15; Circuit layout of the back side 14b. Compared with the circuit layout on only one side, the circuit layout on both sides of this embodiment can improve the density of wiring, and form a multi-chip 3D package structure 1 with more complex wiring and smaller volume.

In addition, the multi-chip 3D packaging structure 1 realizes the connection with the external circuit through the pins 18, so that the performance of the multi-chip 3D packaging structure 1 is reliable. The layout of the conductive pillars 13 , the first redistribution layer 15 , and the second redistribution layer 17 is free and flexible, and is not limited by the size of the substrate.

An embodiment of the present application provides a method for fabricating the multi-chip 3D packaging structure 1 in FIG. 1 . FIG. 2 is a flow chart of the production method. 3 to 9 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2 .

First, referring to step S1 in FIG. 2 , FIG. 3 and FIG. 4 , a carrier board 2 and a plurality of groups of components to be packaged 10 carried on the carrier board 2 are provided. Each group of components to be packaged 10 includes: The chip 11 and the second die 12, the first die 11 includes a number of first pads 111, the first pads 111 are located on the active surface 11a of the first die 11, and the active surface 11a of the first die 11 is covered with a protection Layer 110, the second die 12 includes a plurality of second pads 121, the second pads 121 are located on the active surface 12a of the second die 12; and the conductive post 13, the conductive post 13 includes opposite first ends 13a and second The end 13b; wherein, the active surface 12a of the second die 12 and the second end 13b of the conductive pillar 13 face the carrier 2, and the conductive pillar 13 is located on the side of the first die 11 and the second die 12. FIG. 3 is a top view of a carrier board and groups of components to be packaged; FIG. 4 is a cross-sectional view along line AA in FIG. 3 .

In this embodiment, the first die 11 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE). The second die 12 may be a control chip for controlling the first die 11 . In other embodiments, the first die 11 and the second die 12 may be dies that require electrical interconnection and have other functions. The present application does not limit the functions of the first die 11 and the second die 12 .

Referring to FIG. 3 , in this embodiment, in the stacking direction of the first die and the second die, the orthographic projection area of the second die 12 is larger than the orthographic projection area of the first die 11 , In order to reduce the area of the multi-chip 3D packaging structure 1 . In some embodiments, in the stacking direction of the first die and the second die, the orthographic projection area of the first die 11 may also be larger than the orthographic projection area of the second die 12 .

The first die 11 includes an opposite active surface 11a and a back surface 11b. The first die 11 may contain a variety of devices formed on the semiconductor substrate, and electrical interconnect structures that are electrically connected to the respective devices. The first pads 111 disposed on the active surface 11a of the first die 11 are connected to the electrical interconnection structure for inputting and/or outputting electrical signals of the respective devices. The protective layer 110 covers the first pads 111 to protect the first pads 111 when the plastic encapsulation layer is thinned.

The second die 12 includes opposing active surfaces 12a and back surfaces 12b. The second pad 121 is provided on the active surface 12a. The second die 12 may also contain various devices formed on the semiconductor substrate, as well as electrical interconnect structures that electrically connect the various devices. The second pads 121 disposed on the active surface 12a of the second die 12 are connected to the electrical interconnection structure for inputting and/or outputting electrical signals of the respective devices.

Both the first die 11 and the second die 12 are formed by dicing wafers. Taking the first bare chip 11 as an example, the wafer includes an active surface of the wafer and a back surface of the wafer, and the active surface of the wafer is provided with a first pad 111 and an insulating layer (not shown) protecting the first pad 111 . After the wafer is cut, a first bare chip 11 is formed. Correspondingly, the first bare chip 11 includes an active surface 11a and a back surface 11b, and the active surface 11a of the bare chip is provided with a first pad 111 and an electrically insulating adjacent first pad 111. Insulation.

A protective layer 110 is applied on the active surface 11 a of the first die 11 . The process of applying the protective layer 110 may be as follows: before the wafer is cut into the first die 11 , the protective layer 110 is applied on the active surface of the wafer; the wafer with the protective layer 110 is cut to form the first die 11 with the protective layer 110 . . The process of applying the protective layer 110 can also be as follows: after the wafer is cut into the first die 11 , the protective layer 110 is applied on the active surface 11 a of the first die 11 .

After the multiple groups of components 10 to be encapsulated are encapsulated, a dielectric layer needs to be applied on the encapsulated layer. Before encapsulation, the protective layer 110 is applied on the first die 11 to avoid large-area fabrication of the dielectric layer, and on the one hand, to save the dielectric material, on the other hand can avoid the warpage of the plastic body.

The protective layer 110 is an insulating material, which may be an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.

When the material of the protective layer 110 is an insulating resin material, it can be a) pressed on the first pad 111 and the insulating layer between the adjacent first pads 111 by a lamination process, or b) firstly coated or printed on the insulating layer. On the first pad 111 and the insulating layer between the adjacent first pads 111, post-curing, or c) curing on the first pad 111 and the insulating layer between the adjacent first pads 111 by an injection molding process .

When the material of the protective layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the first pad 111 and the insulating layer between the adjacent first pads 111 through a deposition process.

The protective layer 110 may include one or more layers.

The wafer may be thinned from the backside before dicing to reduce the thickness of the first die 11 and/or the second die 12 .

The carrier plate 2 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.

When multiple groups of components to be packaged 10 are arranged on the surface of the carrier board 2 , a plurality of second dies 12 may be arranged on the carrier board 2 first. An adhesive layer may be provided between the active surface 12a of the second die 12 and the carrier board 2, so as to realize the fixation between the two. A whole-surface adhesive layer may be coated on the surface of the carrier board 2, and a plurality of second dies 12 may be placed on the adhesive layer.

A plurality of first dies 11 may be arranged on another carrier board. An adhesive layer may also be provided between the active surface 11a of the first die 11 and the carrier, so as to realize the fixation between the two.

The backside 11b of the first die 11 and/or the backside 12b of the second die 12 may be provided with an adhesive layer.

On the above basis, the two carriers are butted together, so that the backside 11b of the first die 11 and the backside 12b of the second die 12 are bonded together. The carrier carrying the plurality of first dies 11 is then removed.

The adhesive layer between the second die 12 and the carrier board 2 and the adhesive layer between the first die 11 and the carrier board can be made of easily peelable materials, so as to peel off the corresponding carrier board, for example, by heating Thermal separation material that can be made to lose tack, or UV separation material that can be made to lose tack by UV irradiation.

Next, the second ends 13b of the respective conductive pillars 13 are placed on the adhesive layer on the surface of the carrier board 2 in a predetermined arrangement, so as to realize the fixation between the two.

The height of the conductive pillars 13 is greater than the sum of the thicknesses of the first die 11 and the second die 12 arranged back to back.

A group of components 10 to be packaged are located in an area on the surface of the carrier board 2 for the convenience of subsequent cutting. A plurality of groups of components to be packaged 10 are fixed on the surface of the carrier board 2 to manufacture a plurality of multi-chip 3D packaging structures 1 at the same time, thereby facilitating mass production and reducing costs. In some embodiments, a group of components 10 to be packaged can also be fixed on the surface of the carrier board 2 .

Next, referring to step S2 in FIG. 2 and as shown in FIG. 5 , a plastic sealing layer 14 is formed on the surface of the carrier board 2 to embed each group of components to be packaged 10 ; as shown in FIG. The protective layer 110 on the active surface 11 a of the first die and the first end 13 a of each conductive pillar 13 .

The material of the plastic sealing layer 14 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic sealing layer 14 can also be various polymers or composite materials of resin and polymer. Correspondingly, the encapsulation can be performed by first filling the first die 11 and the second die 12 and the conductive pillars 13 with liquid molding compound, and then curing at high temperature with a molding mold. In some embodiments, the plastic encapsulation layer 14 can also be formed by means of plastic material forming such as thermocompression forming and transfer forming.

The molding layer 14 may include opposite front surfaces 14a and back surfaces 14b.

Referring to FIG. 6 , the thinning of the plastic sealing layer 14 is performed from the front surface 14a, and may be performed by mechanical grinding such as grinding with a grinding wheel.

When the plastic encapsulation layer 14 is thinned until the protective layer 110 disposed on the active surface 11 a of each first die 11 is exposed, the conductive pillars 13 have been partially removed to ensure that the first ends 13 a of the conductive pillars 13 are exposed to the plastic encapsulation layer. 14 on the front side 14a.

During the process of forming the plastic encapsulation layer 14 and thinning the plastic encapsulation layer 14 , the protective layer 110 can prevent the electrical interconnection structures and devices in the first pad 111 , the first die 11 and the second die 12 from being damaged.

In this step, the plastic package of the component to be packaged 10 is formed.

Next, referring to step S3 in FIG. 2 and as shown in FIG. 7 , an opening 110 a is formed in the protective layer 110 to expose at least part of the first pad 111 ; in the protective layer 110 , the exposed part of the first pad 111 , A first redistribution layer 15 is formed on the first end 13a of the conductive pillar 13 and the front surface 14a of the plastic encapsulation layer 14, wherein the first redistribution layer 15 is used for each first pad 111 of the first die 11 in the group. The circuit layout is carried out, the first redistribution layer 15 is led to the back surface 14b of the plastic encapsulation layer 14 through the conductive pillars 13 in the group;

In this embodiment, the first redistribution layer 15 includes one layer, that is, a metal block 15a having one layer. Forming the opening 110a and the first redistribution layer 15 further includes the following steps S31 to S38.

Step S31 : forming a first photoresist layer on the protective layer 110 of each first die 11 , the first end 13 a of each conductive pillar 13 and the front surface 14 a of the plastic sealing layer 14 .

In this step S31, in an optional solution, the first photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and attached to the protective layer 110 of each first die 11 , the first end 13 a of each conductive pillar 13 and the front surface 14 a of the plastic sealing layer 14 . In other alternatives, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.

Step S32 : exposing and developing the photoresist layer to form a patterned first photoresist layer.

In this step S32, the first photoresist layer is patterned. In other alternatives, other easily removable sacrificial materials can also be used to replace the first photoresist layer.

Step S33 : using the patterned first photoresist layer as a mask, dry etching or wet etching the protective layer 110 to form a plurality of openings 110 a to expose partial regions of the first pads 111 . An opening 110a may expose a partial area of a first pad 111 . In other embodiments, one opening 110a may also expose partial regions of two or more first pads 111 .

Step S34 : removing the remaining first photoresist layer by ashing.

Step S35 : forming a second photoresist layer on the protective layer 110 of each first die 11 , the first pad 111 , the first end 13 a of each conductive pillar 13 and the front surface 14 a of the plastic sealing layer 14 .

For the formation method of the second photoresist layer, reference may be made to the formation method of the first photoresist layer in step S31.

Step S36 : exposing and developing the second photoresist layer, leaving the second photoresist layer in the first predetermined area, wherein the first predetermined area is complementary to the area where the metal block 15a of the first redistribution layer 15 to be formed is located.

Step S37 : filling a metal layer in a complementary region of the first predetermined region to form the metal block 15 a of the first redistribution layer 15 .

The position of the metal block 15 a is such that it can be electrically connected to several first pads 111 of the first die 11 . A portion of the metal blocks 15a are positioned so that they can be electrically connected to the first ends 13a of the conductive pillars 13, so as to lead the electrical signals of the first die 11 to the backside 14b of the plastic encapsulation layer 14.

This step S37 may be completed by an electroplating process. The process of electroplating copper or aluminum is relatively mature.

In one embodiment, before the second photoresist layer is formed in step S35, the protective layer 110 of each first die 11 and the first solder exposed by the protective layer 110 may be formed by physical vapor deposition or chemical vapor deposition. A seed layer is formed on the disk 111 , the first ends 13 a of the conductive pillars 13 and the front surface 14 a of the plastic encapsulation layer 14 . The seed layer can be used as a power supply layer for electroplating copper or aluminum.

Electroplating may include electrolytic plating or electroless plating. Electrolytic plating is to use the part to be plated as a cathode and electrolyze the electrolyte to form a layer of metal on the part to be plated. Electroless plating is a method of reducing and precipitation of metal ions in a solution to form a metal layer on the part to be plated. In some embodiments, the metal block 15a may also be formed by a method of sputtering first and then etching.

Step S38 : removing the second photoresist layer in the first predetermined region by ashing.

After the ashing is completed, the seed layer in the first predetermined region is removed by dry etching or wet etching.

The upper surface of the metal block 15a of the first redistribution layer 15 may be flattened by a polishing process, such as chemical mechanical polishing.

It should be noted that the metal blocks 15a of the first redistribution layer 15 in this step S3 are arranged according to the design requirements, and the distribution of the first redistribution layers 15 on each of the first bare chips 11 in the different groups to be packaged 10 Can be the same or different.

In addition, in some embodiments, the first redistribution layer 15 may further include two or more layers, that is, the metal blocks 15a having two or more layers.

In the step of forming the first dielectric layer 16 , in order to prevent the plastic encapsulation layer 14 from being scratched by the process, the first dielectric layer 16 may also be formed on the portion of the front surface 14 a of the plastic encapsulation layer 14 where the first redistribution layer 15 is not formed.

The first dielectric layer 16 is an insulating material, which may be an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.

When the material of the first dielectric layer 16 is an insulating resin material, it can be a) laminated on the first redistribution layer 15 and the front surface 14a of the plastic sealing layer 14 through a lamination process, or b) coated on the first redistribution layer first The layer 15 and the front side 14a of the molding layer 14 are post-cured, or c) cured on the first redistribution layer 15 and the front side 14a of the molding layer 14 by an injection molding process.

When the material of the first dielectric layer 16 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the first redistribution layer 15 and the front surface 14a of the plastic sealing layer 14 through a deposition process.

Compared with the inorganic material, the tensile stress of the insulating resin material is smaller, which can prevent the plastic package from warping when the first dielectric layer 16 is formed in a large area.

The first dielectric layer 16 may include one or more layers.

Then, referring to step S4 in FIG. 2 and as shown in FIG. 8 , the carrier plate 2 is removed to expose the active surface 12a of each second die 12, the second end 13b of each conductive post 13 and the back surface 14b of the plastic encapsulation layer 14; A second redistribution layer 17 is formed on the active surface 12a of each second die 12, the second end 13b of each conductive pillar 13, and the back surface 14b of the plastic encapsulation layer 14, and the second redistribution layer 17 is used to align the second Each second pad 121 of the bare chip 12 performs circuit layout, and the second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive pillars 13 in the group.

Referring to FIG. 8 , after the carrier plate 2 is removed, the support plate 3 may be disposed on the first dielectric layer 16 .

The removal method of the carrier plate 2 may be the existing removal methods such as laser lift-off and UV irradiation.

The support plate 3 may play a supporting role in the subsequent steps of forming the second redistribution layer 17 , and/or forming the pins 18 , and/or forming the second dielectric layer 19 .

The support plate 3 is a rigid plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.

For the method of forming the metal blocks 17 a in the second redistribution layer 17 , reference may be made to the method of forming the metal blocks 15 a in the first redistribution layer 15 . The layout of the second redistribution layer 17 may be determined according to a predetermined layout. The second redistribution layer 17 may include one layer, two layers, or more than two layers.

Next, referring to step S5 in FIG. 2 and as shown in FIG. 8 , leads 18 are formed on the second redistribution layer 17 and a second dielectric layer 19 at least embedded in the second redistribution layer 17 is formed, and the leads 18 are exposed. outside the second dielectric layer 19 .

This step S5 may further include steps S51-S55.

Step S51 : forming a third photoresist layer on the metal block 17 a , the insulating layer (not shown) between the adjacent second pads 121 and the back surface 14 b of the plastic sealing layer 14 .

In this step S51, in an optional solution, the formed third photoresist layer may be a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and attached to the metal block 17 a , the insulating layer between the adjacent second pads 121 and the back surface 14 b of the plastic sealing layer 14 . In other alternatives, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.

Step S52 : exposing and developing the third photoresist layer, and retaining the photoresist in the second predetermined area. The second predetermined area is complementary to the area where the conductive bump 181 is to be formed.

In this step S52, the third photoresist layer is patterned. In other alternatives, other easily removable sacrificial materials can also be used to replace the third photoresist layer.

Step S53 : filling a metal layer in a complementary region of the second predetermined region to form conductive bumps 181 .

This step S53 can be completed by an electroplating process. The process of electroplating copper or aluminum is relatively mature. Before electroplating copper or aluminum, a seed layer (Seed Layer) can also be deposited by physical vapor deposition or chemical vapor deposition as a power supply layer.

Step S54 : removing the third photoresist layer in the second predetermined region by ashing.

The conductive bumps 181 can be flattened on the upper surface by a polishing process, such as chemical mechanical polishing.

Step S55 : Referring to FIG. 8 , forming a second dielectric layer 19 on the conductive bumps 181 , the metal blocks 17 a , the insulating layer between the adjacent second pads 121 and the back surface 14 b of the plastic sealing layer 14 ; Two dielectric layers 19 until the conductive bumps 181 are exposed.

In some embodiments, it is also possible to: firstly form the second dielectric layer 19 burying the second redistribution layer 17 ; thin the second dielectric layer 19 until the uppermost metal block 17 a of the second redistribution layer 17 is exposed ; Next, a conductive bump 181 is formed on the metal block 17a.

For the material and formation method of the second dielectric layer 19 , reference may be made to the material and formation method of the first dielectric layer 16 .

In the step of forming the second dielectric layer 19 , in order to prevent the plastic sealing layer 14 from being scratched, the second redistribution layer 17 may also be formed on the back surface 14 b of the plastic sealing layer 14 between the adjacent groups of the components to be packaged 10 where the second redistribution layer 17 is not formed. The second dielectric layer 19 .

The second dielectric layer 19 may include one or more layers.

After the conductive bumps 181 are fabricated, as shown in FIG. 8 , the conductive bumps 181 serve as the pins 18 .

In some embodiments, after the conductive bumps 181 are exposed, an anti-oxidation layer is also formed on the conductive bumps 181 .

The anti-oxidation layer may include: b1) a tin layer, or b2) a bottom-up stack of nickel layers and gold layers, or b3) a bottom-up stack of nickel layers, palladium layers, and gold layers. The anti-oxidation layer can be formed by an electroplating process. The material of the conductive bumps 181 can be copper, and the above-mentioned anti-oxidation layer can prevent the copper from being oxidized, thereby preventing the deterioration of the electrical connection performance.

In some embodiments, after the conductive bumps 181 are exposed, solder balls are formed on the conductive bumps 181 for flip-chipping of the multi-chip 3D package structure 1 (see FIG. 1 ).

After the lead 18 is formed, as shown in FIG. 9 , the support plate 3 is removed.

The removal method of the support plate 3 may be a conventional removal method such as laser lift-off and UV irradiation.

After that, referring to step S6 in FIG. 2 , FIG. 9 and FIG. 1 , a plurality of multi-chip 3D packaging structures 1 are formed by cutting, and each multi-chip 3D packaging structure 1 includes a group of components to be packaged 10 .

After the above steps, the first die 11 and the second die 12 in a group of components to be packaged 10 can be connected to external circuits through pins 18 , so that the performance of the multi-chip 3D packaging structure 1 is reliable. In addition, the layout of the conductive pillars 13 , the first redistribution layer 15 and the second redistribution layer 17 is free and flexible, and is not limited by the size of the substrate.

FIG. 10 is a schematic cross-sectional structural diagram of a multi-chip 3D packaging structure according to a second embodiment of the present application. Referring to FIG. 10 , the multi-chip 3D packaging structure 2 in this embodiment includes:

The plastic encapsulation layer 14 covers the first die 11 and the second die 12 , the front surface 14 a of the plastic encapsulation layer 14 exposes the exposed portion of the protective layer 110 and the first pad 111 , and the back surface 14 b of the plastic encapsulation layer 14 exposes the second die 12 The active surface 12a of the plastic encapsulation layer 14 has a conductive plug 20. The conductive plug 20 includes opposite first ends 20a and second ends 20b. The conductive plugs 20 are located on the sides of the first die 11 and the second die 12. side;

The first redistribution layer 15 is located on the protective layer 110 , the exposed portion of the first pad 111 , the first end 20 a of the conductive plug 20 and the front surface 14 a of the plastic encapsulation layer 14 , and is used for conducting circuits on each of the first pads 111 layout, the first redistribution layer 15 is led to the back surface 14b of the plastic sealing layer 14 through the conductive plug 20;

the first dielectric layer 16, burying the first redistribution layer 15;

The second redistribution layer 17 is located on the active surface 12a of the second die 12, the second end 20a of the conductive plug 20 and the back surface 14b of the plastic sealing layer 14, and is used for circuit layout of each second pad 121. The second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive plug 20;

The pin 18 is connected to the second redistribution layer 17;

The second dielectric layer 19 at least embeds the second redistribution layer 17 and exposes the pins 18 .

It can be seen that the multi-chip 3D packaging structure 2 in the second embodiment is substantially the same as the multi-chip 3D packaging structure 1 in the first embodiment, and the only difference is that the conductive plugs 20 replace the conductive posts 13 .

The conductive material in the conductive plug 20 may be a metal with good electrical conductivity such as copper and aluminum. The number of the conductive plugs 20 may be one, two or more.

An embodiment of the present application provides a manufacturing method of the multi-chip 3D package structure 2 in FIG. 10 . FIG. 11 is a flowchart of a production method. 12 to 18 are schematic diagrams of intermediate structures corresponding to the process in FIG. 11 .

First, referring to step S1 ′ in FIG. 11 , FIG. 12 and FIG. 13 , a carrier board 2 and a plurality of groups of components to be packaged 10 ′ supported on the carrier board 2 are provided. Each group of components to be packaged 10 ′ includes: The first die 11 and the second die 12 , wherein the first die 11 includes a plurality of first pads 111 , the first pads 111 are located on the active surface 11 a of the first die 11 , and the active The surface 11a is covered with the protective layer 110, the second die 12 includes a plurality of second pads 121, the second pads 121 are located on the active surface 12a of the second die 12, and the active surface 12a of the second die 12 faces the carrier 2 . 12 is a top view of the carrier board and multiple groups of components to be packaged; FIG. 13 is a cross-sectional view along line BB in FIG. 12 .

It can be seen that the step S1 ′ is substantially the same as the step S1 in the first embodiment, and the difference is only that the conductive column 13 is missing from the to-be-packaged component 10 ′ relative to the to-be-packaged component 10 .

For the same or similar structures and manufacturing methods in the steps of the manufacturing methods of the second embodiment and the first embodiment, please refer to the corresponding parts of the foregoing embodiments, and this embodiment focuses on the differences.

Next, as shown in step S2 ′ in FIG. 11 and FIG. 14 , a plastic encapsulation layer 14 is formed on the surface of the carrier board 2 to embed each group of components to be packaged 10 ′; as shown in FIG. 15 , the plastic encapsulation layer 14 is thinned until the The protective layer 110 on the active surface 11a of each first die is exposed.

For related content, please refer to the relevant part of step S2 above.

Next, referring to step S3 ′ in FIG. 11 and as shown in FIG. 16 , an opening 110 a is formed in the protective layer 110 to expose at least part of the first pad 111 ; the exposed part of the protective layer 110 and the first pad 111 is formed. And a first redistribution layer 15 is formed on the front surface 14a of the plastic packaging layer 14, and the first redistribution layer 15 is used for circuit layout of each first pad 111 of the first die 11 in the group; The first dielectric layer 16 of the wiring layer 15 .

For related content, please refer to the relevant part of step S3 above.

After that, referring to step S4 ′ in FIG. 11 and FIG. 17 , the carrier plate 2 is removed to expose the active surface 12 a of each second die 12 and the back surface 14 b of the plastic sealing layer 14 ; the back surface 14 b of the plastic sealing layer 14 is in the plastic sealing layer. Conductive plugs 20 are formed in 14 to lead the first redistribution layer 15 to the back side 14b of the plastic encapsulation layer 14, and the conductive plugs include opposite first ends 20a and second ends 20b; A second redistribution layer 17 is formed on the surface 12a, the second end 20b of each conductive plug 20, and the back surface 14b of the plastic encapsulation layer 14, and the second redistribution layer 17 is used to align the second redistribution layers of the second die 12 in the group. The pads 121 perform circuit layout, and the second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive plugs 20 in the group.

The step S4 ′ is substantially the same as the step S4 in the first embodiment, and the only difference is that the step of forming the conductive plug 20 is added. When the material of the plastic encapsulation layer 14 is a laser-removable material, a through hole can be opened in the plastic encapsulation layer 14 by means of laser irradiation, and then a conductive material is filled in the through hole to form the conductive plug 20 . When the material of the plastic sealing layer 14 is a dry-etchable material, a through hole can be formed in the plastic sealing layer 14 by dry etching, and then a conductive material is filled in the through hole to form the conductive plug 20 .

Referring to FIG. 17 , after the carrier plate 2 is removed, the support plate 3 may be disposed on the first dielectric layer 16 .

Next, referring to step S5 in FIG. 11 and as shown in FIG. 17 , leads 18 are formed on the second redistribution layer 17 and a second dielectric layer 19 at least embedded in the second redistribution layer 17 is formed, and the leads 18 are exposed. outside the second dielectric layer 19 .

This step S5 is the same as the step S5 in the first embodiment.

Then, referring to step S6 ′ in FIG. 11 , as shown in FIG. 18 and FIG. 10 , a plurality of multi-chip 3D packaging structures 2 are formed by cutting, and each multi-chip 3D packaging structure 2 includes a group of components to be packaged 10 ′.

This step S6 ′ is substantially the same as the step S6 in the first embodiment, the only difference is that each multi-chip 3D package structure 2 includes a conductive plug 20 .

Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be based on the scope defined by the claims.

Claims

A multi-chip 3D packaging structure, comprising:

a first die and a second die, the first die includes a plurality of first pads, the first pads are located on the active surface of the first die, and the second die includes a plurality of second pads a pad, the second pad is located on the active surface of the second die, and the first die and the second die are arranged back-to-back;

a protective layer covering the active surface of the first die, the protective layer exposing at least part of the first pad;

a conductive column, located on the side of the first die and the second die, the conductive column includes a first end and a second end opposite to each other;

a plastic encapsulation layer, covering the first die, the second die and the conductive pillar, the front surface of the plastic encapsulation layer exposes the protective layer, the exposed part of the first pad and the conductive pillar The first end of the plastic encapsulation layer exposes the active surface of the second die and the second end of the conductive column;

A first redistribution layer is located on the protective layer, the exposed portion of the first pad, the first end of the conductive post, and the front surface of the plastic encapsulation layer, and is used for performing wiring on each of the first pads. a circuit layout, the first redistribution layer is led to the back of the plastic sealing layer through the conductive post, and the first redistribution layer includes one or more layers;

a first dielectric layer, burying the first redistribution layer;

The second redistribution layer is located on the active surface of the second die, the second end of the conductive pillar and the back surface of the plastic sealing layer, and is used for circuit layout of each of the second pads, and the The second redistribution layer is electrically connected to the first redistribution layer through the conductive pillar, and the second redistribution layer includes one or more layers;

a pin, connected to the second redistribution layer;

The second dielectric layer at least embeds the second redistribution layer, and the pins are exposed outside the second dielectric layer.
A multi-chip 3D packaging structure, comprising:

a first die and a second die, the first die includes a plurality of first pads, the first pads are located on the active surface of the first die, and the second die includes a plurality of second pads a pad, the second pad is located on the active surface of the second die, and the first die and the second die are arranged back-to-back;

a protective layer covering the active surface of the first die, the protective layer exposing at least part of the first pad;

a plastic encapsulation layer, covering the first die and the second die, the front surface of the plastic encapsulation layer exposes the protective layer and the exposed part of the first pad, the On the active surface of the second die, the plastic encapsulation layer has conductive plugs, and the conductive plugs are located on the sides of the first die and the second die;

a first redistribution layer, located on the protective layer, the exposed portion of the first pad, one end of the conductive plug, and the front surface of the plastic encapsulation layer, and used for conducting circuits on each of the first pads layout, the first redistribution layer is led to the back of the plastic sealing layer through the conductive plug, and the first redistribution layer includes one or more layers;

a first dielectric layer, burying the first redistribution layer;

The second redistribution layer is located on the active surface of the second die, the other end of the conductive plug, and the back surface of the plastic packaging layer, and is used for circuit layout of each of the second pads, and the The second redistribution layer is electrically connected to the first redistribution layer through the conductive plug, and the second redistribution layer includes one or more layers;

a pin, connected to the second redistribution layer;

The second dielectric layer at least embeds the second redistribution layer, and the pins are exposed outside the second dielectric layer.
The multi-chip 3D package structure according to claim 1, wherein there are a plurality of the conductive pillars distributed on a plurality of sides of the first die and the second die.
A multi-chip 3D package structure according to any preceding claim, wherein the second die is a control die for controlling the first die.
The multi-chip 3D package structure according to any one of the preceding claims, wherein, in the stacking direction of the first die and the second die, the orthographic projection area of the second die is larger than that of the first die. The orthographic projected area of a die.
The multi-chip 3D package structure according to any one of the preceding claims, wherein the material of the protective layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material ; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
A method for manufacturing a multi-chip 3D packaging structure, comprising:

A carrier board and at least one group of components to be packaged carried on the carrier board are provided, and each group of the components to be packaged includes:

The first die and the second die are arranged back-to-back, the first die includes a plurality of first pads, the first pads are located on the active surface of the first die, and the first die is located on the active surface of the first die. the active surface is covered with a protective layer, the second die includes a plurality of second pads, the second pads are located on the active surface of the second die; and

a conductive column, the conductive column includes opposite first ends and second ends;

Wherein, the active surface of the second die and the second ends of the conductive pillars face the carrier, and the conductive pillars are located on the sides of the first die and the second die;

A plastic sealing layer is formed on the surface of the carrier board to embed the to-be-packaged component; the plastic sealing layer is thinned until the protective layer and the first ends of the conductive pillars are exposed;

An opening is formed in the protective layer to expose at least a portion of the first pad; in the protective layer, the exposed portion of the first pad, the first end of the conductive post, and the plastic encapsulation layer A first redistribution layer is formed on the front side of the surface, the first redistribution layer is used for circuit layout of each of the first pads, and the first redistribution layer is led to the plastic sealing layer through the conductive posts. On the back side, the first redistribution layer includes one or more layers; forming a first dielectric layer burying the first redistribution layer;

removing the carrier plate to expose the active surface of the second die, the second end of the conductive pillar and the backside of the plastic encapsulation layer; on the active surface of the second die, the first A second redistribution layer is formed on both ends and the backside of the plastic encapsulation layer, the second redistribution layer is used for circuit layout of each of the second pads, and the second redistribution layer passes through the conductive pillars is electrically connected to the first redistribution layer, and the second redistribution layer includes one or more layers;

Pins are formed on the second redistribution layer and a second dielectric layer at least embedded in the second redistribution layer is formed, and the pins are exposed outside the second dielectric layer.
The method for fabricating a multi-chip 3D package structure according to claim 7, wherein a group of the components to be packaged includes a plurality of the conductive pillars, and the plurality of conductive pillars are distributed on the first die and the Multiple sides of the second die.
The method for fabricating a multi-chip 3D package structure according to claim 7 or 8, wherein the components to be packaged carried by the carrier board are in multiple groups, and the first redistribution layer is used for aligning the components in the group. Each first pad of the first bare chip performs circuit layout, and the first redistribution layer is led to the back of the plastic packaging layer through the conductive pillars in the group; the second redistribution layer is used to The circuit layout is performed on each second pad of the second die, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive pillars in the group; the pins are connected to the After the second dielectric layer is formed, a plurality of multi-chip 3D packaging structures are formed by cutting, and each of the multi-chip 3D packaging structures includes a group of the to-be-packaged components.
The method for manufacturing a multi-chip 3D package structure according to any one of claims 7 to 9, wherein the material of the protective layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
The method for fabricating a multi-chip 3D package structure according to any one of claims 7 to 10, wherein the first redistribution layer includes two or more layers; and/or the second redistribution layer includes Two or more layers.
A method for manufacturing a multi-chip 3D packaging structure, comprising:

A carrier board and at least one group of components to be packaged carried on the carrier board are provided, each group of the components to be packaged includes: a first die and a second die arranged back-to-back, and the first die includes a plurality of first die a pad, the first pad is located on the active surface of the first die, the active surface of the first die is covered with a protective layer, the second die includes a plurality of second pads, the first die Two bonding pads are located on the active surface of the second die, and the active surface of the second die faces the carrier;

Forming a plastic encapsulation layer to embed the to-be-packaged component on the surface of the carrier board; thinning the plastic encapsulation layer until the protective layer is exposed;

An opening is formed in the protective layer to expose at least a portion of the first pad; a first redistribution layer is formed on the protective layer, the exposed portion of the first pad and the front surface of the plastic encapsulation layer , the first redistribution layer is used for circuit layout of each of the first pads, and the first redistribution layer includes one or more layers; the first redistribution layer is formed to embed the first redistribution layer. dielectric layer;

removing the carrier plate to expose the active surface of the second die and the backside of the plastic encapsulation layer; forming conductive plugs in the plastic encapsulation layer through the backside of the plastic encapsulation layer to rewire the first layer leading to the backside of the plastic encapsulation layer, the conductive plug includes opposing first and second ends; on the active side of the second die, the second end of the conductive plug and the plastic encapsulation A second redistribution layer is formed on the backside of the layer, the second redistribution layer is used for circuit layout of each of the second pads, and the second redistribution layer is connected to the first through the conductive plug. The redistribution layer is electrically connected, and the second redistribution layer includes one or more layers;

Pins are formed on the second redistribution layer and a second dielectric layer at least embedded in the second redistribution layer is formed, and the pins are exposed outside the second dielectric layer.
The method for fabricating a multi-chip 3D package structure according to claim 12 , wherein a plurality of the conductive plugs are correspondingly formed in a set of components to be packaged, and the plurality of conductive plugs are distributed on the first die and all the conductive plugs. multiple sides of the second die.
The method for fabricating a multi-chip 3D package structure according to claim 12 or 13, wherein the components to be packaged carried by the carrier board are in multiple groups, and the first redistribution layer is used for aligning the components in the group. Each first pad of the first bare chip performs circuit layout, and the first redistribution layer is led to the back of the plastic sealing layer through the conductive plugs in the group; the second redistribution layer is used to align the group The circuit layout is performed on each second pad of the second die in the second redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive plug in the group; the pins are connected to the first redistribution layer. After the second dielectric layer is formed, a plurality of multi-chip 3D packaging structures are formed by cutting, and each of the multi-chip 3D packaging structures includes a group of components to be packaged.
The method for manufacturing a multi-chip 3D package structure according to any one of claims 12 to 14, wherein the material of the protective layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.