CN116469832A - Board level packaging method - Google Patents

Board level packaging method Download PDF

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Publication number
CN116469832A
CN116469832A CN202310137908.6A CN202310137908A CN116469832A CN 116469832 A CN116469832 A CN 116469832A CN 202310137908 A CN202310137908 A CN 202310137908A CN 116469832 A CN116469832 A CN 116469832A
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China
Prior art keywords
layer
metal seed
substrate
seed layer
rewiring
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CN202310137908.6A
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Chinese (zh)
Inventor
杜玲玲
颜国秋
上官昌平
黄剑
敖伟平
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Shanghai Meadville Science and Technology Co Ltd
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Shanghai Meadville Science and Technology Co Ltd
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Priority to CN202310137908.6A priority Critical patent/CN116469832A/en
Publication of CN116469832A publication Critical patent/CN116469832A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention provides a board-level packaging method, which comprises the following steps: s1: preparing a substrate; s2: forming a metal seed layer on the surface of the substrate by using a physical vapor deposition process to be electrically connected with the chip; s3: coating a resist layer on the metal seed layer by adopting a slit coating process and carrying out photoetching; s4: developing the resist layer subjected to photoetching by adopting a conveying type dipping bath developing process to define a rewiring layer pattern; s5: forming a metal main body layer on the patterned resist layer by adopting an electroplating process, wherein the metal main body layer is electrically connected with the metal seed layer; s6: etching the metal seed layer according to the patterned resist layer to form a rewiring layer, and removing the residual resist layer; s7: a solder mask layer is formed on the rewiring layer and solder balls electrically connected with the rewiring layer are implanted. The invention can manufacture finer circuits and realize thinner packaging. And is beneficial to reducing the use amount of chemicals and reducing the generation of wastewater. In addition, the production efficiency is improved, and the packaging cost is reduced.

Description

Board level packaging method
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to back-end packaging, and particularly relates to a board-level packaging method.
Background
With the application of heterogeneous integration technology of electronic packaging, the development of high-end carrier boards is promoted to miniaturization and integration, and a series of new technologies and products are promoted in the field of substrates, such as embedded chip boards (eSIP), FC-BGA boards, POP packaging modules based on embedded chips, PLP (Panel Level Package, panel level packaging) modules based on embedded chips and RDL (rewiring layer). At present, the chip embedding board has completed the development of related technologies and products and enters a stage of mass production. The PLP module based on the embedded chip and the RDL is formed by stacking the RDL materials on the basis of the embedded chip to form a panel-level-scale higher-density interconnection layer, and the surface sealing and the segmentation are completed to form the fan-out type heterogeneous integrated module exceeding the mole, so that the PLP module has higher added value of products.
To realize a PLP module based on a buried chip and RDL, RDL fabrication is indispensable. More importantly, PLP modules based on embedded chips and RDLs are assembled on a substrate, which is also subject to high density and miniaturization requirements. The technical capabilities of existing products, including the fabrication of ultra-fine lines in particular, are also in need of further improvement. To reduce the cost of fan-out packages and expand their application further, the industry has focused the goal of FOPLP (fan-out board level package) on L/S (Line/Space) between 1/1 μm and 8/8 μm, which is the technical difference (Gap) between industry upstream board factories and downstream OSAT (outsourcing assembly and testing) factories. Compared with silicon-based FOWLP (fan-out wafer level package), the organic carrier-based FOPLP has a natural panel-level infrastructure, is low in cost in all aspects, and has a higher market prospect.
The carrier board of FOPLP in industry is generally a material such as EMC plastic layer of embedded chip, while the pattern transfer material used for manufacturing fine circuit is a thinner dry film, and the manufacturing process is generally as follows: forming a seed layer, vacuum film pasting, exposing, developing, electroplating, removing the film, etching the seed layer, and thus forming a required circuit. However, the inventor finds that when the technology is applied to the encapsulation of the eSIP organic carrier based on the embedded chip through a large number of experiments, the ultra-fine circuit cannot be manufactured due to the fact that the performance of a thin dry film (less than or equal to 15 μm) can reach the manufacturing requirement of the fine circuit below 8/8 μm at present, and the like, so that the requirements of high density and miniaturization encapsulation are difficult to meet. Meanwhile, the existing board-level packaging method also has the problems of large consumption of chemicals, environmental pollution and the like.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a board-level packaging method for solving the problems that the existing board-level packaging method for forming a seed layer, vacuum film-attaching, exposing, developing, electroplating, film-removing, etching the seed layer can only meet the packaging requirements of the FOPLP carrier board based on materials such as EMC plastic layer of embedded chip, but cannot meet the ultra-fine circuit manufacturing in board-level packaging based on organic carrier board, and cause environmental pollution.
To achieve the above and other related objects, the present invention provides a board level packaging method, comprising the steps of:
s1: preparing a substrate, wherein a chip is embedded in the substrate;
s2: forming a metal seed layer on the surface of the substrate by using a physical vapor deposition process, and electrically connecting the metal seed layer with the chip through the hole;
s3: coating a resist layer on the metal seed layer by adopting a slit coating process and carrying out photoetching;
s4: developing the resist layer after photoetching by adopting a transmission type dipping bath developing process to define a rewiring layer pattern in the resist layer;
s5: forming a metal main body layer on the patterned resist layer by adopting an electroplating process, wherein the metal main body layer is electrically connected with the metal seed layer;
s6: etching the metal seed layer according to the patterned resist layer to form a rewiring layer, and removing the residual resist layer;
s7: a solder mask layer is formed on the rewiring layer and solder balls electrically connected with the rewiring layer are implanted.
Optionally, the substrate includes an organic carrier, and the preparation process of the substrate sequentially includes: providing an organic carrier, making a pattern on the organic carrier, laser cutting a through groove of a buried chip, sticking an adhesive tape at the bottom, burying the chip, laminating a plastic packaging material to fill a space around the chip, turning the organic carrier and tearing the adhesive tape, enabling the active surface of the chip to face upwards, coating or vacuum pressing a dielectric layer, and forming holes in the dielectric layer.
More optionally, the plastic package material is ABF material, the dielectric layer is photosensitive dielectric layer, and the method of forming holes in the dielectric layer is photolithography development.
Optionally, the metal seed layer includes an adhesion layer on a surface of the substrate and a metal seed layer on a surface of the adhesion layer.
More optionally, the adhesion layer comprises a titanium layer and/or a titanium nitride layer, and the metallic seed layer comprises a copper layer; the thickness of the adhesion layer is 50nm-100nm, and the thickness of the copper layer is 100nm-500nm.
Optionally, the etching method of step S6 includes wet-etching the copper layer and wet-etching or dry-etching the adhesion layer.
More optionally, the method of wet-method flash etching the copper layer of the metal seed layer is a method of etching by hydrogen peroxide and acid, and the method of wet-method flash etching the titanium layer of the adhesion layer is a method of etching by HF or NaOH+H 2 O 2 And alkaline mixture thereof, and the dry etching method for the titanium layer of the adhesion layer is to etch by adopting plasma or active ions including argon.
Optionally, the lithography in step S3 is LDI lithography using I lines.
Optionally, step S7 includes manufacturing a solder mask by using any one of a film-sticking method, a roller-coating method and a screen printing method, exposing, developing and post-curing the solder mask at a position where the solder balls are to be implanted, and finally implanting the solder balls at the position where the solder balls are to be implanted.
Optionally, the board level packaging method includes a step of repeating steps S2 to S6 several times to form two or more rewiring layers stacked up and down and electrically connected.
As described above, the board-level packaging method of the present invention has the following advantageous effects: the invention can manufacture finer circuits and realize thinner packaging through improved process design. And is beneficial to reducing the use amount of chemicals and reducing the generation of wastewater. In addition, the production efficiency is improved, and the packaging cost is reduced.
Drawings
Fig. 1 shows a flowchart of a board-level packaging method provided by the invention.
FIG. 2 is a schematic diagram of the structure of the first dielectric layer on the organic carrier after photo-induced hole formation.
FIG. 3 is a schematic view showing the grain and surface roughness of the copper layer.
FIG. 4 is a schematic diagram showing the grain and surface roughness of a metal seed layer deposited by a physical vapor process.
Fig. 5 is a schematic diagram of the structure after physical vapor deposition.
Fig. 6 shows a schematic diagram of a slot coating process.
Fig. 7 shows a schematic structure after slit coating.
Fig. 8 is a schematic view of the first resist layer after coating.
Fig. 9 is a schematic diagram showing the structure of the first resist layer after lithography and development.
Fig. 10 is a schematic diagram showing a structure of forming a first rewiring layer after electroplating.
Fig. 11 is a schematic view showing a structure after removing the first resist layer.
Fig. 12 is a schematic view of the structure after removing the first metal seed layer.
Fig. 13 is a schematic structural diagram of the second dielectric layer, the second metal seed layer, and the second rewiring layer after formation.
Fig. 14 is a schematic view of the structure of the solder mask layer and the implanted solder balls.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. In order to make the illustration as concise as possible, not all structures are labeled in the drawings.
Please refer to fig. 1 to 14.
As shown in fig. 1, the present invention provides a board level packaging method, which includes the following steps:
s1: preparing a substrate, wherein a chip is embedded in the substrate;
s2: forming a metal seed layer on the surface of the substrate by using a physical vapor deposition process, and electrically connecting the metal seed layer with the chip through the hole;
s3: coating a resist layer on the metal seed layer by adopting a slit coating process and carrying out photoetching;
s4: developing the resist layer after photoetching by adopting a transmission type dipping bath developing process to define a rewiring layer pattern in the resist layer;
s5: forming a metal main body layer on the patterned resist layer by adopting an electroplating process, wherein the metal main body layer is electrically connected with the metal seed layer;
s6: etching the metal seed layer according to the patterned resist layer to form a rewiring layer, and removing the residual resist layer;
s7: a solder mask layer is formed on the rewiring layer and solder balls electrically connected with the rewiring layer are implanted.
The board-level packaging method provided by the invention will be further described with reference to the accompanying drawings.
First, step S1 is performed to prepare a substrate 2, and a chip 17 is embedded in the substrate 2.
The packaging method provided by the invention is suitable for board-level packaging based on various material substrates, such as board-level packaging based on inorganic substrates, and the advantages are more remarkable only when the packaging method is used for board-level packaging based on organic boards. Because of the advantages of good heat resistance, high dimensional stability and the like of the inorganic carrier, the inorganic carrier is commonly adopted in the industry at present when the board-level packaging of the fine circuit is required to be manufactured, and the fine circuit manufacturing based on the organic carrier is not used much. The inventor finds that when a fine circuit below 8/8 mu m is required to be manufactured on an organic carrier, the conventional method of forming a seed layer, vacuum film pasting, exposure, development, electroplating, film removing and etching the seed layer is difficult to meet the requirement, and the reason comprises that the conventional dry film process is difficult to be thin. Therefore, the inventor provides an improvement scheme of the application through a great deal of experimental study on the basis of the prior art. That is, the substrate 2 provided in the present application may be an inorganic carrier and a composite substrate, but is an organic carrier in a more preferred example. The organic carrier has the advantages of lower dielectric constant, suitability for high-frequency signal transmission, easiness in processing, light weight and the like, and can meet the current requirements on high density and miniaturization of packaging devices, but the difficulty of manufacturing fine circuits on the organic carrier by adopting a traditional method is relatively high, and the problem can be well solved.
In the case where the substrate 2 used is an organic carrier, the preparation process of the substrate sequentially includes: providing an organic carrier, i.e. a core board, patterning the organic carrier, laser cutting through slots in the buried chip, taping the bottom, embedding the chip 17, laminating the plastic packaging material 18 to fill the space around the chip 17, flipping the organic carrier and tearing the tape, placing the active side of the chip 17 up, coating or vacuum laminating the dielectric layer 19, and forming holes, e.g. punching, in the dielectric layer 19 to form holes 20, more specifically, holes, e.g. using a laser hole forming or lithography process, the resulting structure is shown in fig. 2.
The core board is also called a copper-clad board, the middle layer resin 15 of the core board can be polyimide resin, epoxy resin, polypropylene resin, polyethylene, polyether ketone resin, bismaleimide modified triazine resin and other materials, the surface of the core board is provided with metal circuits 16, and the metal circuits 16 are usually copper foils, such as calendered copper foils or electrolytic copper foils. When attaching the chip 17, the active surface of the chip 17 is close to one side of the tape. The active surface of the chip is typically provided with a plurality of metal pads exposed on the surface of the substrate for subsequent extraction of the electrical signals of the chip.
The dielectric layer 19 is also called an insulating layer or a dielectric layer, and is a material that needs to be finally left in the package substrate, and the dielectric layer 19 used in this embodiment may be a dry film material layer or a wet film photoresist material layer, for example, a material layer of polyimide, phenolic resin, epoxy resin, or the like. If a photoresist layer is used, the dielectric layer 19 is applied by Slit coating, and if a dry film is used, it is prepared by vacuum lamination. The dry film is preferably formed by laser drilling and the photoresist is preferably formed by photolithographic development. In a preferred example of the present application, the dielectric layer 19 is a photosensitive dielectric layer, such as a photoresist layer, the method of forming holes in the dielectric layer 19 is photolithographic development, and the molding compound 18 is preferably ABF (Ajinomoto enhanced film) material. In addition, holes can be formed by adopting a vacuum film pressing mode.
After the substrate is ready, step S2 is performed: a Physical Vapor Deposition (PVD) process is used to form a metal seed layer 21 on the substrate surface, the metal seed layer 21 being electrically connected to the chip 17 through the blind via 31, the structure resulting from this step being shown with reference to fig. 5.
In the existing board-level package, a chemical copper deposition (copper for short) mode is commonly used for preparing the metal seed layer. Although the efficiency of electroless copper deposition is higher, the thinnest copper layer can only be prepared to be 1 mu m, so that only circuits with line width spacing larger than 8/8 mu m can be manufactured. In the application, a Physical Vapor Deposition (PVD) mode, particularly a sputtering deposition mode, can be used for manufacturing a metal seed layer with smaller copper grain size, and is more suitable for manufacturing a circuit with a line width spacing smaller than 8/8 mu m. And, referring to fig. 3 and 4, the roughness 14 of the surface of the copper layer deposited using the sputter deposition process, while having a smaller overall roughness than the roughness 11 of the surface of the copper layer 10, is more dense, facilitating the subsequent electroplating of the combination of the copper layer as the metal bulk layer and the copper layer as the metal seed layer.
In a preferred example, the metal seed layer 21 includes an adhesion layer 12 on the surface of the substrate 9 and a metal seed layer 13 on the surface of the adhesion layer 12, where the adhesion layer 12 may include, but is not limited to, a titanium layer and/or a titanium nitride layer, and the material of the metal seed layer 13 is preferably the same as that of the metal bulk layer, and may be, but is not limited to, a copper layer. For example, a titanium layer of 50nm to 100nm is first formed on the surface of the substrate 9, and then a copper layer of 100nm to 500nm is formed on the titanium layer. In a specific example, the titanium layer as the adhesion layer 12 is 100nm and the copper layer as the metallic seed layer 13 is 300nm.
Wherein, the titanium layer is used as an adhesion layer to increase the adhesion between the substrate 9 and the metal seed layer, and the copper layer can adjust the electroplating resistance, so that the copper on the surface of the electroplated substrate is more uniform. In the existing board-level packaging, electroless copper is generally adopted to prepare a metal seed layer, but electroless copper belongs to a wet method, and not only does the previous process require wet desmeare (decontamination) to increase the surface roughness of a substrate, but also a large amount of waste water is generated, a large amount of chemicals are required to be consumed, and the increase of the surface roughness of the substrate is very unfavorable for the flash erosion of a subsequent fine circuit. Because the rougher the copper layer surface, the more one-time biting is caused, the larger side etching is caused at the bottom of the circuit, and the circuit cannot be ultra-fine. In comparison, the metal seed layer manufactured by adopting the physical vapor deposition process is environment-friendly, and the prepared metal seed layer is smaller in grain size and surface roughness and can achieve smaller line width spacing.
In other examples, the metal seed layer may also be titanium, copper, titanium tungsten alloy, or a combination thereof.
And (3) after the metal seed layer is manufactured, obtaining a prefabricated structure 2, executing a step S3, coating a resist layer 8 on the metal seed layer by adopting a slit coating process, and carrying out photoetching after vacuum drying and hot plate prebaking. Before coating, propylene Glycol Methyl Ether Acetate (PGMEA) cleaning solution can be used to clean the surface of the prefabricated structure 2, and the resist layer 8, i.e. the surface binding force between the photoresist layer and the metal seed layer on the substrate, is increased. Slit coating using wet photoresist belongs to a wet process, unlike a dry film-sticking process. Compared with dry film preparation by dry method, the wet coated resist layer can be thinner and has better uniformity. At present, the thinnest thickness of the dry film is 15 mu m, the uniformity is more than 10%, and the uniformity of the resist layer 8 manufactured by using the slit coating mode is within 5%, and the thickness can be less than or equal to 10 mu m. The resist layer is thinner and more uniform, and the resolution of line width space is higher when exposure is performed by matching with a photoetching machine with higher overlay precision.
In particular, the principle and process of slot coating is shown with reference to fig. 6 and 7. As shown in fig. 6, two photoresist containing tanks 5 and 7 containing photoresist (resist) are arranged on two sides of a carrier 1, a prefabricated structure 2 is fixed on the carrier 1 through a vacuum adsorption 3, and two slit nozzles 4 and 6 capable of sucking the photoresist by vacuum pump are arranged right above the photoresist containing tanks. In the application, the nozzles 4 are spaced from the pre-formed structure 2, i.e. from the substrate, wherein one of the nozzles 4 is automatically moved from one side to above the substrate 9, the vacuum is released during the movement to spray the photoresist, the nozzle is moved to the other end and then returned to the original position, thereby completing the application of the resist layer 8, and the structure after completing the application can be described with reference to fig. 7 and 8. In mass production, the nozzles 4 and 6 are used in turn, so that the coating efficiency can be improved. After coating, the substrate was placed in a vacuum oven for vacuum drying. The vacuum drying can remove bubbles on the photoresist layer and the surface of the substrate and dust around the substrate. If bubbles remain in the photoresist layer, the photoresist layer can bulge and crack during the subsequent prebaking of the hot plate, and the appearance and uniformity are damaged. And (3) curing the photoresist after drying, wherein the curing process can be performed on a heating platform, and parameters such as curing temperature, curing time and the like can be set according to requirements. In a preferred example of the present application, the curing temperature is 90℃and the time is 5 minutes. The curing may be carried out under vacuum or under an inert gas atmosphere, preferably the latter, i.e. inert gases such as nitrogen or argon are introduced into the curing chamber during the curing process. The inert gas can protect the substrate from being polluted, and can play a good role in heat conduction, so that the heating uniformity is improved.
It should be noted that, the photoresist layer in this step is substantially different from the photoresist used as the dielectric layer in the substrate preparation process in step S1, and the photoresist as the dielectric layer is left inside the carrier mainly for forming the holes 20, and the electrical signals of the internal chip are passed through the plated blind holes 31 to the rewiring layer 24. The photoresist layer as the resist layer 22 in this step is finally removed after exposure, development and electroplating to produce the rewiring layer 24.
After the completion of the curing of the resist layer 22, pattern lithography is performed. And selecting a proper photoetching machine to carry out photoetching according to the model of the coated photoresist. Current photoresists typically require LDI (laser direct imaging) of h-line (405 nm), i-line (365 nm) or ghi-line hybrid light sources or stepper lithography. The target line width for g-line lithography is typically greater than 10 μm, while the target line width for photoresist for h-line, i-line, or ghi-line light sources is typically greater than 0.35 μm. From the standpoint of the lithography effect only, the photoresist is a preferred choice for i-line stepper. The inventor finds through experiments that the LDI lithography using i-line in this embodiment can fully meet the line width requirement, and the lithography efficiency can be significantly improved, so that the LDI lithography is preferable in this embodiment.
After the photolithography is completed, step S4 is performed, and the resist layer 22 after the photolithography is developed by using a transfer bath developing process to define a rewiring layer pattern in the resist layer 22, and the developed structure is shown in fig. 9. Unlike dry films, photoresist development typically uses 2.38% tetramethyl ammonium hydroxide (TMAH) developer, or an inorganic developer including an inorganic base. And unlike wafer level development, the present application is directed to board level packaging type products. Compared with wafer level packaging, the plate level packaging has large area and contains an organic substrate, and certain warping exists in reality, so that the inventor selects horizontal conveying type dipping bath development rather than traditional jet development. The developing mode comprises a passive opening and closing device (cutter), a carrier plate with the acceptable warping degree less than or equal to 10mm is flattened during developing, the flatness of the carrier plate is higher, the developing solution fully reacts with the photoresist, and the superfine circuit is manufactured by the subsequent process.
Step S5 is performed next: a metal bulk layer is formed on the patterned resist layer 23 using an electroplating process, such as electroplating to form a bulk copper layer, which is electrically connected to a metal seed layer.
After the development, the metal seed layer 21 at the bottom is exposed, and the plating is performed, and the structure after the plating is shown with reference to fig. 10. It can be seen that the ultra-fine circuit with smaller line width and space is manufactured through the steps. The electroplating of this step generally employs high current density, low sulfur element (< 9.6 ppm) electroplating. After electroplating, photoresist in the area of the protective metal seed layer outside the circuit is removed by using an organic stripping solution, and the structure after removing the first resist layer is shown in fig. 11. Finally, baking to remove residual water vapor in the carrier plate.
S6 is performed next: the metal seed layer is etched in the patterned resist layer 23 to form a re-wiring layer, and the remaining resist layer is removed.
After removing the first resist layer in step S6, the first metal seed layer 21 at the bottom of the line space needs to be removed, and copper on the lines of some metal body layers will be flashed at the same time, so appropriate compensation will be designed during the pattern design, and in this embodiment, compensation of about 1 μm is performed.
In a preferred example, the etching of this step is performed in two steps, first, wet etching is performed on the copper layer as the metal seed layer, and then dry etching is performed using plasma including argon or wet flash etching is performed on the titanium layer as the adhesion layer. The wet flash copper layer is preferably formed using hydrogen peroxide + acid, the acid being sulfuric acid or a weak acid. Wet etching of the titanium layer requires HF (hydrofluoric acid) or naoh+h2o2, other alkaline mixtures, and the like. The dry etching has lower efficiency, but the etching quality is higher, and the method has no pollution. The dry etching generally uses plasma or active ions for etching, and nitrogen, argon, other auxiliary gases and the like can be filled in the etching process, so that the dry etching is not limited. At this time, the first ultra-fine circuit layer is completed. For the fan-out process of this embodiment, the inner linewidth pitch is less than or equal to the outer linewidth pitch. The remaining resist layer is removed after etching to obtain a re-wiring layer 24 of the desired structure, the resulting structure being shown with reference to fig. 12.
The rewiring layer may have a single-layer structure, or may be formed by repeating steps S2 to S6 several times as shown in the present embodiment to form two or more rewiring layers stacked up and down and electrically connected, for example, as shown in fig. 13. A second metal seed layer 32 is formed, for example, by a sputter deposition process, over the first re-wiring layer 24, followed by a slot coating to form a second resist layer, followed by photolithography and transfer bath development to form the desired pattern, electroplating metal into the holes 26 formed in the resist layer, and then etching the second metal seed layer 32, thereby obtaining the second re-wiring layer 28. For more details, reference is made to the foregoing, and details are not repeated for the sake of brevity. The materials and thicknesses of the first rewiring layer 24 and the second rewiring layer 28 may be the same or different, without limitation. In other examples, the different rewiring layers may also be interconnected by other interconnect structures, such as by interposer, or a rewiring layer that is otherwise pre-fabricated on another substrate may be bonded to the structure fabricated in this embodiment to interconnect the different structures. More than two rewiring layers stacked up and down can meet the integration requirements of different devices and devices with higher density, but the quality requirements on the circuit are higher. By adopting the method provided by the embodiment, the interlayer interconnection can be effectively ensured, and the performance of the device can be ensured.
After the re-wiring layer is completed, step S7 is performed again, and a solder resist layer 29 is formed on the re-wiring layer and solder balls 30 electrically connected to the re-wiring layer are implanted, and the resulting structure is shown with reference to fig. 14. Thus, the manufacturing of the ultra-fine circuit of the board-level package based on the eSIP organic board is completed.
In one example, the step may specifically include making the solder mask 29 (also called green oil) by any one of film pasting, roller coating and screen printing, preferably by wet coating such as screen printing, exposing, developing and post-curing, opening the window of the solder mask 29 at the position where the solder ball is to be implanted, and finally implanting the solder ball 30 at the opening. The solder balls may be made of several materials such as copper, tin, nickel, silver or alloys. The surface of the solder balls may be formed with a protective coating. The solder balls may be in the shape of ellipsoids, pillars, or other suitable structures. In one example, the solder ball surface may be formed with a recess that prevents solder from spilling out and shorting the device when the solder ball is subsequently soldered to other electrical connection structures. In other examples, solder balls electrically connected to the rewiring layer may be formed by physical vapor deposition, and then a solder resist layer may be formed in an area other than the solder balls. However, the solder mask layer is formed first and then the window is opened to implant the balls, so that the solder balls can be limited to a specific area effectively, and short circuit is avoided.
After the ball placement, a filling layer, such as epoxy resin, can be formed between the solder balls by methods including but not limited to capillary filling. The filler layer helps to secure the solder balls and prevents the solder balls from being oxidized, while preventing moisture and the like from penetrating into the inside of the packaged structure. And then, further attaching structures such as a protection frame and the like, and then cutting.
The invention combines the advantages of small grain size and surface roughness of physical vapor deposition process, thin slit-coated resist layer, good uniformity (the uniformity can be controlled within 5% and the resist layer can be 0-15 μm), high photoresist resolution, high photoetching precision of a photoetching machine and the like, improves the circuit precision, and realizes the manufacture of ultra-fine circuits with the line width spacing less than or equal to 8/8 μm on a buried chip organic carrier structure. It should be noted that the combination of the above steps is an integral body, and the above steps are matched with each other to finally manufacture the required ultra-fine circuit.
In order to reduce the cost of fan-out packaging and increase the wider application, the industry focuses the objective of FOPLP on L/S between 1/1 μm and 8/8 μm, and the invention just further fills the technical gap between the upstream board factories and the downstream OSAT factories. Compared with the silicon-based FOWLP, the organic-board-based FOPLP has a natural board-level infrastructure, is low in cost in all aspects, and has a higher market prospect.
Compared with the prior art, the invention has the following advantages:
1) In terms of social benefits, the manner of manufacturing the fine circuit on the substrate of the embedded chip by using the Fan-out packaging technology can achieve thinner packaging, can fill the difference of 1/1 mu m-8/8 mu m circuits between an upstream board factory and a downstream OSAT (out-packing assembly and test) factory, and can reduce the cost of Fan-out packaging while achieving high density and miniaturization.
2) In terms of economic benefit, the dry film thickness is affected by the filling property, the thinnest can only achieve about 15 mu m, and the dry film resolution/adhesion of the thickness can not meet the circuit manufacturing requirement below 8/8 mu m for post-process electroplating. The invention eliminates the traditional dry film pasting mode, adopts a wet slit coating mode, and prepares a thinner corrosion-resistant layer (less than or equal to 10 mu m). Compared with the spin coating mode in the wafer level packaging, the slot coating mode can coat a larger area at one time, thereby improving the production efficiency and having the advantage of productivity. On the other hand, compared with the traditional wet chemical copper deposition manufacturing process, the method adopts the dry PVD mode to manufacture the metal seed layer of the rewiring layer, so that the use of chemicals is greatly reduced, the production of industrial wastewater is correspondingly reduced, and the method is more environment-friendly. Furthermore, the PVD process is only required to clean the surface of the substrate, while the conventional wet copper process is also required to clean the surface of the dielectric layer by a wet decontamination (Desmear) process, so that the cost of using chemicals is increased, and wastewater is generated.
3) In terms of technical benefits, the invention can manufacture a thinner corrosion-resistant layer (less than or equal to 10 mu m) by adopting a slit coating mode, and the resolution adhesion of the corrosion-resistant layer can completely meet the requirement of less than 8/8 mu m, so that the invention is beneficial to manufacturing ultra-fine circuits (less than or equal to 8 mu m) by adopting an electroplating mode in a later process.
In the traditional metallization copper deposition process, a certain roughness is required on the surface of the dielectric layer, so that the peeling strength (generally, the peel strength is required to be more than 4N) between the copper deposition layer and the dielectric layer can be ensured to meet the requirements of customers. However, after the copper layer is formed (for example, the thickness of the copper layer is 1 μm), the copper layer at the line pitch needs to be removed by a flash process after the processes of coating a resist layer, exposing, developing, electroplating, and removing the film. At this time, the interfacial roughness of the dielectric layer and the dry film is increased by Desmear, which just results in that the line width interval cannot be made small in the subsequent flash etching, and the thickness of the copper layer is thicker, 1 μm, which means that the flash etching amount is required to be larger. Next, in the additive process, a larger amount of flash will require a larger line compensation, i.e. a smaller pitch, while the copper oxide layer and the dielectric layer at the pitch have a larger roughness, and flash easily causes line bottom side etching, even flying lines. These are all the root causes of failure to make the circuit finer on the copper-clad substrate. According to the invention, the metal seed layer is manufactured in a PVD mode, the roughness of the dielectric layer is not required to be increased, the peeling strength of the metal seed layer and the dielectric layer is more than 4N, and the bonding force is far greater than the bonding force between the copper layer and the dielectric layer. This is because PVD is capable of forming very dense nanoscale metal seed layers, and the metal seed layers are typically two, for example, the titanium metal layer of the first layer (e.g., 50-100 nm thick) has high adhesion and conductivity, and good thickness planarity, and is strongly bonded to the dielectric layer, and then sputtering a copper layer on the titanium layer as the metal host layer of the rewiring layer, the copper layer can be 100-500 nm thick, and compared to conventional copper-melting layers, the required copper layer thickness is greatly reduced, the time for subsequent flash or dry etching of the copper layer is short, and the circuit does not need to be compensated too much. Is beneficial to greatly improving the production efficiency and reducing the production cost.
The invention is not limited to board-level packages based on organic boards, but is particularly advantageous when used in such packages.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The board-level packaging method is characterized by comprising the following steps of:
s1: preparing a substrate, wherein a chip is embedded in the substrate;
s2: forming a metal seed layer on the surface of the substrate by using a physical vapor deposition process, and electrically connecting the metal seed layer with the chip through the hole;
s3: coating a resist layer on the metal seed layer by adopting a slit coating process and carrying out photoetching;
s4: developing the resist layer after photoetching by adopting a transmission type dipping bath developing process to define a rewiring layer pattern in the resist layer;
s5: forming a metal main body layer on the patterned resist layer by adopting an electroplating process, wherein the metal main body layer is electrically connected with the metal seed layer;
s6: etching the metal seed layer according to the patterned resist layer to form a rewiring layer, and removing the residual resist layer;
s7: a solder mask layer is formed on the rewiring layer and solder balls electrically connected with the rewiring layer are implanted.
2. The board-level packaging method according to claim 1, wherein the substrate comprises an organic carrier, and the preparation process of the substrate sequentially comprises: providing an organic carrier, making a pattern on the organic carrier, laser cutting a through groove of a buried chip, sticking an adhesive tape at the bottom, burying the chip, laminating a plastic packaging material to fill a space around the chip, turning the organic carrier and tearing the adhesive tape, enabling the active surface of the chip to face upwards, coating or vacuum pressing a dielectric layer, and forming holes in the dielectric layer.
3. The method of claim 2, wherein the molding compound is ABF, the dielectric layer is a photosensitive dielectric layer, and the method of forming the holes in the dielectric layer is photolithography or vacuum lamination.
4. The board level packaging method of claim 1, wherein the metal seed layer comprises an adhesion layer on a surface of the substrate and a metal seed layer on a surface of the adhesion layer.
5. The board level packaging method of claim 4, wherein the adhesion layer comprises a titanium layer and/or a titanium nitride layer, and the metallic seed layer comprises a copper layer; the thickness of the adhesion layer is 50nm-100nm, and the thickness of the copper layer is 100nm-500nm.
6. The board level packaging method according to claim 5, wherein the etching method of step S6 includes wet etching of the copper layer and wet etching or dry etching of the adhesion layer.
7. The method of claim 6, wherein the wet etching of the copper layer of the metallic seed layer is performed by etching with hydrogen peroxide and acid, and the wet etching of the titanium layer of the adhesion layer is performed by using HF or naoh+h 2 O 2 And alkaline mixture thereof, and the dry etching method for the titanium layer of the adhesion layer is to etch by adopting plasma or active ions including argon.
8. The board level packaging method according to claim 1, wherein the lithography in step S3 is LDI lithography using i-lines.
9. The board level packaging method according to claim 1, wherein step S7 includes the steps of firstly manufacturing a solder mask by any one of a film pasting mode, a roller coating mode and a screen printing mode, then performing window opening on the solder mask at a position where a solder ball is required to be implanted through exposure, development and post-curing, and finally implanting the solder ball at the window opening position.
10. The board level packaging method according to any one of claims 1 to 9, comprising the step of repeating steps S2 to S6 several times to form two or more rewiring layers stacked and electrically connected one above the other.
CN202310137908.6A 2023-02-20 2023-02-20 Board level packaging method Pending CN116469832A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117896908A (en) * 2024-03-14 2024-04-16 江门市和美精艺电子有限公司 Ultra-dense circuit packaging substrate and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117896908A (en) * 2024-03-14 2024-04-16 江门市和美精艺电子有限公司 Ultra-dense circuit packaging substrate and manufacturing method thereof

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