CN115799074A - Manufacturing method of embedded packaging structure - Google Patents

Abstract

According to the manufacturing method of the embedded packaging structure, a UV laser hole forming process is used for forming a blind hole which has a certain distance with a bonding pad of a chip in advance of an insulating medium layer, and then an etching process is used for forming a through hole; in addition, the process provided by the invention is not limited by the type of the copper foil on the surface of the substrate, does not need to carry out any windowing treatment on the surface, and has high applicability.

Description

Manufacturing method of embedded packaging structure

Technical Field

The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of an embedded packaging structure.

Background

With the development of electronic products towards high density and miniaturization, the embedded package structure technology has become one of the hot research contents in the field of electronic device packaging technology, and the structure and manufacturing procedure thereof are briefly described as follows. First, an electronic component (e.g., an active component) is embedded in an insulating substrate, and CO is used ₂ At least one through hole is formed in the insulating substrate in a laser drilling mode, then a conductive substance is filled in the through hole to form a conductive through hole, and then a redistribution layer (RDL) of high-density metal interconnection is formed on the insulating substrate and is in contact with the conductive through hole, so that the structure is electrically connected with an external electronic element.

At present, the conventional re-wiring layer for forming high-density metal interconnection has the following schemes: 1. a non-photosensitive dielectric layer is coated on a silicon substrate, a copper circuit on the surface layer is subjected to an etching windowing process, then a through hole is formed in the dielectric layer by using a carbon dioxide laser pore-forming process, a conductive substance is filled to form a conductive through hole, and the added layer is achieved in an overlapping mode to form a metal interconnection layer. The carbon dioxide laser pore-forming process can directly punch through the dielectric layer above the chip bonding pad, so the carbon dioxide laser pore-forming process may have the risk of the chip bonding pad being punctured, in addition, the carbon dioxide laser pore-forming process directly acts on the bonding pad of the chip, the chip cracking or other reliability influences may be caused by the influence of the laser heat effect, and the process flow is complex. 2. The copper opening is etched by opening the equal-size copper window, and then the through hole is formed by adopting a plasma dry etching mode, wherein the plasma dry etching mode adopts a variable frequency bias mode with same direction and opposite polarity so as to ensure the etching directionality. Although the process can meet the etching requirement and does not affect the bonding pad of the chip, the efficiency is generally low for forming the blind hole with high thickness-diameter ratio (blind hole depth/opening aperture), and the process is not suitable for large-scale mass production. 3. A photosensitive insulating layer dielectric layer is coated on a silicon substrate, and then the purpose of forming holes is achieved in an exposure and development mode. Although this process is common, the photolithography process involves multiple polluting wet chemical processes, which are complicated and expensive, resulting in high cost.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for manufacturing an embedded package structure, which is used to solve the problems of chip damage or other reliability impacts, low production efficiency due to complex manufacturing process, high environmental pollution, high production cost, and low process applicability of the prior art.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing an embedded package structure, including the steps of:

providing an organic carrier plate, wherein a first circuit layer and a second circuit layer are respectively arranged on a first surface and a second surface of the organic carrier plate, the first circuit layer and the second circuit layer are electrically connected through a conductive path penetrating through the organic carrier plate, and at least one cavity for accommodating a chip is arranged in the organic carrier plate;

attaching an adhesive film on the second surface, placing a chip in the cavity, and adhering and fixing the bonding pad of the chip and the adhesive film;

forming a plastic packaging layer on the first surface, wherein the plastic packaging layer completely covers the first surface and the first circuit layer, and the cavity is completely filled with the chip and the plastic packaging layer;

removing the adhesive film and forming an insulating medium layer on the second surface, so that the second surface, the second circuit layer and the chip are completely covered by the insulating medium layer;

forming a plurality of blind holes in the insulating medium layer through a UV laser hole forming process;

removing the residual insulating medium layer in the blind hole through a dry plasma etching process to form a through hole, wherein the through hole exposes the bonding pad of the chip and the second circuit layer;

and electroplating metal in the through hole to form a metal connecting layer, wherein the metal connecting layer is combined with the insulating medium layer to form a rewiring layer, and the rewiring layer is respectively and electrically connected with the chip and the organic carrier plate.

Optionally, the method further includes the steps of forming a solder mask covering the metal connection layer and an opening in the solder mask, and forming a solder joint array electrically connected to the metal connection layer in the opening in the solder mask.

Optionally, the second surface and the bonding pad of the chip are located on the same plane.

Optionally, the dry plasma etching process includes a capacitive coupling plasma etching process, an inductive coupling plasma etching process, or a microwave plasma etching process.

Optionally, the forming process of the insulating dielectric layer includes a spin coating process or a vacuum film pasting process, and the insulating dielectric layer includes a non-photosensitive insulating dielectric layer or a photosensitive insulating dielectric layer.

Optionally, the width of the blind hole ranges from 30 μm or less.

Optionally, the rewiring layer is a composite rewiring structure stacked from bottom to top.

Optionally, the specific step of forming the metal connection layer by electroplating metal in the through hole includes: forming a pre-plated metal layer covering the insulating medium layer and the through hole; forming a photoresist layer on the pre-plated metal layer, and patterning the photoresist layer; electroplating metal to form a metal connecting layer, wherein the metal connecting layer is respectively and electrically connected with the chip and the organic carrier plate; and removing the photoresist layer and the exposed part of the pre-plated metal layer.

Optionally, the pre-plated metal layer comprises a Ti/Cu layer, the thickness of the Ti/Cu layer is 300nm to 500nm, the thickness deviation is less than 5%, and the thickness of the Cu layer is greater than that of the Ti layer.

Compared with the prior art, the manufacturing method of the embedded packaging structure has the following beneficial effects: the UV laser pore-forming process is used for forming a blind hole which has a certain distance with a bonding pad of a chip in advance of the insulating medium layer, and then an etching process is used for forming a through hole; in addition, the process provided by the invention is not limited by the type of the copper foil on the surface of the substrate, does not need to carry out any windowing treatment on the surface, and has high applicability.

Drawings

Fig. 1 is a flowchart illustrating a method for manufacturing an embedded package structure according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view illustrating an organic carrier according to a first embodiment of the invention.

Fig. 3 is a schematic cross-sectional view illustrating the formation of an adhesive film according to an embodiment of the invention.

Fig. 4 is a schematic cross-sectional view of a chip embedded according to a first embodiment of the invention.

Fig. 5 is a schematic cross-sectional view illustrating a plastic encapsulation layer formed according to an embodiment of the invention.

Fig. 6 is a schematic cross-sectional view illustrating a process of removing the adhesive film and forming an insulating dielectric layer according to an embodiment of the invention.

Fig. 7 is a schematic cross-sectional view illustrating the formation of blind vias in an insulating dielectric layer according to an embodiment of the invention.

Fig. 8 is a schematic cross-sectional view illustrating the formation of a via in an insulating dielectric layer according to a first embodiment of the invention.

Fig. 9 is a schematic cross-sectional view illustrating the formation of a photoresist layer in a via hole according to a first embodiment of the invention.

FIG. 10 is a schematic cross-sectional view illustrating a patterned photoresist layer provided in accordance with one embodiment of the present invention.

Fig. 11 is a schematic cross-sectional view illustrating a metal connection layer formed in accordance with a first embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view illustrating a first redistribution layer formed according to an embodiment of the invention.

Fig. 13 is a schematic cross-sectional view illustrating a second redistribution layer formed in accordance with a first embodiment of the present invention.

Fig. 14 is a schematic structural diagram illustrating a structure after forming a solder resist layer and forming an opening according to a first embodiment of the present invention.

Fig. 15 is a schematic structural diagram illustrating a method for forming a solder pad array according to an embodiment of the invention.

Fig. 16 is a schematic structural diagram of an embedded package structure according to an embodiment of the invention.

Description of the element reference numerals

10. Organic carrier plate

101. First surface

102. Second surface

103. Conductive path

104. First circuit layer

105. Second circuit layer

106. Hollow cavity

11. Adhesive film

12. Chip and method for manufacturing the same

121. Bonding pad

13. Plastic packaging layer

14. Insulating medium layer

15. Blind hole

16. Through hole

17. Photoresist layer

18. Metal connection layer

19. Redistribution layer

191. First rewiring layer

192. Second rewiring layer

193. Third rewiring layer

20. Solder mask

201. Opening(s)

210. Solder joint array

S1 to S7

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

It should be understood that the terms "first," "second," and the like, are used for limiting the components, are used for distinguishing the components, and have no special meaning if not stated otherwise, and therefore, the scope of the present invention should not be construed as being limited.

Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Referring to fig. 1 to fig. 16, an embodiment of the invention provides a method for manufacturing an embedded package structure, where the method includes the following steps:

s1: providing an organic carrier 10, wherein a first surface 101 and a second surface 102 of the organic carrier 10 are respectively provided with a first circuit layer 104 and a second circuit layer 105, the first circuit layer 104 and the second circuit layer 105 are electrically connected through a conductive path 103 penetrating through the organic carrier 10, and at least one cavity 106 for accommodating a chip 12 is arranged in the organic carrier 10;

s2: attaching an adhesive film 11 on the second surface 102, placing the chip 12 in the cavity, and adhering and fixing the bonding pad 121 of the chip 12 and the adhesive film 11;

s3: forming a molding layer 13 on the first surface 101, wherein the molding layer 13 completely covers the first surface 101, the first circuit layer 104, and the cavity 106 is completely filled with the chip 12 and the molding layer 13;

s4: removing the adhesive film 11 and forming an insulating dielectric layer 14 on the second surface 102, so that the second surface 102, the second circuit layer 105 and the chip 12 are completely covered by the insulating dielectric layer 14;

s5: forming a plurality of blind holes 15 in the insulating medium layer 14 by a UV laser pore-forming process;

s6: removing the residual insulating medium layer 14 in the blind hole 15 by a dry plasma etching process to form a through hole 16, wherein the through hole 16 exposes the bonding pad 121 of the chip 12 and the second circuit layer 105;

s7: and electroplating metal in the through hole 16 to form a metal connecting layer 18, wherein the metal connecting layer 18 is combined with the insulating medium layer 14 to form a re-wiring layer 19, and the re-wiring layer 19 is electrically connected with the chip 12 and the organic carrier plate 10 respectively.

The following further describes the manufacturing method of the embedded package structure in this embodiment with reference to the accompanying drawings, which are as follows:

in step S1, please refer to fig. 1 and fig. 2, an organic carrier 10 is provided, a first circuit layer 104 and a second circuit layer 105 are respectively disposed on a first surface 101 and a second surface 102 of the organic carrier 10, the first circuit layer 104 and the second circuit layer 105 are electrically connected through a conductive via 103 penetrating through the organic carrier 10, and at least one cavity 106 for accommodating a chip 12 is disposed inside the organic carrier 10.

Specifically, as shown in fig. 2, in the present embodiment, an organic carrier 10 is provided, the organic carrier 10 includes a first surface 101 and a second surface 102, and a first circuit layer 104 disposed on the first surface 101 and a second circuit layer 105 disposed on the second surface 102, a patterning process is performed on the first circuit layer 104 to expose a portion of the first surface 101 of the organic carrier 10 through the first circuit layer 104, and a plurality of conductive vias 103 are formed in the organic carrier 10, the first circuit layer 104 is connected to the conductive vias 103 for conduction, a similar patterning process is performed on the second circuit layer 105 to expose a portion of the second surface 102 of the organic carrier 10, and the second circuit layer 105 is also connected to the conductive vias 103 for conduction, so as to electrically connect the first circuit layer 104 to the second circuit layer 105. At least one cavity 106 for accommodating the chip 12 is disposed in the organic carrier 10, and of course, the organic carrier 10 may also include a plurality of openings or cavities 106 for accommodating the chip 12 respectively.

Alternatively, the cavity 106 may be formed mechanically, the cavity 106 may or may not extend through the organic carrier 10, and the shape of the cavity 106 may be a square or any other shape suitable for placing a chip.

Optionally, the type of the chip 12 may be any chip suitable for packaging technology, and the thickness of the chip 12 is 60 to 100 μm. The chip 12 has a bonding pad 121, and in order to ensure that the chip 12 can be inserted into the cavity 106 without damage, the thickness of the chip 12 is smaller than the depth of the cavity 106 and the size of the chip 12 is smaller than the size of the cavity 106.

Optionally, the second surface 102 and the bonding pads 121 of the chip 12 are located on the same plane, so as to ensure the planarization of the organic carrier 10 and the chip 12, thereby facilitating the layout of the redistribution layers.

In step S2, referring to fig. 1, fig. 3 and fig. 4, an adhesive film 11 is attached to the second surface 102, the chip 12 is placed in the cavity 106, and the bonding pad 121 of the chip 12 is bonded and fixed to the adhesive film 11.

Optionally, as shown in fig. 3, in the present embodiment, an adhesive film 11 is attached to the second surface 102 of the organic carrier 10, where the adhesive film 11 is one of a tape and a DAF film, and in the present embodiment, the adhesive film 11 is preferably a DAF film, which is beneficial to relieving a thermal stress during a packaging process and is applicable to an uneven organic carrier.

Specifically, as shown in fig. 4, in this embodiment, the chip 12 is placed in the cavity 106, and the bonding pad 121 of the chip 12 is bonded and fixed to the bonding film 11, wherein a certain space is left between the chip 12 and the organic carrier 10 after the chip 12 is placed in the cavity 106.

In step S3, please refer to fig. 1 and fig. 5, a molding compound layer 13 is formed on the first surface 101, the molding compound layer 13 completely covers the first surface 101, the first circuit layer 104, and the cavity 106 is completely filled with the chip 12 and the molding compound layer 13.

As an example, as shown in fig. 5, in this embodiment, a molding compound layer 13 is formed on the first surface 101 of the organic carrier 10, and the molding compound layer 13 fills the remaining space except for the area occupied by the chip 12 in the cavity 106, the first surface 101 not covered by the first circuit layer 104, and the first circuit layer 104.

Alternatively, the molding layer 13 may be formed by injection through a nozzle, and the molding layer 13 includes one or a combination of epoxy resin, silicone resin, or polyimide.

In step S4, referring to fig. 1 and fig. 6, the adhesive film 11 is removed and an insulating dielectric layer 14 is formed on the second surface 102, so that the second surface 102, the second circuit layer 105 and the chip 12 are completely covered by the insulating dielectric layer 14.

As an example, as shown in fig. 6, in this embodiment, the adhesive film 11 is removed, and an insulating medium layer 14 is formed on the second surface 102 of the organic carrier 10 and the pad 121 of the chip 12, where the insulating medium layer 14 covers the pad 121 of the chip 12, the second surface 102, and the second circuit layer 105.

Optionally, the forming process of the insulating dielectric layer 14 includes a spin coating process or a vacuum film pasting process, and the insulating dielectric layer 14 includes a non-photosensitive insulating dielectric layer or a photosensitive insulating dielectric layer.

In step S5, referring to fig. 1 and fig. 7, a plurality of blind holes 15 are formed in the insulating dielectric layer 14 by a UV laser via-forming process.

As an example, as shown in fig. 7, in the present embodiment, a plurality of blind holes 15 are formed in the insulating dielectric layer 14 by a UV laser via forming process, and the positions of the blind holes 15 are opposite to the pads 121 of the chip 12 and the second circuit layer 105. In order to ensure that the UV laser does not affect the bonding pads 121 of the chip 12, the depth of the blind holes 15 is smaller than the height of the insulating medium layer 14, i.e. a certain distance of the insulating medium layer 14 is reserved. Wherein the bottom of the blind hole 15 is at least 3 μm away from the pad 121 of the chip 12.

Optionally, the width of the blind holes ranges below 30 μm, for example, 5 μm, 10 μm, 20 μm or 30 μm. Compared with the thermochemical effect of the traditional carbon dioxide laser processing technology on the insulating dielectric layer 14, the UV laser pore-forming technology can cause electron transition in the molecules of the insulating dielectric layer 14, and the thermal effect influence on the insulating dielectric layer 14 can be effectively reduced due to the high energy density and the special photochemical effect of the UV laser pore-forming technology. Optionally, the UV laser may select one of Nano UV and Pico UV.

In step S6, referring to fig. 1 and 8, the remaining insulating dielectric layer 14 in the blind via 15 is removed by a dry plasma etching process to form a through hole 16, and the through hole 16 exposes the pad 121 of the chip 12 and the second circuit layer 105.

Specifically, as shown in fig. 8, in this embodiment, the remaining insulating medium layer 14 in the blind via 15 is removed through a dry plasma etching process, so as to form a through hole 16 exposing the pad 122 on the pad 121 of the chip 12 and the second circuit layer 105.

Optionally, the dry plasma etching process includes a capacitive coupling plasma etching process, an inductive coupling plasma etching process, or a microwave plasma etching process. The dry plasma etching process has the same anisotropy, and the RF bias voltage is applied in a certain direction, so that the plasma etching direction can be controlled, the influence on the side wall of the blind hole 15 can be reduced, and the pad 121 of the chip 12 cannot be damaged while the residual insulating medium layer 14 is removed to the maximum extent.

In step S7, referring to fig. 1 and fig. 9 to fig. 13, a metal is electroplated in the through hole 16 in the insulating dielectric layer 14 to form a metal connection layer 18, the metal connection layer 18 is combined with the insulating dielectric layer 14 to form a redistribution layer 19, and the redistribution layer 19 is electrically connected to the chip 12 and the organic carrier 10, respectively.

As an example, the specific steps of forming the metal connection layer 18 by electroplating metal in the through hole 16 include: forming a pre-plated metal layer covering the insulating medium layer 14 and the through hole 16; forming a photoresist layer on the pre-plated metal layer, and patterning the photoresist layer; electroplating metal to form a metal connecting layer 18, wherein the metal connecting layer 18 is electrically connected with the chip 12 and the organic carrier 10 respectively; and removing the photoresist layer and the exposed part of the pre-plated metal layer.

As an example, the pre-plated metal layer includes a Ti/Cu layer having a thickness of 300nm to 500nm, a thickness deviation of <5%, and a Cu layer having a thickness greater than the Ti layer.

Specifically, as shown in fig. 9 to 12, in this embodiment, a Ti/Cu layer (not shown in the figure) is deposited in the through hole 16, the thickness of the Ti/Cu layer is 300nm to 500nm, and the thickness deviation thereof is kept to be less than 5%, that is, a Ti layer is deposited first, because the Ti layer has high electrical conductivity and adhesion and good thickness uniformity, the adhesion between the metal connection layer 18 and the insulating dielectric layer 14 formed subsequently is enhanced to achieve better fixation, and then a Cu layer is deposited on the Ti layer, and the thickness of the Cu layer is greater than that of the Ti layer, and the Ti/Cu layer may be formed by physical vapor deposition. As shown in fig. 9, a photoresist layer 17 is coated on the Ti/Cu seed layer and the second surface 102 of the organic carrier 10, and as shown in fig. 10, the Ti/Cu seed layer and the second surface are patterned by exposure and development to expose the through holes 16, wherein the patterning process is performed by performing photolithography and etching on the photoresist layer 17. As shown in fig. 11, the through hole 16 is filled with a conductive material to form a metal connection layer 18, and the metal connection layer 18 may be formed by selective electroplating. As shown in fig. 12, the remaining photoresist layer 17 and the exposed portion of the pre-plated metal layer are removed to form a patterned metal connection layer 18.

As an example, the rewiring layer 19 is a composite rewiring structure stacked from bottom to top.

Specifically, as shown in fig. 13, in the present embodiment, the metal connection layer 18 and the insulating medium layer 14 form the rewiring layer 19, the rewiring layer 19 is a composite rewiring structure stacked from bottom to top, for example, the rewiring layer 19 may include a first rewiring layer 191 and a second rewiring layer 192, and each rewiring layer is electrically extended to the outside of the package structure through the metal connection layer 18, and the rewiring layer 19 is used to electrically connect the pad 121 of the chip 12 and the second wiring layer 105 of the organic carrier 10.

Alternatively, steps S5 through S7 may be repeated as necessary to prepare a package structure including N (N ≧ 2) redistribution layers 19. For example, in another embodiment, as shown in fig. 16, the re-wiring layer 19 further includes a third re-wiring layer 193. Of course, the specific number of layers of the redistribution layer 19 may be selected according to needs, and is not limited herein.

Optionally, as shown in fig. 14, in this embodiment, a solder mask layer 20 is formed on the package structure obtained in step S7, where the solder mask layer 20 may be formed through a series of processes such as coating, photolithography and annealing, the solder mask layer 20 covers the redistribution layer 19, an opening 201 is formed in the solder mask layer 20 to expose the metal connection layer 18, and as shown in fig. 15, a solder pad array 210 connected to the metal connection layer 18 is formed in the opening 201 through a ball-mounting process. Wherein the pad array 210 is electrically connected to an external device.

Specifically, in this embodiment, a photolithography process is used to form the opening 201 on the solder mask layer 20, and a ball-planting process is used to form the solder joint array 210 in the opening 201, so as to electrically connect the package structure with an external structure.

Optionally, the pad array 210 includes one of a gold-tin pad array, a silver-tin pad array, and a copper-tin pad array. Of course, the pad array 210 can also be formed by a reflow process, which is not limited herein.

In summary, the present invention provides a method for manufacturing an embedded package structure, which has the following advantages: the UV laser pore-forming process is used for forming a blind hole which has a certain distance with a bonding pad of a chip in advance of the insulating medium layer, and then the dry plasma etching process is used for forming a through hole; in addition, the process provided by the invention is not limited by the type of the copper foil on the surface of the substrate, does not need to carry out any windowing treatment on the surface, and has high applicability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A manufacturing method of an embedded packaging structure is characterized by comprising the following steps:

providing an organic carrier plate, wherein a first circuit layer and a second circuit layer are respectively arranged on a first surface and a second surface of the organic carrier plate, the first circuit layer and the second circuit layer are electrically connected through a conductive path penetrating through the organic carrier plate, and at least one cavity for accommodating a chip is arranged in the organic carrier plate;

attaching an adhesive film on the second surface, placing a chip in the cavity, and adhering and fixing the bonding pad of the chip and the adhesive film;

forming a plastic packaging layer on the first surface, wherein the plastic packaging layer completely covers the first surface, the first circuit layer and the cavity, and the chip and the plastic packaging layer are completely filled in the cavity;

removing the adhesive film and forming an insulating medium layer on the second surface, so that the second surface, the second circuit layer and the chip are completely covered by the insulating medium layer;

forming a plurality of blind holes in the insulating medium layer through a UV laser hole forming process;

removing the residual insulating medium layer in the blind hole through a dry plasma etching process to form a through hole, wherein the through hole exposes the bonding pad of the chip and the second circuit layer;

and electroplating metal in the through hole to form a metal connecting layer, wherein the metal connecting layer is combined with the insulating medium layer to form a rewiring layer, and the rewiring layer is respectively and electrically connected with the chip and the organic carrier plate.

2. The method of manufacturing according to claim 1, wherein: the method also comprises the steps of forming a solder mask covering the metal connecting layer and an opening positioned in the solder mask, and forming a welding spot array electrically connected with the metal connecting layer in the opening of the solder mask.

3. The method of manufacturing according to claim 1, wherein: the second surface and the bonding pad of the chip are positioned on the same plane.

4. The method of manufacturing according to claim 1, wherein: the dry plasma etching process comprises a capacitive coupling plasma etching process, an inductive coupling plasma etching process or a microwave plasma etching process.

5. The method of manufacturing according to claim 1, wherein: the forming process of the insulating layer comprises a spin coating process or a vacuum film pasting process.

6. The method of manufacturing according to claim 1, wherein: the insulating medium layer comprises a non-photosensitive insulating medium layer or a photosensitive insulating medium layer.

7. The method of manufacturing according to claim 1, wherein: the width range of the blind hole is below 30 mu m.

8. The method of manufacturing according to claim 1, wherein: the rewiring layer is a composite rewiring structure which is overlapped from bottom to top.

9. The method of manufacturing according to claim 1, wherein: the specific steps of forming the metal connecting layer by electroplating metal in the through hole comprise: forming a pre-plated metal layer covering the insulating medium layer and the through hole; forming a photoresist layer on the pre-plated metal layer, and patterning the photoresist layer; electroplating metal to form a metal connecting layer, wherein the metal connecting layer is respectively and electrically connected with the chip and the organic carrier plate; and removing the photoresist layer and the exposed part of the pre-plated metal layer.

10. The method of manufacturing according to claim 9, wherein: the pre-plated metal layer comprises a Ti/Cu layer, the thickness of the Ti/Cu layer is 300 nm-500 nm, the thickness deviation is less than 5%, and the thickness of the Cu layer is larger than that of the Ti layer.

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