TWI814584B - Packaging substrate structure and method of fabricating the same - Google Patents

Abstract

A packaging substrate structure and a method of fabricating the same are provided. The method includes forming pads on a first carrier plate; sticking a conducting block on an exposing portion of the first carrier plate; forming a substrate containing a dielectric layer, circuit layers, first vias and second vias on the first carrier plate; forming a connecting structure containing insulating layers and third vias on the substrate; removing the conducting block to expose narrow ends of the second vias; and disposing a chip on the second vias. Therefore, the first vias and the second vias can be formed simultaneously. The narrow ends of the second vias are used to bind the chip to decrease pitches between connecting ends.

Description

Package substrate structure and manufacturing method thereof

The present invention relates to a packaging substrate structure and a manufacturing method thereof, in particular to a packaging substrate structure for stacked packaging and a manufacturing method thereof.

In recent years, electronic equipment has developed rapidly, and electronic packaging technology has continued to increase its demand for miniaturization, high input/output (I/O) density and reliability. Among them, package on package (POP) is the best way to save circuit board space. effective technical means. For example, stacked packaging packages the memory and the processor into an integrated circuit (IC), and connects solder balls or conductive pillars below or above the two integrated circuits, and then stacks the processor. The layer is above the memory.

One aspect of the present invention provides a method for manufacturing a packaging substrate structure to simultaneously manufacture first via holes and second via holes.

Another aspect of the present invention is to provide a packaging substrate structure, which is produced using the method of the above aspect.

According to an aspect of the present invention, a method for manufacturing a packaging substrate structure is provided. The method includes providing a first carrier board and a metal layer, wherein the metal layer is disposed on the surface of the first carrier board; patterning the metal layer to form contact pads and partially exposing the first carrier board; attaching conductive blocks on the exposed portion of the first carrier board; forming a substrate on the first carrier board; removing the first carrier board to expose the conductive blocks in the dielectric layer and the pads; forming a connection substrate on the surface of the dielectric layer; removing part of the insulating layer in the connection substrate and leaving only the insulating layer around the second via hole to form a plurality of connecting components and exposing the conductive block; removing the conductive block to form a groove on the dielectric layer and exposing a narrow end of the second via hole; and disposing at least one wafer on the conductive On the blind hole. The substrate includes a dielectric layer pressed on the surface of the first carrier board, and the dielectric layer covers the conductive block and the pad; it is formed on the surface of the dielectric layer away from the pad a circuit layer on the circuit layer; a plurality of first via holes electrically connecting the circuit layer and the pads; and a second via hole electrically connecting the conductive block and the circuit layer. The connection substrate includes an insulating layer covering the conductive block and the pad; and a plurality of third via holes penetrating the insulating layer and exposed to a top surface of the insulating layer, and the third via holes The hole is electrically connected to the pad.

According to an embodiment of the present invention, before removing the first carrier board, the method further includes forming a solder resist layer on the substrate.

According to an embodiment of the present invention, after the first carrier board is removed, the method further includes forming a second carrier board on the solder resist layer relative to the conductive block.

According to an embodiment of the present invention, after pasting the conductive block, the method further includes pasting an adhesive layer on the conductive block, wherein the second via hole is formed on the adhesive layer, and removing the conductive block. The step of blocking further includes removing the adhesive layer.

According to an embodiment of the present invention, after removing part of the insulating layer and before removing the conductive block, the dielectric layer is further thinned to form at least one protrusion on the dielectric layer. on the surface away from the circuit layer.

According to an embodiment of the present invention, before bonding the wafer, the method further includes forming an underfill layer in the groove and on the second via hole.

According to an aspect of the present invention, a packaging substrate structure is provided, which includes a circuit substrate, a plurality of contact pads, and a plurality of connection members disposed on the contact pads. The circuit substrate includes a dielectric layer, a circuit layer, a first via hole disposed in the dielectric layer, and a second via hole disposed in the dielectric layer. The first surface of the dielectric layer includes at least one protrusion. The circuit layer is disposed on the second surface of the dielectric layer, wherein the second surface is opposite to the first surface. The second via hole has a trapezoidal cross-sectional shape and has a narrow end, and the narrow end protrudes from the first surface of the dielectric layer. The contact pad is arranged on the protruding part. Each connection member includes at least one third via hole and an insulating layer covering the third via hole. The third via hole is electrically connected to the pad, and the outermost third via hole is exposed to the top surface of the insulating layer.

According to an embodiment of the present invention, the pad and the circuit layer are electrically connected using the first via hole.

According to an embodiment of the present invention, the packaging substrate structure further includes an underfill layer disposed on the narrow end of the second via hole.

According to an embodiment of the present invention, the cross-sectional shape of each first via hole is a trapezoid, and the width of the first via hole is along the second surface of the dielectric layer toward the first surface. direction decreases.

According to an embodiment of the present invention, the cross-sectional shape of each third via hole is a trapezoid, and the width of the third via hole decreases along the top surface of the insulating layer toward the direction of the pad. .

According to an embodiment of the present invention, the above-mentioned packaging substrate structure further includes at least one chip or at least one semiconductor element bonded to the second via hole.

Applying the packaging substrate structure and its manufacturing method of the present invention, a plurality of connection members are formed on the circuit substrate, and the conductive blocks are used to form second via holes with uniform height, and the narrow ends of the second via holes are used to connect the chips, thereby reducing packaging costs. Spacing between substrate connection ends.

The invention provides many different embodiments or illustrations for implementing different features of the invention. Specific illustrations of components and arrangements described below are provided to simplify the present invention. These are of course only examples and are not intended to be limiting. For example, descriptions of a first feature being formed on or above a second feature include embodiments in which the first feature and the second feature are in direct contact, and also include embodiments in which other features are formed between the first feature and the second feature. Embodiments such that the first feature and the second feature are not in direct contact. In addition, the present invention repeats reference symbols and/or letters in various embodiments. This repetition is for simplicity and clarity of illustration and does not imply a relationship between the various discussed embodiments and/or configurations.

Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" ” etc. are used to easily describe the relationship between the parts or features shown in the drawings and other parts or features. Spatially relative terms include the orientation of components in use or operation in addition to the orientation depicted in the diagrams. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As the functionality of electronic devices continues to increase, the density of interconnections in packaging structures continues to increase. Under this situation, if you want to increase the number of interconnection lines by reducing the size of solder balls or copper pillars in a stacked package, you will be limited by materials and processes. Therefore, the number of interconnect lines will limit the performance improvement of stacked packages.

In the existing package on package (POP) technology, in order to connect the upper package and the lower package, solder balls must be used to ensure the height of the gap between the package substrate and the chip. However, if the density and number of chip connection terminals are to be increased, the density and number of chip connections must be reduced. The size of the solder ball, otherwise it cannot meet the aforementioned pitch height at the same time. Another existing approach is to etch and electroplat copper pillars or fill conductive paste in dry film or sealant to connect substrates. However, due to the process characteristics of electroplating and filling conductive paste, the die connection end is affected by the aspect ratio (aspect ratio, also known as (aspect ratio), it is difficult to increase the spacing between the connecting ends arranged on the sealant surface.

Another existing stacked packaging technology uses through mold via (TMV), which uses laser drilling to form through holes, and then fills the through holes with conductive materials. However, the plastic mold material is organic. And inorganic composite materials, the cost of making through holes is high, and the aperture ratio is also limited. Therefore, the present invention provides a packaging substrate structure and a manufacturing method thereof to achieve the above-mentioned high circuit density and comply with a specific packaging stacking height.

Please refer to FIG. 1 , which illustrates a cross-sectional view of a packaging substrate structure 100 according to some embodiments of the present invention. The package substrate structure 100 includes a circuit substrate 101 , and the circuit substrate 101 includes a solder resist layer 110 and a dielectric layer 120 on the solder resist layer 110 . In some embodiments, top surface 120T of dielectric layer 120 has at least one protrusion 121 higher than top surface 120T. The circuit substrate 101 also includes a plurality of circuit layers 132 on the bottom surface 120B of the dielectric layer 120 . In some embodiments, the circuit layer 132 can also be selectively disposed in the dielectric layer 120 . In some embodiments, the circuit substrate 101 may be a multi-layer circuit board.

The circuit substrate 101 also includes a plurality of first via holes 131 , first via holes 162 and second via holes 130 . As shown in FIG. 1 , some of the second via holes 130 and the first via holes 131 are stacked respectively, that is, three via holes (one second via hole 130 and two first via holes 131 ) are stacked on each other, but the stacking number There is no limitation; and part of the second via hole 130 may not be stacked with the first via hole 131 . Some of the first via holes 162 are not under the second via holes 130 . In some embodiments, the cross-sectional shapes of the first via hole 131 , the first via hole 162 and the second via hole 130 are all trapezoidal, and the widths of the first via hole 131 , the first via hole 162 and the second via hole 130 are It gradually decreases along the bottom surface 120B of the dielectric layer 120 toward the top surface 120T. Furthermore, the narrow end portion (ie, the end portion with smaller width) 130A of the second via hole 130 protrudes from the dielectric layer 120 and is exposed in the groove (not shown in the figure) of the dielectric layer 120 . In some embodiments, plasma etching or laser ablation may be used to simultaneously fabricate the first via hole 131 , the first via hole 162 and the second via hole 130 .

In addition, in some embodiments, the solder resist layer 110 may have an opening 115 below the first via hole 131 to expose the soldering pad or the soldering pad in the circuit layer 132 (not shown in the figure). The solder pad will cover the first via hole 131 .

In addition, in this embodiment, the packaging substrate structure 100 further includes a plurality of pads 161 disposed on the protruding portions 121 of the dielectric layer 120 . In other words, the pad 161 is higher than the top surface 120T of the dielectric layer 120 . In some embodiments, the pad 161 and the circuit layer 132 are electrically connected using the first via hole 131 .

The package substrate structure 100 also includes a plurality of connection members 171 disposed on the pads 161 . Each connection member 171 includes at least one third via hole 164 and an insulating layer 170 covering the third via hole 164 . The third via hole 164 is electrically connected to the pad 161 . In some embodiments, the cross-sectional shape of the third via hole 164 is trapezoidal, and the width of the third via hole 164 decreases along the top surface 170T of the insulating layer 170 toward the direction of the pad 161 . In other words, the first via hole 162 and the third via hole 164 are both connected to the pad 161 with a narrow end (ie, an end portion with a smaller width). It should be noted that FIG. 1 shows that the uppermost third via hole 164 includes a pad 164A, but in other embodiments, the uppermost third via hole 164 may not have a pad 164A.

The insulating layer 170 covers the third via hole 164 to protect the third via hole 164 and contribute to the stability of the connection member 171 . In some embodiments, the material of the insulating layer 170 is the same as the material of the dielectric layer 120 . In other embodiments, since no circuits are provided in the insulating layer 170, lower cost insulating materials can be used.

In some embodiments, each connection member 171 may include only one third via hole 164 or may include multiple stacked third via holes 164 . In the aforementioned embodiment with only one third via hole 164 , the third via hole 164 is exposed to the top surface 170T of the insulating layer 170 ; in the embodiment with multiple stacked third via holes 164 , the outermost or farthest The third via hole 164 of the pad 161 is exposed to the top surface 170T of the insulating layer 170 . The stacking number of the third via holes 164 of the connection member 171 can be adjusted according to application requirements. The connection member 171 can replace the existing solder balls or copper pillars to connect another package (such as other package substrate structures 100), thereby forming a package substrate structure for stacked packaging. Therefore, it is advantageous to use the connection member 171 of the present invention. To improve the circuit density of the substrate.

In some embodiments, an underfill layer 140 is disposed in a groove (not shown) of the dielectric layer 120 . In other words, the bottom surface of the underfill layer 140 is lower than the top surface 120T of the dielectric layer 120 . The narrow end portion 130A of the second via hole 130 is connected to the underfill layer 140 . The package substrate structure 100 includes at least one chip (or at least one semiconductor component) 150 , and the chip 150 is disposed on the underfill layer 140 and the narrow end portion 130A of the second via hole 130 . In some embodiments, a solder ball 142 is further included between the narrow end portion 130A of the second via hole 130 and the chip 150 to electrically connect the chip 150 and the second via hole 130 . The present invention uses the narrow end portion 130A of the second via hole 130 as the connection end of the chip, so it is beneficial to reduce the spacing between the connection ends, thereby increasing the density of the connection lines. Furthermore, the narrow end portion 130A of the second via hole 130 protruding from the dielectric layer 120 can effectively improve the reliability of interconnection with the chip 150 .

Please refer to FIGS. 2A to 2M , which illustrate cross-sectional views of an intermediate stage of the manufacturing process of the packaging substrate structure 200 according to some embodiments of the present invention. First, please refer to FIG. 2A , a first carrier plate 201 and a metal layer 203 on the first carrier plate 201 are provided. In some embodiments, the first carrier plate 201 includes resin material or other suitable materials. In some embodiments, metal layer 203 includes copper.

Referring to FIG. 2B , the metal layer 203 in FIG. 2A is patterned to expose part of the first carrier board 201 and form contact pads 261 . Furthermore, the conductive block 205 is attached to the exposed portion of the first carrier board 201 . In some embodiments, the conductive block 205 can be applied between the pads 261 . In some embodiments, after attaching the conductive block 205, an adhesive layer 207 can be formed on the conductive block 205.

Referring to FIG. 2C , a build-up process is used to form a substrate on the first carrier board 201 , where the substrate includes a dielectric layer 220A, a first via hole 262A, a second via hole 230A and a circuit layer 232 . The specific method includes first forming the dielectric layer 220A and the metal layer 213 on the first carrier board 201, the pads 261, the conductive blocks 205 and the adhesive layer 207, wherein the metal layer 213 is on the dielectric layer 220A. In some embodiments, metal layer 213 includes the same material as metal layer 203 (or pad 261). Next, a laser drilling operation 10 is performed to form the first opening O1 and the second opening O2.

The direction shown in the laser drilling operation 10 may be the direction of travel of the laser beam. The first opening O1 extends downward from the top 213T of the metal layer 213 to expose the pad 261 , and the second opening O2 extends downward from the top 213T of the metal layer 213 to expose the conductive block 205 . Due to the direction of the laser drilling operation 10 , the first opening O1 and the second opening O2 are formed in a trapezoidal cross-sectional shape, and their widths decrease along the direction from the pad 261 to the first carrier plate 201 .

Referring to FIG. 2D , conductive material (eg, copper) is deposited and filled on the first opening O1 and the second opening O2 (refer to FIG. 2C ) to form the first via hole 262A and the second via hole 230A respectively. The first via hole 262A and the second via hole 230A formed due to conformal deposition also have a trapezoidal cross-section whose width decreases along the direction from the pad 261 to the first carrier board 201 . Next, the metal layer 213 on the dielectric layer 220A is patterned (see FIG. 2C ) to partially remove the metal layer 213 to expose the top surface 220A _T of the dielectric layer 220A. Then, a circuit layer 232 is formed on the first via hole 262A and on the exposed top surface 220A _T of the dielectric layer 220A. In some embodiments, the second via hole 230A is electrically connected to the conductive block 205 and the circuit layer 232 .

Referring to FIG. 2E, repeat the steps of FIG. 2C and FIG. 2D (i.e., build-up method) to form the first via hole 262B stacked on the first via hole 262A, and to form the first via hole 230 on the second via hole 230A. . It should be noted that the dielectric layer 220B includes the dielectric layer 220A and a dielectric layer portion formed on the dielectric layer 220A. FIG. 2E shows that only two first via holes 262B are formed on the second via holes 230A at both ends, but no first via holes 262B are formed on the two second via holes 230A in the middle. However, the invention is not limited thereto. . In other words, according to subsequent applications or structural configurations, no first via hole 262B may be formed on the second via hole 230A, or more or fewer first via holes 262B may be formed on the second via hole 230A. Likewise, wiring layer 232 is formed on the top surface of dielectric layer 220B.

Referring to FIG. 2F , the steps of FIG. 2C and FIG. 2D (ie, the layering method) are repeated to form the first via hole 262C stacked on the first via hole 262B. It should be noted that, as shown in FIG. 2F , only the first via hole 262C is formed, and the first via hole is no longer formed on the second via hole 230A. However, in other embodiments, the first via hole can also be continued to be formed. The holes are stacked on the second via hole 230A (refer to FIG. 2E). Similar to FIG. 2E , dielectric layer 220 includes dielectric layer 220B and a dielectric layer portion formed on dielectric layer 220B. Likewise, a circuit layer 232 is formed on the top surface of the dielectric layer 220 . In the following description, the first via hole 262A, the first via hole 262B, and the first via hole 262C may be collectively referred to as the first via hole 262. It should be understood that in some embodiments, the circuit layer 232 may be formed only on the dielectric layer 220 but not in the dielectric layer 220 (ie, not formed on the dielectric layer 220A and the dielectric layer 220B).

Referring to FIG. 2G , a solder resist layer 210 is formed on the dielectric layer 220 and covers the circuit layer 232 . The solder resist layer 210 is mainly used to protect the circuit layer 232 on the circuit board. In some embodiments, solder mask 210 contains ink or other suitable insulating material.

It should be noted that, in order to increase the output and reduce the production time, the steps of FIG. 2A to FIG. 2G can be selectively performed on the upper and lower sides of the first bearing plate 201 at the same time, that is, a symmetrical structure is formed on the upper and lower sides. Then, the upper and lower structures are separated and the subsequent processes are carried out separately.

Referring to FIG. 2H , the first carrier board 201 is removed to expose the conductive blocks 205 and contact pads 261 in the dielectric layer 220 . Next, a second carrying plate 280 is formed on the solder resist layer 210 relative to the conductive block 205 . In other words, the second carrying plate 280 does not cover the conductive block 205 . It should be understood that the structure of FIG. 2H is the structure of FIG. 2G turned upside down, so the lower solder resist layer 210 in FIG. 2H is the top solder resist layer 210 in FIG. 2G. In some embodiments, the second carrier plate 280 and the first carrier plate 201 include the same material.

Next, a connection substrate 271 (see FIG. 2J ) is formed on the dielectric layer 220 and the conductive block 205 . Specifically, first, referring to FIG. 2I , the insulating layer 270 is formed on the dielectric layer 220 and the conductive block 205 . In some embodiments, insulating layer 270 and dielectric layer 220 include different materials. Next, a laser drilling operation 20 is performed to form an opening O3 in the insulating layer 270 so that the opening O3 extends downward from the top of the insulating layer 270 to expose the pad 261 . The direction shown for laser drilling operation 20 may be the direction of travel of the laser beam. Due to the direction of the laser drilling operation 20 , the width of the opening O3 decreases along the direction from the insulating layer 270 to the dielectric layer 220 , that is, the opening O3 has a trapezoidal cross-sectional shape.

Conductive material is filled into the opening O3 to form a third via hole 264 on the pad 261 . Next, after repeating the steps of FIG. 2I , please refer to FIG. 2J to form a stacked third via hole 264 on the pad 261 and connect the first via hole 262 through the pad 261 . The third via hole 264 has the same appearance as the opening O3, so the width of the third via hole 264 also decreases along the direction from the insulating layer 270 to the dielectric layer 220. Therefore, the narrow end of the third via hole 264 (ie, the part with the smallest width) and the narrow end of the first via hole 262 are connected to the pad 261 from above and below respectively.

Referring to FIG. 2K , part of the insulating layer 270 is removed, leaving only the part of the insulating layer 270 around the third via hole 264 to form the connection member 273 . At the same time, the dielectric layer 220 is thinned so that the dielectric layer 220 has a protruding portion 221 on the surface relative to the solder resist layer 210 , and the protruding portion 221 is higher than the remaining portion of the dielectric layer 220 . In some embodiments, thinning the dielectric layer 220 may simultaneously expose the side surfaces of the conductive block 205 . In other words, the top surface of the conductive block 205 is made higher than the top surface of the remaining dielectric layer 220 . In some embodiments, plasma etching or laser etching may be used to remove the insulating layer 270 . In some embodiments, the top portion of third via hole 264 is exposed to the top surface of the remaining insulating layer 270 .

It should be noted that the third via hole 264 shown in FIG. 2K has a pad, but in other embodiments, the third via hole may not have a pad. In other words, during the process of removing the insulating layer 270 , the pad of the third via hole 264 may be removed, or the pad of the third via hole 264 may be retained.

According to different applications, the above-mentioned layer-adding method process of FIG. 2I and FIG. 2J can be repeated, that is, different stack numbers of third via holes 264 can be produced according to actual needs. If there is more than one stacked third via hole 264, you may choose to perform the steps of removing the insulating layer 270 and thinning the dielectric layer 220 after completing all the third via holes 264.

Referring to FIG. 2L , the conductive block 205 and the adhesive layer 207 are removed (refer to FIG. 2K ) to form the groove R1 and expose the narrow end portion 230A1 of the second via hole 230A. In some embodiments, the material of the conductive block 205 is different from the material of the second via hole 230A, so as to avoid damaging the narrow end portion 230A1 of the second via hole 230A during the etching process of removing the conductive block 205 and affecting subsequent processing. Application. In some embodiments, the height of the narrow end portion 230A1 of each second via hole 230A exposed in the groove R1 is the same.

Referring to FIG. 2M, an underfill layer 240 is formed in the groove R1 (refer to FIG. 2K) and bonded to the narrow end portion 230A1 (refer to FIG. 2K) of the second via hole 230A. In some embodiments, a solder ball (not shown) may be selectively disposed in the underfill layer 240 and electrically connected to the narrow end portion 230A1 of the second via hole 230A. Next, the chip 250 is bonded on the underfill layer 240 to form the packaging substrate structure 200 . In some embodiments, the second carrier plate 280 can be selectively removed, and an opening 215 is formed at the bottom of the exposed solder resist layer 210 and directly below the first via hole 262 to expose the solder pad (not shown in the figure). mark).

As mentioned above, the present invention provides a packaging substrate structure and a manufacturing method thereof, which can simultaneously fabricate and stack first via holes, second via holes, and third via holes to form connection members, thereby increasing circuit density in the substrate. Furthermore, using the narrow end of the second via hole as a connection pad of the chip can help reduce the pitch and improve the reliability of interconnection with the chip. In addition, the stacked third via hole is covered with an insulating layer to improve the stability of the connection component.

Although the present invention has been disclosed in several embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs can make various modifications without departing from the spirit and scope of the present invention. Modifications and modifications, therefore, the scope of protection of the present invention shall be determined by the appended patent application scope.

10,20: Laser drilling operation

100:Package substrate structure

101: Circuit substrate

110: Solder mask

115:Open your mouth

120:Dielectric layer

120B: Bottom surface

120T:Top surface

121:Protrusion

130: Second via hole

130A: Narrow end part

131: First via hole

132: Line layer

140: Bottom glue layer

142:Tin ball

150:wafer

161: Pad

162: First via hole

164:Third via hole

164A:Packing

170:Insulation layer

170T:Top surface

171:Connection components

200:Package substrate structure

201:First load-bearing plate

203:Metal layer

205:Conductive block

207: Adhesive layer

210: Solder mask

213:Metal layer

213T:Top

215:Open your mouth

220, 220A, 220B: dielectric layer

220A _T :Top surface

221:Protrusion

230: First via hole

230A: Second via hole

230A1: Narrow end part

232: Line layer

240: Bottom glue layer

250:wafer

261: Pad

262,262A,262B,262C: first via hole

264:Third via hole

270:Insulation layer

271:Connect base board

273:Connection components

280: Second load-bearing plate

O1: First opening

O2: Second opening

O3: Open your mouth

R1: Groove

The aspects of the present invention can be better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, the dimensions of many features can be arbitrarily scaled for clarity of discussion. [Fig. 1] illustrates a cross-sectional view of a packaging substrate structure according to some embodiments of the present invention. [FIG. 2A] to [FIG. 2M] illustrate cross-sectional views of intermediate stages of the manufacturing process of a packaging substrate structure according to some embodiments of the present invention.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Package substrate structure

101: Circuit substrate

110: Solder mask

115:Open your mouth

120:Dielectric layer

120B: Bottom surface

120T:Top surface

121:Protrusion

130: Second via hole

130A: Narrow end part

131: First via hole

132: Line layer

140: Bottom glue layer

142:Tin ball

150:wafer

161: Pad

162: First via hole

164:Third via hole

164A:Packing

170:Insulation layer

170T:Top surface

171:Connection components

Claims (12)

A method for manufacturing a packaging substrate structure, including: Provide a first load-bearing plate and a metal layer, wherein the metal layer is disposed on the surface of the first load-bearing plate; Patterning the metal layer to form at least one contact pad and partially exposing the first carrier board; Paste a conductive block on an exposed portion of the first carrier board; A substrate is formed on the first carrier plate, wherein the substrate includes: A dielectric layer is pressed on the surface of the first carrier board and covers the conductive block and the contact pad; A plurality of circuit layers formed on a surface of the dielectric layer away from the pad; A plurality of first via holes electrically connecting the circuit layer and the pad; and At least one second via hole electrically connects the conductive block and the circuit layer; Remove the first carrier board to expose the conductive block and the pad in the dielectric layer; Forming a connection substrate on the surface of the dielectric layer, wherein the connection substrate includes: An insulating layer covering the conductive block and the pad; and A plurality of third via holes penetrating the insulating layer and exposed to the top surface of the insulating layer, wherein the third via holes are electrically connected to the pads; Remove part of the insulating layer in the connection substrate, leaving only the insulating layer around the second via hole to form a plurality of connection members and expose the conductive block; Remove the conductive block to form a groove on the dielectric layer and expose a narrow end of the second via hole; and At least one chip is disposed on the second via hole. The manufacturing method of the packaging substrate structure as described in claim 1 further includes: Before removing the first carrier board, a solder resist layer is formed on the substrate. The manufacturing method of a packaging substrate structure as claimed in claim 2, wherein after removing the first carrier board, it further includes: A second carrying plate is formed on the solder resist layer relative to the conductive block. The manufacturing method of a packaging substrate structure as claimed in claim 1, wherein after pasting the conductive block, it further includes: Applying an adhesive layer on the conductive block, wherein the second via hole is formed on the adhesive layer, and the step of removing the conductive block further includes: Remove the adhesive layer. The manufacturing method of a packaging substrate structure as claimed in claim 1, wherein after removing part of the insulating layer and before removing the conductive block, it further includes: The dielectric layer is thinned to form at least one protrusion on a surface of the dielectric layer away from the circuit layer. The manufacturing method of a packaging substrate structure as claimed in claim 1, before bonding at least one chip, further comprising: An underfill layer is formed in the groove and on the second via hole. A packaging substrate structure including: A circuit substrate, including: a dielectric layer, wherein a first surface of the dielectric layer includes at least one protrusion; A plurality of circuit layers disposed on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface; A plurality of first via holes are provided in the dielectric layer; and At least one second via hole is provided in the dielectric layer, wherein the cross-sectional shape of the second via hole is a trapezoid and has a narrow end, and the narrow end protrudes from the third portion of the dielectric layer. a surface; A plurality of contact pads provided on the protruding portion; and A plurality of connecting members are provided on the pads, wherein each of the connecting members includes: At least one third via hole electrically connected to the pad; and An insulating layer covers the at least one third via hole, wherein the outermost one of the at least one third via hole is exposed to the top surface of the insulating layer. The packaging substrate structure of claim 7, wherein the pad and the circuit layer are electrically connected using the first via hole. The packaging substrate structure as described in claim 7 further includes: An underfill layer is provided on the narrow end of the second via hole. The packaging substrate structure of claim 7, wherein the cross-sectional shape of each of the first via holes is a trapezoid, and the width of the first via holes is along the second surface of the dielectric layer decreasing towards the first surface. The packaging substrate structure of claim 7, wherein the cross-sectional shape of each of the third via holes is a trapezoid, and the width of the third via holes is along the top surface of the insulating layer toward the The direction of the pads is decreasing. The packaging substrate structure as described in claim 7 further includes: At least one wafer or at least one semiconductor component is bonded to the second via hole.

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