201031300 六、發明說明 f發明所屬之技術領域】 本發明係有關於-種封裝基板㈣作方法，特别是有關於 具凹穴結構的高密度封裝基板的製作方法。 、 參 【先前技術】 近年來’三維立體㈣構裝的快速發展，除大幅縮小 將不同功能的晶片整合在同—構裝模組，達縣 更此 =ge，Sip)峨[射，層_獅娜糊维11 二封裝體3,層疊在第—封裝 。3有第—封裝體2’以及—第 片20’設於一第一基板22，:笛之上。第一封裝體2,包括一第一晶 •，如金線，與第一基接合 接合一模_，住= 201031300 片30’設於-第二基板32’上，第二晶片3〇，透過接合導㈣，與第二 基板32’構成雜連接，第一晶片3〇，與接合導線％，同樣被〆模塑 材料34’包覆住。第二封裝體3,的第二基板％，藉由錫球4〇，與第一 封裝體2’的第-基板22,構成電性連接，通常，在第一基板22，與第 二基板32’之間會填人底膠42,，以躺球你受料力破壞。 上述傳統層疊式封裝結構至少包括以下的缺點：⑴踢球4〇，的 參大小受限於第-基板22,與第二基板32，之間的距離。錫球4〇，的高 度必須超過模塑材料24,的高度，以確保第—基板22，盘第二基板％， 之間的電性連接，因而無法進一步縮小錫球節距(祕），導致錫球 40’的數目以及輸出輸入接腳(1/〇)數難以提升；（2)第一基板^，與 第二基板32’的熱膨脹係數(CTE)不_致錫球4〇，可能受到不同程 度的應力’影響到封裝體的可靠度；⑶錫球4〇，的共面性控制不 易，使得封裝製程的餘欲度(processwind〇w)較小；（句需額外進行第 藝-基板22,與第二基板32’之間的灌膠步驟；⑶堆§體積較大。 【發明内容】 ，本發明之主要目的在提供—種改㈣具败結_封裝基板的 製作方法’以解決並克服先前技藝之不足及缺點。 為達上述目的，本發明提供-種具凹穴結構的封裝基板的製作 方法，包含有：提供一連接板，包含有一第一線路層、覆蓋在該第 6 201031300 -線路層上的-第—防焊層、—接合Ί 供一主體雷踗扨曰°又於5亥第一防焊層上；提 ί、主體電路板，至少包含有—第二線路 杈 該第二線闕，其巾H隨I ^ 第-防焊層覆盖住 的該第二線路層有複數刪口，暴露出部分 於顧數個開Π内形成複數個 及將該連接板與社體電路缝合，使該 、卜， 覆壓合在該第-防焊層、該接合 t構被緊饮的包 構中 . 第一防焊層所構成的三明治結 ❹ 參 種具凹穴結構的封裝 根據本發明之較佳實施例，本發明提供一 的結構中 ==方法，包含有:提供一連接板，包含有-第-線路層、 在該第-線路層上的—第—防焊層、—接合層，設於該第一防 2上；提供-主體電路板，至少包含有—第二線路層及一第二防 2覆力蓋健第二線路層，其中該第二防焊層包含有複數個開口， ㈣出部分的該第二線路層；於該複數個開σ _成複數個導電凸 t構；以及將該連接板與該電路域合，使該導電凸塊結構 2緊㈣包觀合在該第―_層、雜合層及第二防騎所構成 6為了使貝審查委員能更進一步了解本發明之特徵及技術内 ，’請參_下有關本㈣之詳減__。飾所_式僅供 >考與輔賴_，並翻來對本發鴨叫限制者。 【實施方式】 7 201031300 本發明係·於-種具有凹穴結構的封裝基板賴作方法 ==Γ:Γ解決手段。本發_-種複合 合，:完=二的電路板與，電•結 、本發有凹雜構的職基板㈣作綠主要可分做三個部 β分，其中第-部分是形成具有預留開孔的連接板，第二部分是 主體電路板’第三部分是將連接板與主體電路板壓合。以下，即藉 由第U圖至第lc圖說明第-部分，藉由第2a圖及第2b圖說明第 一部分’藉由第3圖說明第三部分。 請參閱第la圖至第1C圖，其為依據本發曰月較佳實施例所緣示 的具有凹穴結構的封裝基板的製作方法㈣—部分的步驟，也就是 具有預留開孔的連接板的形成步驟。 首先，如第la圖所示，提供一連接板10，例如雙面電路板， 其包括一核心絕緣層12、設於連接板1〇的第一面1〇a上的第一線 路層14、設於連接板10的第二面10b上的第二線路層16、連接第 一線路層14與第二線路層16的導電通孔18、覆蓋在連接板1〇的 第一面10a上的防焊層22，以及覆蓋在連接板1〇的第二面上 的防焊層24。 201031300 其中，防焊層22中形忐古·„ ^ 成有開口 22a，暴露出部分的第一線路層 14，防焊層24中則形成有開 令開口 24a，暴露出部分的第二線路層16。 在經由開口 22a及開口 24a異命山认你 暴路出的第一線路層14上’可以形成有 錄金層14a。 為簡化說明’本發明較佳實施例僅以雙面雙層電路板做說明， 當然，熟習該項技藝者應當理解亦可以採用四層板、六層板等多層 ❹線路板作為本發明的連接板。此外’連接板1〇的形成可以用銅箱基 板為起始材料，並包括利用微影、磁彳、雷射穿孔、電鑛、印刷等 等的製程步驟’例如，第-線路層14及第二線路層16可以利用微 影及触刻製程來定義’導電通孔18係以雷射穿孔技術及電鑛技術來 形成。由於上述微影、蝕刻、雷射穿孔、電鍍、印刷等等的製程步 驟均為習知，因此不重複贅述。 ©接著’如第lb圖所不’在連接板1〇的第二面的防焊層24 上，層疊一接合層26。接合層20中已預先形成有複數個開孔26a , 其相對應於防焊層24中的開口 24a。接合層26中的開孔26a可以 利用雷射技術或沖壓等方式形成。 根據本發明較佳實施例，接合層26可以是一黏膠層、介電層或 預浸材(prepreg)。接合層26可以是一感光材料層，而另外透過曝光 及顯影製程，在感光材料層中形成開孔26a。 201031300 接下來，如第lc圖所示，在連接板1〇的預定區域形成貫穿連 接板10的開孔10c。根據本發明較佳實施例，形成開孔的方法 可以採用雷射技術、CNC繞走切除、沖壓等技術。 請參閱第2a圖至第2b圖，其為依據本發明較佳實施例所繪示 的具有凹穴結構的封裝基板的製作方法的第二部分的步驟也就'是 形成主體電路板的步驟。 ❹ 如第2a圖所示，先提供一主體電路板30，其可以是多層電路 板，例如四層板或六層板。為簡化說明，本發明較佳實施例僅以四 層電路板做說明，當然，熟習該項技藝者應當理解亦可以採用六層 板等其它多層線路板。主體電路板3〇包括一核心絕緣層32、設於 主體電路板30的第一面3〇a上的第一線路層34、設於主體電路板 30的第二面30b上的第二線路層36、連接第一線路層34與第二線 路層36的導電通孔38、設在主體電路板30的第一面3(^上的增層 介電層112、設於主體電路板3〇的第二面3〇b上的增層介電層114、 位於增層介電層H2上的增層線路層44、位於增層介電層114上的 增層線路層46、連接增層線路層44與第一線路層34的導電通孔 48、連接增層線路層46與第二線路層％的導電通孔％、覆蓋在主 體電路板30的第-面3〇a上的防焊層122，以及覆蓋在主體電路板 30的第二面3〇b上的防焊層124。 其中，防焊層122中形成有開口 122a，暴露出部分的增層線路 201031300 層44,防谭層124中則形成有開口⑽，暴露出部分的增層線路層 46。在經由開口 122a及開口 ma暴露出的部分增層線路層糾上， 例如位於主體電路板30的第一面灿上的一晶片安置區域勘内的 轉接指(b〇ndfmger)440上，可以形成有錄金層他，以方便後續與 金線做連接。其中，晶片安置區域2〇〇相對應於連接板⑺的開孔 1 Πη 〇 ® 請同時參閱第2b圖、第3圖，接著在主體電路板30的第一面 3〇a上的晶片安置區域勘以外的區域，經由開口肋暴露出的增 層線路層44上，形成導電凸塊結構6〇，例如，锡、錫秦鋼合金 (SAC)、銅膏、銀膏、導電樹脂等，其可以_網版印刷技術或其 他射方法形成。根據本發明較佳實施例，導電凸塊結構⑼的高度 h需高出防焊層122的表面。此外，高度h必須大於防焊層24的開 口 24a深度與接合層26厚度的加總，以確保在後續的步驟中，增層 參線路層44能夠與第二線路層16有效的電連接。 曰 請參閱第3圖’其為依據本發明較佳實施例所繪示的具有凹穴 結構的封裝基板的製作方法的第三部分的步驟，也就是將連接板與 主體電路板壓合’以構成具有凹穴結構的封裝基板。 如第3圖所示’將第lc圖中的連接板10與第2b圖中的主體電 路板30進行壓合’最後構成本發明具有凹穴結翻塊基板。 壓合後’連接板10的開孔10c暴露出位於主體電路板3〇上的晶片 11 201031300 安置區域200以及晶片安置區域2〇〇 _轉接指44〇，此外 接合層26緊密的將連接板10的防焊層％與主體電路㈣的 層m黏固，使導電凸塊結構6〇有效的將增層線路層44與第 路層16電連接在-起，而導電凸塊結構6〇被緊密的包覆壓合在防 焊層24、接合層26及防焊層122所構成的結構中其間幾乎 空隙，這餅導電凸塊結構6G在面對應力時的可靠度大幅提昇。 第4a圖及第4b圖緣示的是將本發明具有凹穴結構的封裝基板 應用在層疊式封裝製程的示意圖。如第4a圖所示，將一晶片置 於晶片安置區域200内，其中，晶片8〇上設有複數個連接塾82， 透過金線84接合至相對應的轉接指44〇上。接著，將填充材料％， 例如，樹脂，填入開孔10c並將晶片80以及金線84包覆起來。填 充材料86的表面約略與防焊層22的表面同一平面。 如第4b圖所示’隨後於防焊層22以及填充材料％上方層疊一 1C封裝體300，包括一封裝基板31〇、複數個錫球322設於封裝基 板310的下表面並接合至相對應的開口 22a、晶片38〇設於封裝基 板310的上表面，以及模封材料386，包覆住晶片38〇以及連接晶 片380與封裝基板310的金線384。 本發明具有凹穴結構的封裝基板應用在層疊式封裝結構時，至 少包括以下的優點：（1)錫球322的大小不會受限於封裝基板31〇 與基板30之間的距離，因此可以進一步縮小錫球間距，提升錫球數 12 201031300 目以及輸出輸入接腳(I/o)數；⑺導電凸塊結構6〇被緊密的包霞 合在防焊層24、接合層26及防焊層122所構成的結構中，其間幾 乎沒有二P承’這使得導電凸塊結構6〇在面對應力時的可靠度大幅提 昇；⑶共面性控制容易，使得封裝製程的餘欲度(pr〇cesswind〇w) 較大；⑷不需額外進行灌膠步驟；（5)堆疊體積較小。 本發明另一較佳實施例提供另一種具有凹穴結構的封裝基板的 _製作方法，·可分做三個部分，其中第—部分是提供—主體電路 板’第二部分是形成具有預留開孔的連接板，第三部分是將連接板 與主體電路板壓合並進行連接板的導電盲孔製程。以下，即藉由第 5圖說明第一部分，藉由第如圖至第6(1圖說明第二部分，藉由第 7a圖至第7d圖說明第三部分。 首先，如第5圖所示，提供一主體電路板4〇〇，其可以是多層 藝電路板，例如四層板或六層板。為簡化說明，本發明較佳實施例僅 以四層電路板做說明，當然，熟習該項技藝者應當理解亦可以採用 六層板等其它多層線路板。主體電路板4〇〇至少包括一設於主體電 路板400的第一面400a上的第一線路層412以及設於主體電路板 400的第二面4〇〇b上的第二線路層414。當然，主體電路板4〇〇中 還有增層介電層及連接各層線路的導電通(盲)孔等等，不再詳加扩 述。覆蓋在主體電路板400的第一面400a上的是防焊層4〇2，覆1 住位於主體電路板4〇〇的第一面4〇〇a上的第一線路層Μ〕，其耳有 一開孔402a ’暴露出一連接墊412a。此外，第一線路層412另包人 13 201031300 -轉接墊獅’其位於主體電路板彻的第一面條的周圍區域。 凊參閱第6a圖至帛Μ圖’其為依據本發明另一較佳實施例所 繪示的具有喊結構的封裝基板的製作方法的第二部分的步驟也 就是形成具有預留開孔的連接板的步驟。 首先，如第6a圖所示，提供一連接板5〇〇，其包括—核心絕緣 ❹層51〇、設於連接板500的第一面500a上的第一線路層512，及設 於連接板500的第二面500b上的第二線路層514。接著，對連接板 5〇〇進行-鑽孔製程，在連接板5〇〇的一周圍區域，形成複數個相 對應於轉接墊412b的貫穿孔502。 接著，如第6b圖所示，進行一微影以及蝕刻製程，將設於連接 板500的第二面500b上的第二線路層514定義成線路圖案μ如。 ❹ 接著，如第6c圖所示，在連接板500的第二面500bi，層疊 一接合層516。接合層516蓋住貫穿孔5〇2，形成盲孔5〇2b。根據 本發明較佳實施例，接合層516可以是一黏膠層、介電層、預浸材 (Pfepreg)或感光材料層。 接下來，如第6d圖所示，在連接板500的預定區域形成貫穿第 一線路層512、核心絕緣層510及接合層516的開孔520。形成開孔 520的方法可以採用雷射技術、CNC繞走切除、沖壓等技術。 14 201031300 明參閱第7a圖至第7d圖’其為依據本發明另—較佳實施例所 繪示的具有凹穴結構的封裝基板的製作方法的第三部分的步驟，也 就是將連接板與織缝合，以構献有凹穴結構贿裝基板。 如第7a圖所不，將第6d圖中的連接板5〇〇與第$圖中的主體 電路板4〇0進行壓合，最後構成本發明具有凹穴結構的封裝基板 ❹麵。壓合後，連接板500的開孔520暴露出位於主體電路板3〇上 的晶片安置區域900以及晶片安置區域_内的連接塾仙，此 外’利用接合層516緊密的將連接板5〇〇與主體電路板4〇〇的防焊 層402黏固。然後進行鑽孔製程，例如雷射飢，經由連接板· 的盲孔502b燒轉接合層5! 6以及主體電路板4〇〇的防焊層搬， 形成盲孔502c ’並暴露出部分的轉接墊412b。 如第几圖所示，接著在封裝基板800的一周圍區域(晶片安置 區域900以外的區域)形成一化學銅層6〇2，其中，化學鋼層⑻2共 形地覆蓋在盲孔502c的底部及側壁上，並且覆蓋在第一線路層512 上。根據本發明另一較佳實施例，化學銅層6〇2的厚度約丨微米。 此外，在封裝基板800的周圍區域沈積化學銅層6〇2時，可以利用 乾膜將晶片安置區域9〇〇保護起來。 \如第7e圖所示’接著進行—導電膠填孔製程’藉由例如網版印 刷等技術，將導電膠61〇，例如銀膠、導電高分子等導電材料，直 15 201031300 接填滿盲孔502c。 如第7d圖所示’接著進行微影及蝕刻製程，將化學銅層6〇2、 第一線路層512以及導電膠61〇定義成内連結構71〇，並將第二線 路層414定義成線路圖案4i4a。最後，於内連結構71〇上以及晶片 安置區域900内的連接墊412a上形成鎳金層62〇。在後續步驟中， 内連結構710可與另-封裝基板或封裝體(圖未示)的錫球構成電連 ⑩接’而在晶片安置區域_内，可以將或積體電路容置於開 孔520内，並透過打線將晶片與晶片安置區域900内的連接墊412a 電連接。 乂上所述僅為本發明之較佳實施例’凡依本發明申請專利範圍 所做之均等與修飾，皆制本發明之涵蓋範圍。 【圖式簡單說明】 參 第1圖縿示的是傳統層疊式封裝結構的勤結構示意圖。 第la圖至第1C圖為依據本發明較佳實施例靖示 的封裝基板的製作方法的第—部分的步驟。 胃八4 =====爾增有凹穴結構 的製作方法的第三例所繪—有凹穴結構的封裝基板 16 201031300 第4a圖及第4b圖緣示的县脸士 在賴獅縣物有喊_騎基板 第5圖為依據本發明另— 基板的製物⑽―部^/。崎谢㈣結構的封敦 第6a圖至第6d圖為依據本發明另― 〃 m 結構的封裝基板的製作方法的[部分的步^、、，示的具有凹穴 第7a圖及第7d㈣依據本發明另—較佳 結構的封裝基板的製作方法的第三部分的步驟％示的具有凹穴 【主要元件符號說明】 1層疊式封裝結構 2’第一封裝體 3第二封裝體 20’第一晶片 22’第-基板 24、34’模塑材料 26’接合導線 30’第二晶片 32’第二基板 36’接合導線 40’锡球 42’底膠 17 201031300 ίο連接板 10a、30a、400a、500a 第一面 10b、30b、400b、500b 第二面 10c、26a、402a、520 開孔 12、32、510核心絕緣層 14、34、412、512 第一線路層 14a、44a鎳金層 φ 16、36、414、514 第二線路層 18、38、48、58導電通孔 22、24、122、124 防焊層 22a、24a、122a、124a 開口 26、516接合層 30主體電路板 44、46增層線路層 ^ 60導電凸塊結構 80、380晶片 82、412a連接墊 84、384金線 86填充材料 100封裝基板 112、114增層介電層 200、900晶片安置區域 3001C封裝體 18 201031300 310、800封裝基板 322錫球 386模封材料 440轉接指 400主體電路板 402防焊層 412b轉接墊 φ 4Ma、5Ha線路圖案 500連接板 500b第二面 502貫穿孔 502b、502c 盲孔 514a線路圖案 602化學銅層 _ 610導電膠 ❿ 620鎳金層 710内連結構 800封裝基板 19BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a package substrate (four), and more particularly to a method for fabricating a high-density package substrate having a recessed structure. In the recent years, the rapid development of the three-dimensional (four) configuration, in addition to the large reduction of the different functions of the wafer integrated in the same - structure module, Daxian more = ge, Sip) 峨 [shot, layer _ Liona paste 1 2 package 3, laminated in the first package. The first package body 2' and the first film piece 20' are disposed on a first substrate 22, above the flute. The first package 2 includes a first crystal, such as a gold wire, and is bonded to the first substrate, and the die is placed on the second substrate 32'. The bonding guide (4) is connected to the second substrate 32', and the first wafer 3, and the bonding wire %, are also covered by the molding material 34'. The second substrate % of the second package 3 is electrically connected to the first substrate 22 of the first package 2 ′ by solder balls 4 , generally, the first substrate 22 and the second substrate 32 . 'There will be a bottom glue 42 between them, and you will be damaged by the lying ball. The above conventional stacked package structure includes at least the following disadvantages: (1) The size of the kick ball 4 is limited by the distance between the first substrate 22 and the second substrate 32. The height of the solder ball 4 must exceed the height of the molding material 24 to ensure the electrical connection between the first substrate 22 and the second substrate %, so that the solder ball pitch cannot be further reduced, resulting in The number of solder balls 40' and the number of output input pins (1/〇) are difficult to increase; (2) the thermal conductivity coefficient (CTE) of the first substrate ^ and the second substrate 32' is not caused by the tin ball 4 Different degrees of stress 'affects the reliability of the package; (3) the solder ball 4 〇, the coplanarity control is not easy, making the process process's residual power (processwind 〇 w) is small; 22, the step of potting between the second substrate 32'; (3) the bulk of the stack is larger. [Summary of the Invention] The main purpose of the present invention is to provide a method for making a change (four) with a knot _ package substrate to solve In order to achieve the above object, the present invention provides a method for fabricating a package substrate having a recessed structure, comprising: providing a connection board, including a first circuit layer, covering the sixth 201031300 - On the circuit layer - the first - solder mask, - Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί Ί The second circuit layer covered by the solder resist layer has a plurality of cut-outs, and a plurality of exposed portions are formed in the plurality of openings, and the connecting plate is stitched with the social circuit, so that the covering and the pressing are combined The first solder resist layer, the joint t structure is in a tightly packed composition. The sandwich layer formed by the first solder resist layer is encapsulated with a recessed structure. According to a preferred embodiment of the present invention, the present invention provides a The structure of the == method includes: providing a connecting board, including a - first-circuit layer, a - solder resist layer on the first wiring layer, a bonding layer, disposed on the first protection 2 Providing a main circuit board comprising at least a second circuit layer and a second anti-2 cover force cover second circuit layer, wherein the second solder resist layer comprises a plurality of openings, and (4) the second portion of the output portion a circuit layer; the plurality of open σ _ into a plurality of conductive convex t structures; and the connecting plate is combined with the circuit domain to make the conductive Block structure 2 tightly (four) package is combined with the first layer, the hybrid layer and the second anti-riding structure 6 in order to enable the shell review committee to further understand the characteristics and technology of the present invention, 'please refer to the relevant (4) The detailed reduction __. The decoration _ is only for the > test and supplement _, and turned over to the hair duck called the limiter. [Embodiment] 7 201031300 The present invention is a package with a recess structure Substrate-based method==Γ:ΓResolution means. The present invention _-species composite,: the circuit board of the end = two, the electric junction, the front of the board with concave concave structure (four) for green can be divided into three The portion β is divided into a connecting plate having a reserved opening, and a second portion is a main circuit board. The third portion is to press the connecting plate with the main circuit board. Hereinafter, the first part will be explained by the U to lc, and the first part will be explained by the second and second figures. The third part will be explained by the third drawing. Please refer to FIG. 1 to FIG. 1C , which are diagrams of a method for fabricating a package substrate having a recess structure according to a preferred embodiment of the present invention (four)—partial steps, that is, a connection having a reserved opening. The step of forming the board. First, as shown in FIG. 1a, a connecting board 10, such as a double-sided circuit board, is provided, which includes a core insulating layer 12, a first circuit layer 14 disposed on the first surface 1A of the connecting board 1〇, a second wiring layer 16 disposed on the second surface 10b of the connecting board 10, a conductive via 18 connecting the first wiring layer 14 and the second wiring layer 16, and an anti-overlay covering the first surface 10a of the connecting board 1 The solder layer 22, and the solder resist layer 24 covering the second surface of the connecting plate 1A. 201031300, wherein the solder resist layer 22 is shaped to have an opening 22a, and a portion of the first circuit layer 14 is exposed. The solder resist layer 24 is formed with an opening 24a and a second circuit layer of the exposed portion. 16. A gold layer 14a may be formed on the first circuit layer 14 which is vented through the opening 22a and the opening 24a. For the sake of simplicity, the preferred embodiment of the present invention is only a double-sided double-layer circuit. The board is explained. Of course, those skilled in the art should understand that a multi-layered circuit board such as a four-layer board or a six-layer board can also be used as the connecting board of the present invention. Further, the formation of the connecting board 1 can be started from the copper box substrate. Starting materials, and including process steps using lithography, magnetic enthalpy, laser perforation, electric ore, printing, etc. 'For example, the first-line layer 14 and the second wiring layer 16 can be defined by lithography and a lithography process' The conductive via 18 is formed by a laser perforation technique and an electric ore technique. Since the above-described process steps of lithography, etching, laser perforation, electroplating, printing, etc. are well known, the description will not be repeated. Figure lb is not 'in the connection board On the second surface of the solder resist layer 24, a bonding layer 26 is laminated. A plurality of openings 26a are formed in the bonding layer 20 corresponding to the openings 24a in the solder resist layer 24. The bonding layer 26 is formed. The opening 26a can be formed by laser technology or stamping, etc. According to a preferred embodiment of the invention, the bonding layer 26 can be an adhesive layer, a dielectric layer or a prepreg. The bonding layer 26 can be a The photosensitive material layer is additionally formed with an opening 26a in the photosensitive material layer through an exposure and development process. 201031300 Next, as shown in FIG. 1c, an opening 10c penetrating the connecting plate 10 is formed in a predetermined region of the connecting plate 1? According to a preferred embodiment of the present invention, the method of forming the opening may employ laser technology, CNC bypass cutting, stamping, etc. Please refer to Figures 2a to 2b, which are drawn in accordance with a preferred embodiment of the present invention. The second step of the method of fabricating the package substrate having the recessed structure is also the step of forming the main body circuit board. ❹ As shown in Fig. 2a, a main circuit board 30 is provided, which may be a multi-layer circuit. Board, such as a four-layer board or six layers In order to simplify the description, the preferred embodiment of the present invention is described by only four layers of circuit boards. Of course, those skilled in the art should understand that other multi-layer circuit boards such as six-layer boards can also be used. The main circuit board 3 includes a core insulation. The layer 32, the first circuit layer 34 disposed on the first surface 3a of the main circuit board 30, the second circuit layer 36 disposed on the second surface 30b of the main circuit board 30, and the first circuit layer 34 are connected The conductive vias 38 of the second circuit layer 36, the build-up dielectric layer 112 disposed on the first surface 3 of the main circuit board 30, and the second surface 3〇b disposed on the main surface of the main circuit board 3 The dielectric layer 114, the build-up wiring layer 44 on the build-up dielectric layer H2, the build-up wiring layer 46 on the build-up dielectric layer 114, and the conductive connection between the build-up wiring layer 44 and the first trace layer 34. The via hole 48, the conductive via hole % connecting the build-up wiring layer 46 and the second wiring layer %, the solder resist layer 122 covering the first surface 3〇a of the main body circuit board 30, and the overcoat layer 30 covering the main body circuit board 30 The solder mask layer 124 on the second side 3〇b. An opening 122a is formed in the solder resist layer 122, and a portion of the build-up line 201031300 is exposed, and an opening (10) is formed in the anti-tank layer 124 to expose a portion of the build-up wiring layer 46. The portion of the build-up wiring layer exposed through the opening 122a and the opening ma is corrected, for example, on a transfer finger (b〇ndfmger) 440 in a wafer placement area on the first surface of the main circuit board 30. A gold layer is formed to facilitate the subsequent connection with the gold wire. Wherein, the wafer placement area 2 〇〇 corresponds to the opening 1 Π 〇 〇 of the connection board (7). Please refer to FIG. 2b and FIG. 3 simultaneously, and then the wafer placement area on the first side 3〇a of the main circuit board 30. The conductive region is formed on the build-up wiring layer 44 exposed through the opening ribs, for example, tin, tin-steel alloy (SAC), copper paste, silver paste, conductive resin, etc., which may be _ Screen printing technology or other shooting methods. In accordance with a preferred embodiment of the present invention, the height h of the conductive bump structure (9) needs to be higher than the surface of the solder resist layer 122. In addition, the height h must be greater than the sum of the depth of the opening 24a of the solder mask 24 and the thickness of the bonding layer 26 to ensure that the build-up wiring layer 44 can be electrically connected to the second wiring layer 16 in a subsequent step. Please refer to FIG. 3, which is a step of the third part of the manufacturing method of the package substrate having the recess structure according to the preferred embodiment of the present invention, that is, pressing the connecting board with the main circuit board. A package substrate having a recessed structure is formed. As shown in Fig. 3, the connecting plate 10 in Fig. 1c is pressed against the main body circuit board 30 in Fig. 2b. Finally, the present invention has a recessed bumping substrate. After the press-fitting, the opening 10c of the connecting board 10 exposes the wafer 11 201031300 mounting area 200 on the main body circuit board 3 and the wafer mounting area 2〇〇_transfer finger 44〇, and the bonding layer 26 tightly connects the connecting board The solder resist layer % of 10 is adhered to the layer m of the main circuit (4), so that the conductive bump structure 6 〇 effectively electrically connects the build-up wiring layer 44 and the via layer 16 to each other, and the conductive bump structure 6 is The tight cladding is pressed into the structure formed by the solder resist layer 24, the bonding layer 26 and the solder resist layer 122, and the gap between the solder bump structure 6G is greatly improved when facing the stress. 4a and 4b are schematic views showing the application of the package substrate having the recessed structure of the present invention to a stacked package process. As shown in Fig. 4a, a wafer is placed in the wafer placement area 200, wherein a plurality of ports 82 are disposed on the wafer 8 and bonded to the corresponding transfer fingers 44 through the gold wires 84. Next, a filler material %, for example, a resin, is filled in the opening 10c and the wafer 80 and the gold wire 84 are covered. The surface of the filling material 86 is approximately flush with the surface of the solder resist layer 22. As shown in FIG. 4b, a 1C package 300 is stacked on the solder resist layer 22 and the filler material %, and includes a package substrate 31, and a plurality of solder balls 322 are disposed on the lower surface of the package substrate 310 and bonded to the corresponding surface. The opening 22a, the wafer 38 is disposed on the upper surface of the package substrate 310, and the molding material 386 covers the wafer 38 and the gold wire 384 connecting the wafer 380 and the package substrate 310. When the package substrate having the recessed structure of the present invention is applied to the stacked package structure, at least the following advantages are included: (1) the size of the solder ball 322 is not limited by the distance between the package substrate 31 and the substrate 30, and thus Further reduce the pitch of the solder balls, increase the number of solder balls 12 201031300 and the number of output input pins (I/o); (7) the conductive bump structure 6〇 is tightly wrapped in the solder resist layer 24, the bonding layer 26 and the solder resist In the structure formed by the layer 122, there is almost no two P-bearing therebetween. This makes the reliability of the conductive bump structure 6〇 in the face of stress greatly increased; (3) the coplanarity control is easy, and the redundancy of the packaging process is made (pr 〇cesswind〇w) is larger; (4) no additional potting step is required; (5) the stacking volume is small. Another preferred embodiment of the present invention provides another method for fabricating a package substrate having a recessed structure, which can be divided into three parts, wherein the first portion is provided - the main circuit board 'the second portion is formed with a reservation The connecting plate of the opening, the third part is a conductive blind hole process for pressing the connecting plate and the main circuit board to form a connecting plate. Hereinafter, the first part will be described with reference to Fig. 5, and the third part will be explained by the seventh to seventh figures, as shown in Fig. 5 through Fig. 6 (first embodiment). Providing a main circuit board 4〇〇, which may be a multi-layer art board, such as a four-layer board or a six-layer board. For simplicity of description, the preferred embodiment of the present invention is described by only four layers of boards, of course, familiar with It should be understood by those skilled in the art that other multi-layer circuit boards such as a six-layer board can also be used. The main circuit board 4A includes at least a first circuit layer 412 disposed on the first surface 400a of the main circuit board 400 and a main circuit board. The second circuit layer 414 on the second side 4〇〇b of the 400. Of course, the main circuit board 4〇〇 also has a build-up dielectric layer and conductive (blind) holes connecting the lines of the layers, etc., no longer detailed Overlaid on the first surface 400a of the main circuit board 400 is a solder resist layer 4〇2 covering the first wiring layer on the first surface 4〇〇a of the main circuit board 4〇〇 〕, the ear has an opening 402a' exposing a connection pad 412a. In addition, the first circuit layer 412 is another person 13 2010 31300 - Transfer lion lion 'is located in the surrounding area of the first noodle of the main circuit board. 凊 See Fig. 6a to '', which is a shouting structure according to another preferred embodiment of the present invention. The second part of the method of fabricating the package substrate is the step of forming a connection plate having a reserved opening. First, as shown in FIG. 6a, a connection plate 5 is provided, which includes a core insulating layer 51〇, a first circuit layer 512 disposed on the first surface 500a of the connection board 500, and a second circuit layer 514 disposed on the second surface 500b of the connection board 500. Next, the connection board 5〇〇 is performed - In the drilling process, a plurality of through holes 502 corresponding to the transfer pads 412b are formed in a peripheral region of the connecting plate 5A. Next, as shown in FIG. 6b, a lithography and etching process is performed, which will be provided in The second wiring layer 514 on the second face 500b of the connection board 500 is defined as a wiring pattern μ. ❹ Next, as shown in Fig. 6c, a bonding layer 516 is laminated on the second surface 500bi of the connection board 500. 516 covers the through hole 5〇2 to form a blind hole 5〇2b. According to the present invention, For example, the bonding layer 516 may be an adhesive layer, a dielectric layer, a prepreg or a photosensitive material layer. Next, as shown in FIG. 6d, a predetermined area is formed in the connecting plate 500 to penetrate the first line. The layer 512, the core insulating layer 510 and the opening 520 of the bonding layer 516. The method of forming the opening 520 can adopt the techniques of laser technology, CNC bypass cutting, stamping, etc. 14 201031300 See Figures 7a to 7d for details. The third part of the method for fabricating a package substrate having a recessed structure according to another preferred embodiment of the present invention, that is, the connecting plate and the woven fabric are stitched to form a recessed structure bribe substrate . As shown in Fig. 7a, the connecting plate 5A of Fig. 6d is pressed together with the main circuit board 4?0 of Fig. $, and finally, the package substrate having the recessed structure of the present invention is constructed. After the pressing, the opening 520 of the connecting plate 500 exposes the wafer seating area 900 on the main circuit board 3 and the connection in the wafer placement area, and further, the connecting board 5 is tightly closed by the bonding layer 516. It is adhered to the solder resist layer 402 of the main circuit board 4A. Then, a drilling process, such as laser hunger, is performed, and the bonding layer 5! 6 and the solder resist layer of the main circuit board 4 are burned through the blind hole 502b of the connecting plate, and the blind hole 502c' is formed and the portion is exposed. Transfer pad 412b. As shown in the figures, a chemical copper layer 6〇2 is then formed in a peripheral region of the package substrate 800 (region outside the wafer placement region 900), wherein the chemical steel layer (8) 2 conformally covers the bottom of the blind via 502c. And on the sidewall, and overlying the first circuit layer 512. According to another preferred embodiment of the invention, the thickness of the chemical copper layer 6〇2 is about 丨 microns. Further, when the chemical copper layer 6?2 is deposited in the peripheral region of the package substrate 800, the wafer placement region 9 can be protected by the dry film. \As shown in Fig. 7e, 'following - conductive adhesive filling process', by means of techniques such as screen printing, conductive adhesive 61, such as silver glue, conductive polymer and other conductive materials, straight 15 201031300 filled with blind Hole 502c. As shown in FIG. 7d, 'the lithography and etching process is followed, and the chemical copper layer 〇2, the first wiring layer 512, and the conductive paste 61〇 are defined as the interconnect structure 71〇, and the second wiring layer 414 is defined as Line pattern 4i4a. Finally, a nickel-gold layer 62 is formed on the interconnect structure 71 and on the connection pads 412a in the wafer placement region 900. In the subsequent step, the interconnect structure 710 can be electrically connected to the solder ball of the other package substrate or the package (not shown). In the wafer placement area, the integrated circuit can be placed in the open circuit. Within the aperture 520, the wafer is electrically connected to the connection pads 412a in the wafer placement area 900 by wire bonding. The above description of the preferred embodiments of the present invention is intended to be within the scope of the present invention. [Simple description of the diagram] Refer to Figure 1 for a schematic diagram of the structure of the traditional stacked package structure. 1 to 1C are steps of a first part of a method of fabricating a package substrate according to a preferred embodiment of the present invention. Stomach VIII 4 ===== 增 第三 第三 有 有 有 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三The object has a shouting _ riding the substrate Fig. 5 is a further object of the present invention - the substrate (10) - part ^ /. 6a to 6d of the structure of Fengshen (4) is a method for fabricating a package substrate according to another 〃 m structure according to the present invention. [Parts of the steps, paragraphs 7a and 7d (4) The step of the third part of the method for fabricating the package substrate of the preferred structure of the present invention has a recess shown in the figure [main element symbol description] 1 laminated package structure 2' first package 3 second package 20' A wafer 22' first substrate 24, 34' molding material 26' bonding wire 30' second wafer 32' second substrate 36' bonding wire 40' solder ball 42' primer 17 201031300 ίο connection plates 10a, 30a, 400a 500a first side 10b, 30b, 400b, 500b second side 10c, 26a, 402a, 520 opening 12, 32, 510 core insulating layer 14, 34, 412, 512 first circuit layer 14a, 44a nickel gold layer φ 16, 36, 414, 514 second circuit layer 18, 38, 48, 58 conductive vias 22, 24, 122, 124 solder resist layers 22a, 24a, 122a, 124a openings 26, 516 bonding layer 30 main circuit board 44, 46 build-up circuit layer ^ 60 conductive bump structure 80, 380 wafer 82, 412a connection pad 84, 384 gold wire 8 6 filling material 100 packaging substrate 112, 114 build-up dielectric layer 200, 900 wafer placement area 3001C package 18 201031300 310, 800 package substrate 322 solder ball 386 molding material 440 transfer finger 400 main circuit board 402 solder resist layer 412b Transfer pad φ 4Ma, 5Ha line pattern 500 connection plate 500b second face 502 through hole 502b, 502c blind hole 514a line pattern 602 chemical copper layer _ 610 conductive adhesive 620 nickel gold layer 710 interconnect structure 800 package substrate 19