TWI507096B - Multilayer printed circuit board and method for manufacturing same - Google Patents

Description

Multilayer circuit board and manufacturing method thereof

The present invention relates to circuit board technology, and more particularly to a multilayer circuit board having a recess and a method of fabricating the same.

In the information, communications and consumer electronics industries, circuit boards are an essential component of all electronic products. With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided circuit boards to double-sided circuit boards and multilayer circuit boards. Multilayer boards, especially buried multi-layer boards with embedded electronic components, are widely used, see Takahashi, A. et al., 1992, IEEE Trans.on Components, Packaging, and Manufacturing Technology. The document "High density multilayer printed circuit board for HITAC M~880".

A multilayer circuit board in which electronic components are embedded generally has a recess for embedding electronic components. However, on the one hand, the presence of the recess reduces the area of the circuit design, so that the buried circuit board may have a large thickness; on the other hand, the assembly of electronic components in the recess is prone to poor assembly, so It affects the yield and quality of the board.

In view of this, it is necessary to provide a multi-layer circuit board having a groove with a good product quality and a manufacturing method thereof.

Hereinafter, a multilayer circuit board and a method of fabricating the same will be described by way of embodiments.

A method of fabricating a multilayer circuit board, comprising the steps of: providing an insulating substrate having opposing first and second surfaces; forming at least one through hole penetrating the first surface and the second surface in the insulating substrate, and Forming a first blind trench pattern exposed only on the first surface and a second blind trench pattern exposed only on the second surface; depositing a conductive material on the insulating substrate by a plating technique to fill the conductive material in the at least one pass Forming at least one conductive hole in the hole, filling a first line pattern in the first blind groove pattern, and filling a second line pattern in the second blind groove pattern, the first line pattern being embedded in the insulating substrate and Flush with the first surface, the second line pattern is embedded in the insulating substrate and flush with the second surface, the first line pattern has an assembly area and a nip area surrounding the connection assembly area, the first The circuit pattern is electrically connected to the second line pattern through the at least one conductive hole; forming a first press-substrate substrate on the first surface of the insulating substrate to obtain a multi-layer substrate, the first press-fit The board includes a first conductive circuit layer and a first film, the first film is pressed between the first conductive circuit layer and the first surface, the first conductive circuit layer is electrically connected to the first line pattern; The assembly area corresponds to the first pressed substrate, thereby forming an exposed groove in the multilayer substrate, and the assembly area is exposed in the groove.

Preferably, after forming an exposed recess in the multilayer substrate, the method further includes the step of mounting an electronic component in the recess, the electronic component being electrically connected to the assembly area of the first wiring pattern.

Preferably, the assembly area includes a plurality of pads, and the electronic component has a plurality of connection terminals one-to-one corresponding to the plurality of pads, each of the connection terminals being electrically connected to one of the pads by a solder ball bump .

A multilayer circuit board comprising a first press-fit substrate and a circuit substrate that are pressed together. The first press-fit substrate includes a first conductive circuit layer and a first film. The circuit substrate includes an insulating substrate, a first line pattern, a second line pattern, and at least one conductive hole. The insulating substrate has opposing first and second surfaces, and the first film is located between the first conductive circuit layer and the first surface. The first line pattern, the second line pattern and the at least one conductive hole are both embedded in the insulating substrate. The at least one conductive hole is exposed on the first surface and the second surface, and is flush with both the first surface and the second surface. The first line pattern is only exposed to the first surface and is flush with the first surface, the first line pattern comprising an assembly area and a nip area surrounding the connection assembly area. The second line pattern is only exposed on the second surface and flush with the second surface, and the second line pattern is electrically connected to the first line pattern through the at least one conductive hole. The multilayer circuit board has a recess extending through the first press-fitted substrate, the recess corresponding to the assembly area, the assembly area being exposed in the recess.

A multilayer circuit board comprising a first laminated substrate, a circuit substrate and an electronic component. The first press-bonding substrate is pressed together with the circuit substrate. The first press-fit substrate includes a first conductive circuit layer and a first film. The circuit substrate includes an insulating substrate, a first line pattern, a second line pattern, and at least one conductive hole. The insulating substrate has opposing first and second surfaces, and the first film is located between the first conductive circuit layer and the first surface. The first line pattern, the second line pattern and the at least one conductive hole are both embedded in the insulating substrate. The at least one conductive hole is exposed on the first surface and the second surface, and is flush with both the first surface and the second surface. The first line pattern is only exposed to the first surface and is flush with the first surface, the first line pattern comprising an assembly area and a nip area surrounding the connection assembly area. The second line pattern is only exposed on the second surface and flush with the second surface, and the second line pattern is electrically connected to the first line pattern through the at least one conductive hole. The multilayer circuit board has a recess extending through the first press-fit substrate, the recess corresponding to the assembly area, the assembly area being exposed in the recess, the electronic component being received in the recess and mounted In the assembly area of the circuit substrate.

In the technical solution, a circuit substrate having a buried circuit is formed by forming a blind trench pattern in an insulating substrate and then depositing a conductive material by a plating technique, and the circuit substrate is used as a core of a multilayer circuit board having a groove The board has at least the following advantages: on the one hand, the pads of the circuit substrate exposed in the groove are separated from each other by the material of the insulating substrate, and the tin bridge phenomenon does not occur when assembling the electronic component, thereby ensuring the assembly yield; On the other hand, the circuit substrate can conveniently realize the design of the thin circuit, and can also reduce the thickness of the entire multilayer circuit board, thereby facilitating the thinning and miniaturization of the circuit board.

100‧‧‧Insulation base

111‧‧‧ first surface

112‧‧‧ second surface

120‧‧‧Double-sided copper clad substrate

121‧‧‧Upper copper foil

122‧‧‧Bottom copper foil

130‧‧‧through hole

131‧‧‧First blind groove pattern

132‧‧‧second blind groove pattern

14‧‧‧Electrical materials

101‧‧‧Electrical hole

11‧‧‧First line graphics

12‧‧‧Second line graphics

10‧‧‧Line substrate

1101‧‧‧ Assembly area

1102‧‧‧ nip area

113‧‧‧ pads

114‧‧‧ lines

15‧‧‧Protective film

21, 61‧‧‧ first pressed substrate

22, 62‧‧‧ second press-substrate

211‧‧‧First conductive circuit layer

212‧‧‧First film

221‧‧‧Second conductive circuit layer

222‧‧‧second film

210‧‧‧First copper foil

220‧‧‧second copper foil

102‧‧‧First blind via

103‧‧‧Second blind guide hole

10a‧‧‧ four-layer substrate

213‧‧‧ first opening

31, 71‧‧‧ grooves

41, 81‧‧‧First solder mask

42. 82‧‧‧Second solder mask

10b, 10c‧‧‧ four-layer circuit board

50, 90‧‧‧ Electronic components

51, 91‧‧‧ Connection terminals

52, 92‧‧‧ solder ball bumps

612‧‧‧ Third film

610‧‧‧third copper foil

622‧‧‧Fourth film

620‧‧‧fourth copper foil

104‧‧‧ third blind via

105‧‧‧4th blind via

106‧‧‧through holes

611‧‧‧ Third conductive circuit layer

621‧‧‧fourth conductive layer

10d‧‧‧six-layer substrate

613‧‧‧ second opening

10e, 10f‧‧‧ six-layer circuit board

FIG. 1 is a schematic diagram of a double-sided copper-clad substrate provided by a first embodiment of the present technical solution.

2 is a schematic view of an insulating substrate provided by a first embodiment of the present technical solution.

3 is a schematic view of the insulating substrate of FIG. 2 after ablation using a laser.

4 is a schematic view of a conductive material deposited on the insulating substrate of FIG.

FIG. 5 is a schematic diagram of a circuit substrate according to a first embodiment of the present technical solution.

Figure 6 is a top plan view of Figure 5.

Fig. 7 is a schematic view showing the provision of a protective film on the circuit substrate of Fig. 5.

Fig. 8 is a schematic view showing the film and the copper foil are respectively pressed on the upper and lower sides of the circuit substrate of Fig. 7.

Figure 9 is a schematic view showing the formation of a blind via in a pressed film.

Fig. 10 is a schematic view showing a four-layer substrate obtained by forming a pressed copper foil into a conductive wiring layer.

Figure 11 is a schematic view showing the formation of a groove in the four-layer substrate of Figure 10.

Fig. 12 is a schematic view showing the assembly of electronic components in the grooves of the four-layer substrate of Fig. 11.

Fig. 13 is a schematic view showing the film and the copper foil are respectively pressed on the upper and lower sides of the four-layer substrate of Fig. 10.

Figure 14 is a schematic view of a blind via hole formed in a pressed film.

Fig. 15 is a schematic view showing a six-layer substrate obtained by forming a pressed copper foil into a conductive wiring layer.

Figure 16 is a schematic view showing the formation of a groove in a six-layer substrate.

17 is a schematic view of a six-layer circuit board obtained after forming a solder resist layer on both sides of the six-layer substrate of FIG.

Fig. 18 is a schematic view showing the assembly of electronic components in the recess of the six-layer circuit board of Fig. 17.

The multi-layer circuit board provided by the technical solution and the manufacturing method thereof will be further described in detail below with reference to the accompanying drawings and embodiments.

The manufacturing method of the multi-layer circuit board provided by the first embodiment of the present technical solution includes the following steps:

In the first step, referring to FIG. 1 and FIG. 2, an insulating substrate 100 having opposing first surface 111 and second surface 112 is provided.

The insulating substrate 100 may be a purchased insulating sheet or may be formed by etching a commercially available copper clad substrate. In this embodiment, the insulating substrate 100 is formed by: first, as shown in FIG. 1 , a double-sided copper-clad substrate 120 is provided, the double-sided copper-clad substrate 120 including the insulating substrate 100 and being bonded thereto The upper side copper foil 121 and the lower side copper foil 122 on both sides of the insulating substrate 100; secondly, as shown in FIG. 2, the double-sided copper-clad substrate 120 is etched by a chemical etching solution, thereby removing the upper side copper foil 121 and the lower side copper foil 122, That is, the insulating substrate 100 is formed. The insulating substrate 100 has a thickness of 40 to 80 μm.

In the second step, referring to FIG. 3, at least one through hole 130 penetrating the first surface 111 and the second surface 112 is formed in the insulating substrate 100 by using the laser ablation insulating substrate 100, and is formed only to be exposed on the first surface 111. The first blind groove pattern 131 and the second blind groove pattern 132 exposed only to the second surface 112. The first blind groove pattern 131 is configured to form a line pattern, and includes a plurality of first blind grooves, the plurality of first blind grooves having substantially the same depth and different shapes, and the plurality of first blind grooves corresponding to the line shape The blind slot has a plurality of blind slots corresponding to the shape of the pad. The second blind groove pattern 132 is also used to form a line pattern including a plurality of second blind grooves having substantially the same depth and different shapes, and also including a plurality of lines corresponding to the line shape. The blind slot has a plurality of blind slots corresponding to the shape of the pad. Preferably, the depth of the first blind groove is equal to the depth of the second blind groove. In general, the first blind groove and the second blind groove have a depth of 15-25 microns.

In a third step, referring to FIG. 4, a conductive material 14 is deposited on the insulating substrate 100 by a plating technique to deposit the conductive material 14 in the at least one via 130, the first blind trench pattern 131, and the second blind trench pattern. 132. The conductive material 14 may be copper, a material such as carbon black, nickel, silver, gold, or the like, or a combination of the above materials. E.g A chemical copper layer or a carbon black layer may be deposited on the surface of the insulating substrate by an electroless copper plating process or a blackening process, and then an electroplated copper layer may be deposited on the surface of the chemical copper layer or the carbon black layer by an electroplating copper process, so that all copper may be formed. The conductive material 14 or the conductive material 14 composed of carbon black and copper.

It will be understood by those of ordinary skill in the art that if the first surface 111 and the second surface 112 are not masked prior to deposition of the conductive material 14, the conductive material 14 is also deposited on the first surface 111 and the second surface 112. In addition, in order to ensure that sufficient conductive material 14 is deposited in the at least one via 130, the first blind trench pattern 131, and the second blind trench pattern 132, the plating time is generally slightly extended, so that deposition is performed on at least one pass. The conductive material 14 in the hole 130, in the first blind groove pattern 131, and in the second blind groove pattern 132 protrudes from the first surface 111 and the second surface 112.

Referring to FIG. 5, after the conductive material 14 is deposited, the conductive material 14 protruding from the first surface 111 and the second surface 112 is removed by a step of rubbing or etching. That is, the conductive material 14 deposited on the first surface 111 and the second surface 112 will be removed while the conductive material 14 deposited in the at least one via 130 is flush with the first surface 111 and the second surface 112, respectively. The conductive material 14 in the first blind trench pattern 131 is flush with the first surface 111, and the conductive material 14 in the second blind trench pattern 132 is flush with the second surface 112. Thereby, the conductive material 14 is filled in the at least one through hole 130 to form at least one conductive hole 101, and the first blind pattern 131 is filled in the first blind groove pattern 131 to form the first line pattern 11, and the second blind groove pattern 132 is filled in the second line. Line graphic 12. The first line pattern 11 is embedded in the insulating substrate 100 and flush with the first surface 111. The second line pattern 12 is embedded in the insulating substrate 100 and flush with the second surface 112. The first line pattern 11 and the second line pattern 12 each include a plurality of conductive lines and a plurality of pads, and the conductive lines and pads in the first line pattern 11 are both opposite to the first surface 111. Flush, the conductive lines and pads in the second line pattern 12 are flush with the second surface 112. Thus, the closely coupled insulating substrate 100, the first wiring pattern 11 and the second wiring pattern 12 can constitute the wiring substrate 10 having the embedded wiring pattern.

Of course, those skilled in the art can understand that if the first surface 111 and the second surface 112 are shielded before depositing the conductive material 14, the plating conditions and the plating time are strictly controlled during plating so that deposition is performed. The conductive material 14 in the at least one through hole 130 is exactly flush with the first surface 111 and the second surface 112, respectively, and the conductive material 14 in the first blind groove pattern 131 is flush with the first surface 111, and the second blind groove pattern The conductive material 14 in the 132 is flush with the second surface 112, and then the wiring substrate 10 is obtained without removing the conductive material 14 protruding from the first surface 111 and the second surface 112 by a step of rubbing or etching.

In the present embodiment, the first line pattern 11 is defined to include an assembly area 1101 and a nip area 1102 that is circumferentially connected around the assembly area 1101, as shown in FIG. In this embodiment, the assembly area 1101 is rectangular, and has at least a plurality of pads 113. The nip 1102 surrounds the assembly area 1101, and has at least a plurality of lines 114. It will be understood by those skilled in the art that the number and shape of the pads and lines in the first line pattern 11 depend on the circuit design of the board, and generally have more pads and lines, in the diagram of this embodiment. 5 and FIG. 6, only one line 114 of the nip 1102 is schematically depicted, schematically depicting two pads 113 of the assembly area 1101.

In the fourth step, referring to FIG. 7, a protective film 15 is disposed in the assembly area 1101 of the first line pattern 11 to protect the pads 113 in the assembly area 1101. The protective film 15 may be a release film. The cross-sectional area of the protective film 15 may be equal to or slightly smaller than the cross-sectional area of the assembly area 1101, and only the lines and pads 113 in the assembly area 1101 need to be sufficiently covered. In this embodiment, the cross-sectional area of the protective film 15 is slightly smaller than the assembly area. The cross-sectional area of 1101.

In the fifth step, referring to FIG. 8 to FIG. 10, the first pressing substrate 21 is press-fitted on the first surface 111 side of the circuit substrate 10, and the second pressing substrate 22 is formed on the second surface 112 side. The first pressing substrate 21 is electrically connected to the first line pattern 11, and the second pressing substrate 22 is electrically connected to the second line pattern 12.

In this embodiment, the first laminated substrate 21 is a single-layer substrate including a first conductive circuit layer 211 and a first film 212, and the second pressed substrate 22 is also a single-layer substrate including a second conductive circuit layer. 221 and second film 222. Specifically, the pressing of the first pressing substrate 21 and the second pressing substrate 22 can be achieved by first providing the first film 212, the first copper foil 210, the second film 222, and the second copper foil 220; A film 212 is placed on the first surface 111 and covers the protective film 15, the first copper foil 210 is placed on the upper side of the first film 212, and the second film 222 is also disposed on the second surface 112, and the second copper foil 220 is placed. Placed on the lower side of the second film 222, that is, the first copper foil 210, the first film 212, the circuit substrate 10, the second film 222, and the second copper foil 220 are sequentially stacked; then the stacked first copper foil 210, The first film 212, the circuit substrate 10, the second film 222, and the second copper foil 220 are placed in a press machine, and the first copper foil 210, the first film 212, the circuit substrate 10, and the second film 222 are pressed together at a time. The second copper foil 220 is formed into a four-ply laminate as shown in FIG. Secondly, at least one first blind hole and at least one second blind hole are formed in the four laminated ply by a laser drilling technique, and the at least one first blind hole penetrates only the first copper foil 210 of the first press-substrate 21 And the first film 212, the at least one second blind hole only penetrates the second copper foil 220 and the second film 222 of the second press-substrate 22; and then passes through an electroless copper plating process and an electroplating copper process in the at least one Depositing a copper layer in a blind hole and at least one second blind hole, thereby forming the at least one first blind hole into the first blind via hole 102 and the second blind hole into the second hole The blind via 103 is as shown in FIG. Again, the first copper foil 210 and the second copper foil 220 are selectively etched by an image transfer process and a chemical etching process, thereby forming the first copper foil 210 into the first conductive wiring layer 211 and the second copper foil 220 The second conductive circuit layer 221 is electrically connected to the first circuit pattern 11 through the at least one first blind via 102, and the second conductive circuit layer 221 passes through the at least one second blind via 103 and the second line pattern. 12 is electrically conducted, and thus the four-layer substrate 10a as shown in FIG. 10 can be obtained. The first conductive circuit layer 211 and the second conductive circuit layer 221 each have a plurality of conductive lines and a plurality of pads, and the specific circuit design can be determined according to requirements.

Preferably, when the first copper foil 210 is selectively etched, a portion of the first copper foil 210 corresponding to the boundary of the assembly region 1101 is etched away, and a first portion corresponding to the boundary of the assembly region 1101 is formed in the first conductive wiring layer 211. Opening 213.

In the sixth step, referring to FIG. 11, a portion of the first press-substrate substrate 21 corresponding to the assembly area 1101 is removed, so that a single-layer substrate 10a is formed in the four-layer substrate 10a and penetrates only the first press-fit substrate 21 and corresponds to the assembly area 1101. The groove 31 is removed, and the protective film 15 attached to the surface of the assembly area 1101 is removed.

Specifically, the groove 31 may be formed by first cutting the first pressing substrate 21 along the boundary of the assembly area 1101 using a laser, that is, cutting the first conductive wiring layer 211 and the first film 212. After the cutting, the portion of the first pressing substrate 21 above the assembly area 1101 is separated from the first pressing substrate 21 of the other regions, that is, the first pressing substrate 21 above the assembly region 1101 and the nip region 1102 The upper first press-substrate substrates 21 are separated from each other. Thus, the recess 31 can be formed by peeling off the first press-fit substrate 21 corresponding to the assembly area 1101. In this embodiment, due to the presence of the first opening 213 in the first conductive circuit layer 211, the first film 212 is directly cut from the first opening 213 along the boundary of the assembly area 1101 by laser, and then the assembly area 1101 is directly peeled off. Above The portion of the first film 212 can remove the portion of the first press-substrate substrate 21 corresponding to the assembly area 1101, thereby forming the recess 31. It will be understood by those of ordinary skill in the art that when the adhesion between the protective film 15 and the first film 212 is good and the adhesion to the surface of the assembly area 1101 is poor, that is, between the protective film 15 and the first film 212 When the adhesive force is better than the adhesion between the protective film 15 and the surface of the assembly area 1101, the protective film 15 can be peeled off from the surface of the self-assembly area 1101 when the first film 212 is peeled off; when the protective film 15 and the first film 212 are When the adhesive force is poor and the adhesion to the surface of the assembly area 1101 is good, that is, when the adhesive force between the protective film 15 and the first film 212 is worse than the adhesion between the protective film 15 and the surface of the assembly area 1101, The protective film 15 may be peeled off from the surface of the assembly area 1101 after the first film 212 is peeled off. At this time, after the first film 212 is peeled off, the protective film 15 is exposed in the groove 31, and the protective film 15 can be peeled off from the surface of the assembly area 1101 relatively easily, exposing the land 113 of the assembly area 1101.

The groove 31 has a shape and a position corresponding to the assembly area 1101. In the embodiment, the shape of the groove 31 corresponds to the shape and position of the assembly area 1101 shown in FIG. 6, that is, the groove 31 is located. A rectangular blind groove in the middle of the four-layer substrate 10a.

Before forming the recess 31 or after forming the recess 31, a first solder resist layer 41 may be disposed on the surface of the first conductive trace layer 211, and a second solder resist layer 42 may be disposed on the surface of the second conductive trace layer 221 to protect The first conductive wiring layer 211 and the wiring and pads in the second conductive wiring layer 221 . Thus, the four-layer circuit board 10b having the recess 31 can be obtained.

In the seventh step, referring to FIG. 12, the electronic component 50 is mounted in the recess 31, and the electronic component 50 is electrically connected to the assembly area 1101 of the first line pattern 11. Specifically, the electronic component 50 is first provided, which may be an active component or a passive component, such as a crystal sheet. The surface of the electronic component 50 has a plurality of connection terminals 51 that are in one-to-one correspondence with the plurality of pads 113 in the assembly area 1101. Next, solder ball bumps 52 are disposed on the surface of each of the connection terminals 51, and the electronic components 50 are placed in the recesses 31 such that each of the pads 113 is bonded to the solder bumps 52 of the surface of the connection terminal 51 corresponding thereto. Contact. Again, each solder ball bump 52 is melted and solidified by reflow soldering to electrically connect a connection terminal 51 and a pad 113. In this way, the electrical connection between the electronic component 50 and the first line pattern 11 can be realized, and the four-layer circuit board 10c in which the electronic component 50 is mounted can be obtained.

Preferably, a package adhesive material may be filled between the electronic component 50 and the recess 31 to better fix the electronic component 50.

The four-layer circuit board 10c obtained according to the above steps of the first embodiment, as shown in FIG. 12, includes a first solder resist layer 41, a first press-bonding substrate 21, a circuit substrate 10, a second press-substrate 22, and a The second solder resist layer 42 and the electronic component 50. The first press-bonded substrate 21, the circuit substrate 10, and the second press-bonded substrate 22 are sequentially pressed together. The first press-fit substrate 21 includes a first conductive wiring layer 211 and a first film 212. The first solder resist layer 41 is disposed on the surface of the first press-bonding substrate 21 and covers the first conductive wiring layer 211. The second pressing substrate 22 includes a second conductive circuit layer 221 and a second film 222. The second solder resist layer 42 is disposed on the surface of the second press-bonding substrate 22 and covers the surface of the second conductive wiring layer 221 . The circuit substrate 10 includes an insulating substrate 100 and a first wiring pattern 11 embedded in the insulating substrate 100, a second wiring pattern 12, and at least one conductive hole 101. Wherein, the first line pattern 11 is only exposed on the first surface 111 and flush with the first surface 111, and the second line pattern 12 is only exposed on the second surface 112 and flush with the second surface 112. The conductive holes 101 are exposed on the first surface 111 and the second surface 112 and are flush with the first surface 111 and the second surface 112 for electrically connecting the first line pattern 11 and the second line pattern 12. The first conductive line layer 211, the first line pattern 11, the second line pattern 12, and the second conductive line layer 221 are electrically conducted through the conductive via 101, the first blind via 102, and the second blind via 103. The four-layer circuit board 10c has a recess 31 extending through the first press-fit substrate 21 and the first solder resist layer 41, and the recess 31 is a blind groove exposed to the outside. The assembly area 1101 of the first line pattern 11 is exposed in the groove 31. The electronic component 50 is disposed in the recess 31 and is mounted on the plurality of pads 113 of the assembly area 1101 and exposed. The electronic component 50 has a plurality of connection terminals 51 that are electrically connected to the first line pattern 11 by a plurality of solder ball bumps 52.

Since the first line pattern 11 is embedded in the insulating substrate 100, the pads 113 are separated by the material of the insulating substrate 100. Therefore, when the electronic component 50 is assembled in the recess 31, the solder bumps 52 are formed. There is no phenomenon of a solder bridge between them, which ensures the assembly rate of the electronic component 50.

In addition, since the first line pattern 11 is formed by post-etch plating, the design of the thin line can be conveniently realized; and since the first line pattern 11 is embedded in the insulating substrate 100, it can be reduced compared to the prior art. The thickness of the entire four-layer circuit board 10c realizes thinning and miniaturization of the circuit board.

It will be understood by those of ordinary skill in the art that the steps in the method of fabricating a multilayer circuit board of the first embodiment are not all necessary technical features. For example, in the third step, the first pressing substrate 21 may be pressed only on the upper side of the circuit substrate 10 without simultaneously pressing the second pressing substrate 22 on the lower side of the circuit substrate 10, so that after the subsequent steps, A three-layer circuit board having a recess is formed. Also, the components in the four-layer circuit board 10c manufactured in the first embodiment are not all necessary technical features, for example, the first solder resist layer 41 and the second solder resist layer 42. In addition, the first conductive circuit layer 211, the first line pattern 11, the second line pattern 12, and the second conductive line layer 221 are not limited to The electrical hole 101, the first blind via 102 and the second blind via 103 are electrically connected, or the first blind via 102 and the second blind via 103 are not formed, and at least one via extending through the four-layer circuit board 10c is formed. Realize the electrical conduction of each layer.

Of course, it will be understood by those of ordinary skill in the art that in addition to fabricating a three-layer circuit board or a four-layer circuit board having one recess, the present technology can fabricate a multilayer circuit board of any number of layers having any number of grooves. For example, more than one groove, for example two or three grooves, may be formed in the sixth step, so that a multilayer circuit board having two or more grooves can be formed. Further, for example, by continuing to form a film and a copper foil on both sides of the four-layer substrate 10a shown in FIG. 10, a multilayer circuit board of four or more layers can be obtained. Hereinafter, a six-layer circuit board having one groove will be described as an example.

A method for fabricating a multilayer circuit board according to a second embodiment of the present technical solution includes the steps of:

In the first step, referring to Fig. 7, the circuit substrate 10 after the protective film 15 is obtained obtained in the fourth step of the first embodiment is provided.

In the second step, referring to FIG. 8 to FIG. 10 and FIG. 13 to FIG. 15, the first pressing substrate 61 is press-fitted on the first surface 111 side of the insulating substrate 100, and the second surface 112 is pressed to form the first surface. The substrate 62 is pressed and the first pressing substrate 61 is electrically connected to the first wiring pattern 11, and the second pressing substrate 62 is electrically connected to the second wiring pattern 12.

In the present embodiment, the first press-fit substrate 61 is a multi-layer substrate including a first film 212, a first conductive circuit layer 211, a third film 612, and a third conductive circuit layer 611, and the second pressed substrate 62 is also The multilayer substrate includes a second film 222, a second conductive wiring layer 221, a fourth film 622, and a fourth conductive wiring layer 621. Specifically, forming the first pressed substrate 61 and the second pressed substrate 62 can be achieved by the following process: Referring to FIG. 8 to FIG. 10, the first film 212 and the first conductive circuit layer 211 are formed on the first surface 111 side of the circuit substrate 10 by the specific steps in the fifth step of the first embodiment. The second surface 112 of the circuit substrate 10 is pressed to form a second film 222 and a second conductive circuit layer 221. The first conductive circuit layer 211 is electrically connected to the first line pattern 11 through the at least one first blind via hole 102. The conductive circuit layer 221 is electrically conducted to the second wiring pattern 12 through the at least one second blind via 103, so that the four-layer substrate 10a as shown in FIG. 10 can be obtained. Next, referring to FIG. 13, a third film 612, a third copper foil 610, a fourth film 622, and a fourth copper foil 620 are provided; a third film 612 is placed over the first conductive circuit layer 211, and a third copper foil is disposed. 610 is placed on the third film 612, and the fourth film 622 is also disposed under the second conductive circuit layer 221, and the fourth copper foil 620 is placed on the lower side of the fourth film 622, that is, the third copper foil 610, the third The film 612, the four-layer substrate 10a, the fourth film 622, and the fourth copper foil 620 are sequentially stacked; then the stacked third copper foil 610, third film 612, four-layer substrate 10a, fourth film 622, and fourth copper foil are stacked. The 620 is placed in a press machine to press the third copper foil 610, the third film 612, the four-layer substrate 10a, the fourth film 622 and the fourth copper foil 620 at a time to form a six-ply laminate, as shown in FIG. Show. Again, at least one third blind via, at least one fourth blind via and at least one via are formed in the six ply by drilling techniques, the at least one third blind via only the third copper foil 610 and the third The film 612, the at least one fourth blind hole penetrates only the fourth copper foil 620 and the fourth film 622, and the at least one through hole penetrates the third copper foil 610, the third film 612, the four-layer substrate 10a, and the fourth film. 622 and a fourth copper foil 620; then depositing a copper layer in the at least one third blind via, the at least one fourth blind via, and the at least one via through an electroless copper plating process and an electroplating copper process, thereby The at least one third blind hole is formed as a third blind via 104, the fourth blind via is formed as a fourth blind via 105, and the at least one via is formed as a via 106, as shown in FIG. Finally, through image transfer process and The etching process selectively etches the third copper foil 610 and the fourth copper foil 620, thereby forming the third copper foil 610 into the third conductive wiring layer 611, and forming the fourth copper foil 620 into the fourth conductive wiring layer 621. The third conductive circuit layer 611 is electrically connected to the first conductive circuit layer 211 through at least one third blind via 104, and the fourth conductive trace layer 621 is electrically connected to the second conductive trace layer 221 through at least one fourth blind via 105, at least one The via hole 106 can electrically conduct the third conductive circuit layer 611, the first conductive circuit layer 211, the first line pattern 11, the second line pattern 12, the second conductive line layer 221, and the fourth conductive line layer 621. A six-layer substrate 10d as shown in FIG. The third conductive circuit layer 611 and the fourth conductive circuit layer 621 each have a plurality of conductive lines and a plurality of pads, and the specific circuit design can be determined according to requirements.

Preferably, when the third copper foil 610 is selectively etched, a portion of the third copper foil 610 corresponding to the boundary of the assembly region 1101 is etched away, and a second portion corresponding to the boundary of the assembly region 1101 is formed in the third conductive wiring layer 611. The opening 613, the second opening 613 and the first opening 213 correspond to each other.

In the third step, referring to FIG. 16, a portion of the first press-substrate substrate 61 corresponding to the assembly area 1101 is removed, thereby forming a single-layered substrate 10d that penetrates only the first press-fit substrate 61 and corresponds to the assembly area 1101. The groove 71 is removed, and the protective film 15 attached to the surface of the assembly area 1101 is removed.

Specifically, the groove 71 may be formed by first cutting the first pressing substrate 61 along the boundary of the assembly area 1101 by using a laser, that is, cutting the third conductive circuit layer 611, the third film 612, and the first conductive circuit layer. 211 and the first film 212. After the cutting, the portion of the first pressing substrate 61 above the assembly area 1101 is separated from the first pressing substrate 61 of the other regions, that is, the first pressing substrate 61 above the assembly area 1101 and the nip area 1102 The upper first pressing substrates 61 are separated from each other. So, the stripping group The portion of the first press-substrate 61 above the loading area 1101 forms a recess 71. In this embodiment, the second opening 613 of the third conductive circuit layer 611 and the first opening 213 of the first conductive circuit layer 211 are present, and since the second opening 613 and the first opening 213 are both associated with the assembly area 1101 The boundary correspondingly, so that the third film 612 and the first film 212 are directly cut by the laser from the second opening 613, the first pressing substrate 61 located above the assembly area 1101 can be peeled off from the surface of the circuit substrate 10.

It will be understood by those of ordinary skill in the art that when the adhesion between the protective film 15 and the first film 212 is good and the adhesion to the surface of the assembly area 1101 is poor, that is, between the protective film 15 and the first film 212 When the adhesive force is better than the adhesion between the protective film 15 and the surface of the assembly area 1101, the protective film 15 can be peeled off from the surface of the self-assembly area 1101 when the first film 212 is peeled off; when the protective film 15 and the first film 212 are When the adhesive force is poor and the adhesion to the surface of the assembly area 1101 is good, that is, when the adhesive force between the protective film 15 and the first film 212 is worse than the adhesion between the protective film 15 and the surface of the assembly area 1101, The protective film 15 may be peeled off from the surface of the assembly area 1101 after the first film 212 is peeled off. At this time, after the first film 212 is peeled off, the protective film 15 is exposed in the groove 71, and the protective film 15 can be peeled off from the surface of the assembly area 1101 relatively easily, exposing the land 113 of the assembly area 1101.

After the first press-bonded substrate 61 corresponding to the assembled portion 1101 is peeled off and the protective film 15 is peeled off, the groove 71 can be formed. The groove 71 is a blind groove that is exposed to the shape and position of the assembly area 1101. The assembly area 1101 is exposed in the recess 71, that is, the pad 113 is also exposed. In the present embodiment, the recess 71 is a rectangular blind groove corresponding to the shape and position of the assembly area 1101 shown in FIG.

Referring to FIG. 17, after the recess 71 is formed, a first solder resist layer 81 is further disposed on the surface of the third conductive circuit layer 611, and a second solder resist layer is disposed on the surface of the fourth conductive trace layer 621. 82, thereby protecting the lines and pads in the third conductive wiring layer 611 and the fourth conductive wiring layer 621. Thus, a six-layer circuit board 10e having the recess 71 can be obtained.

It will be understood by those of ordinary skill in the art that the first solder mask layer 81 and the second solder resist layer 82 may also be formed prior to forming the recess 71. At this time, the first solder resist layer 81 may be formed only on the surface of the third conductive wiring layer 611 corresponding to the nip region 1102; or, the first solder resist layer 81 may be formed on the entire surface of the third conductive wiring layer 611. It is only necessary to simultaneously remove the portion of the first solder resist layer 81 corresponding to the assembly region 1101 when the first press-bonded substrate 61 corresponding to the assembled region 1101 is peeled off.

In the fourth step, referring to FIG. 18, an electronic component 90 is mounted in the recess 71, and the electronic component 90 is electrically connected to the assembly area 1101 of the first line pattern 11. Specifically, the electronic component 90 is first provided, and the electronic component 90 can be an active component or a passive component such as a capacitor, a resistor, a wafer, or the like. The surface of the electronic component 90 has a plurality of connection terminals 91 that are in one-to-one correspondence with the plurality of pads 113 in the assembly area 1101. Next, solder ball bumps 92 are disposed on the surface of each of the connection terminals 91, and the electronic components 90 are placed in the recesses 71 such that each of the pads 113 is bonded to the solder bumps 92 of the surface of the connection terminal 91 corresponding thereto. Contact. Again, each solder ball bump 92 is melted and solidified by reflow soldering to electrically connect a connection terminal 91 and a pad 113. Thus, the electrical connection between the electronic component 90 and the first line pattern 11 can be realized, and the six-layer circuit board 10f on which the electronic component 90 is mounted can be obtained.

Preferably, a package adhesive material may also be filled between the electronic component 90 and the six-layer circuit board 10e.

The six-layer circuit board 10f obtained according to the above steps of the second embodiment is as shown in FIG. 18, and includes a first solder resist layer 81, a first press-bonding substrate 61, a circuit substrate 10, a second press-substrate 62, and a The second solder mask layer 82 and the electronic component 90. The first pressed substrate 61, The circuit substrate 10 and the second pressing substrate 62 are sequentially pressed together. The first pressing substrate 61 includes a third conductive wiring layer 611, a third film 612, a first conductive wiring layer 211 and a first film 212 which are sequentially bonded. The first solder resist layer 81 is disposed on the surface of the third conductive wiring layer 611. The second pressing substrate 62 includes a fourth conductive wiring layer 621, a fourth film 622, a second conductive wiring layer 221 and a second film 222 which are sequentially bonded. The second solder resist layer 82 is disposed on the surface of the fourth conductive circuit layer 621. The circuit substrate 10 includes an insulating substrate 100 and a first wiring pattern 11, a second wiring pattern 12, and at least one conductive hole 101 embedded in the insulating substrate 100 as described above. The third conductive circuit layer 611, the first conductive circuit layer 211, the first circuit pattern 11, the second circuit pattern 12, the second conductive circuit layer 221, and the fourth conductive circuit layer 621 pass through the conductive hole 101, the first blind via 102, The second blind via hole 103, the third blind via hole 104, the fourth blind via hole 105, and the via hole 106 are electrically connected to each other. The six-layer circuit board 10f has a recess 71 penetrating through the first press-fit substrate 61, and the recess 71 is a blind groove exposed to the outside. That is, the first solder resist layer 81 exposes the groove 71. The assembly area 1101 of the first line pattern 11 is exposed in the recess 71. The electronic component 90 is disposed in the recess 71, is mounted on the plurality of pads 113 of the assembly area 1101, and is exposed. The electronic component 90 has a plurality of connection terminals 91 that are electrically connected to the plurality of pads 113 of the first line pattern 11 by a plurality of solder ball bumps 92.

Since the first line pattern 11 is embedded in the insulating substrate 100, the pads 113 are separated by the material of the insulating substrate 100. Therefore, when the electronic component 90 is assembled in the recess 71, the solder bumps 92 are formed. There is no solder bridge between the two, which ensures the assembly rate of the electronic components 90. In addition, since the first line pattern 11 is formed by post-etch plating, the design of the thin line can be conveniently realized; and since the first line pattern 11 is embedded in the insulating substrate 100, it can be reduced compared to the prior art. The thickness of the entire six-layer circuit board 10f makes the board thin and light and short Small.

It will be understood by those of ordinary skill in the art that variations of the above steps of the present teachings can be used to make other layers of multi-layer boards having other numbers of grooves. For example, by continuing to press-fit the film and the copper foil on the upper side or both sides of the six-layer substrate 10d of Fig. 15, a multilayered circuit board having a larger number of layers can be produced. That is, the number of layers of the first laminated substrate in the multilayer circuit board produced by the present technical solution is not limited, and may also include three or more conductive wiring layers. Of course, the number of grooves in the multilayer circuit board is not limited, and may be two, three or more, and may be opened as needed in the number of electronic components mounted in the multilayer circuit board.

In the process of fabricating a multi-layer circuit board of the present technical solution, a circuit substrate having a buried circuit is formed by forming a blind groove pattern in an insulating substrate and then depositing a conductive material by a plating technique, and the circuit substrate has a concave shape. The core board of the multi-layer circuit board of the slot has at least the following advantages: on the one hand, the pads of the circuit substrate exposed in the recess are separated from each other by the material of the insulating substrate, and the solder bridge does not occur when the electronic component is assembled. On the other hand, the circuit substrate can conveniently realize the design of the thin circuit, and can also reduce the thickness of the entire multilayer circuit board, and is beneficial to realize the thinning and miniaturization of the circuit board.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

10f‧‧‧Six-layer circuit board

61‧‧‧First press-fit substrate

10‧‧‧Line substrate

62‧‧‧Second pressed substrate

71‧‧‧ Groove

81‧‧‧First solder mask

82‧‧‧Second solder mask

90‧‧‧Electronic components

91‧‧‧Connecting terminal

92‧‧‧ solder ball bumps

113‧‧‧ pads

Claims (8)

A method of fabricating a multilayer circuit board, comprising the steps of: providing an insulating substrate having opposing first and second surfaces; forming at least one through hole penetrating the first surface and the second surface in the insulating substrate, and Forming a first blind trench pattern exposed only on the first surface and a second blind trench pattern exposed only on the second surface; depositing a conductive material on the insulating substrate by a plating technique to fill the conductive material in the at least one pass Forming at least one conductive hole in the hole, filling a first line pattern in the first blind groove pattern, and filling a second line pattern in the second blind groove pattern, the first line pattern being embedded in the insulating substrate and Flush with the first surface, the second line pattern is embedded in the insulating substrate and flush with the second surface, the first circuit pattern has an assembly area and a nip area surrounding the connection assembly area, the assembly area Include a plurality of pads, the first line pattern being electrically connected to the second line pattern through the at least one conductive hole; forming a first press-bonded substrate on the first surface of the insulating substrate to obtain a multi-layer substrate, the first press-bonding substrate includes a first conductive circuit layer and a first film, the first film is pressed between the first conductive circuit layer and the first surface, the first conductive circuit layer and the first a line pattern electrical connection; removing the first press-fit substrate corresponding to the assembly area, thereby forming an exposed groove in the multilayer substrate, the assembly area is exposed in the groove; and having a plurality of connection terminals The electronic component is electrically connected to the plurality of pads of the first line pattern, and each of the connection terminals is electrically connected to one of the pads by a solder ball bump. The method for fabricating a multi-layer circuit board according to claim 1, wherein after forming an exposed groove in the multilayer substrate, further comprising the step of mounting an electronic component in the recess, the electronic component It is electrically connected to the assembly area of the first line pattern. The method for fabricating a multilayer circuit board according to claim 2, wherein after depositing the conductive material on the insulating substrate by a plating technique, the step of rubbing or etching is further removed to remove the first surface and the second surface. a conductive material on the surface such that the conductive material filled in the at least one through hole is flush with the first surface and the second surface such that the conductive material filled in the first blind groove pattern is flush with the first surface, The conductive material filled in the second blind trench pattern is made flush with the second surface. The method of fabricating a multilayer circuit board according to claim 2, wherein, after forming the first line pattern and the second line pattern, the plurality of layers are formed before the first pressing substrate is formed on the first surface of the insulating substrate The manufacturing method of the circuit board further includes the step of providing a protective film on the surface of the assembly area; and the method of manufacturing the multilayer circuit board further removes the protective film while or after removing the portion of the first pressed substrate corresponding to the assembled area A step of. The method for fabricating a multilayer circuit board according to claim 2, wherein the forming the first press-bonding substrate on the first surface of the insulating substrate comprises the steps of: providing a first copper foil and the first film; a first copper foil, a first film and an insulating substrate, and press-bonding the first copper foil, the first film and the insulating substrate at a time; forming at least one first blind via hole in the first film by drilling and plating techniques Electrically connecting the first copper foil with the first wiring pattern; and selectively etching the first copper foil by an image transfer process and a chemical etching process to form the first copper foil into the first conductive wiring layer. The manufacturing method of the multi-layer circuit board of claim 2, wherein the first pressing substrate comprises a third conductive circuit layer, a third film, a first conductive circuit layer and a first film which are sequentially laminated. The third film is pressed between the third conductive circuit layer and the first conductive circuit layer, and the first film is pressed between the first conductive circuit layer and the first surface, on the first surface of the insulating substrate Forming the first pressed substrate includes the steps of: Providing a first copper foil and the first film; sequentially stacking the first copper foil, the first film and the insulating substrate, and pressing the first copper foil, the first film and the insulating substrate at a time; The plating technique forms at least one first blind via hole in the first film to electrically connect the first copper foil and the first line pattern; selectively etching the first copper foil by an image transfer process and a chemical etching process to thereby form the first copper foil Forming the first conductive circuit layer; providing a third copper foil and the third film; pressing the third film between the third copper foil and the first conductive circuit layer; by drilling and plating techniques Forming at least one third blind via hole in the third film to electrically connect the third copper foil and the first conductive wiring layer; and selectively etching the third copper foil by an image transfer process and a chemical etching process to form the third copper foil The third conductive circuit layer. The method for fabricating a multilayer circuit board according to claim 2, wherein a first press-bonding substrate is formed on the first surface of the insulating substrate, and a second press-bonding substrate is formed on the second surface of the insulating substrate, The second pressing substrate includes a second conductive circuit layer and a second film, the second film is pressed between the second conductive circuit layer and the second surface, and the second conductive circuit layer and the second circuit pattern Electrical connection. The method of fabricating a multilayer circuit board according to claim 2, wherein a solder resist layer is formed on the surface of the first press-bonded substrate before or after the recess is formed.