CN112838078A

CN112838078A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112838078A
Application number: CN202011276663.8A
Authority: CN
Inventors: 郑心圃; 庄博尧; 陈硕懋; 许峯诚
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-11-22
Filing date: 2020-11-16
Publication date: 2021-05-25
Also published as: DE102020116106A1; DE102020116106B4

Abstract

Semiconductor devices and methods of fabricating the same are provided in which a plurality of integrated passive devices are integrated together using an integrated fan-out process to form larger devices having smaller footprints. In particular embodiments, the plurality of integrated passive devices are capacitors that, once stacked together, can be used to provide a greater total capacitance than any single passive device that can achieve a similar footprint.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present application relate to a semiconductor device and a method of manufacturing the same.

Background

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from an iterative reduction in the minimum feature size so that more components can be integrated into a given area. As the demand for shrinking electronic devices has grown, a need has arisen for smaller and more inventive semiconductor die packaging techniques. An example of such a packaging system is the package on package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology can generally produce semiconductor devices with enhanced functionality and small footprints on Printed Circuit Boards (PCBs).

Disclosure of Invention

An embodiment of the present application provides a semiconductor device including: a first Integrated Passive Device (IPD); a first molding compound encapsulating the first integrated passive device; a redistribution structure located over and electrically connected to the first integrated passive device; a second integrated passive device located on an opposite side of the redistribution structure from the first integrated passive device, wherein the second integrated passive device is electrically connected to the first integrated passive device through the redistribution structure; and a second molding compound encapsulating the second integrated passive device.

Other embodiments of the present application provide a semiconductor device, including: a first redistribution structure; a first functional die bonded to the first redistribution structure; and a first integrated passive device stack coupled to the first redistribution structure, the first integrated passive device stack comprising: a second redistribution structure; a first integrated passive device located over the second redistribution structure; a third redistribution structure located over the first integrated passive component, the third redistribution structure connected to the second redistribution structure by first vias; and a second integrated passive device located over the third redistribution structure.

Still further embodiments of the present application provide a method of manufacturing a semiconductor device, the method including: forming a first redistribution structure over the carrier wafer; forming a via over the first redistribution structure; placing a first integrated passive device on the first redistribution structure adjacent to the via; sealing the first integrated passive device and the via with an encapsulant; forming a second redistribution structure over the encapsulant in electrical connection with the via; and placing a second integrated passive device on the second redistribution structure and in electrical connection with the via.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates the formation of a redistribution structure according to some embodiments.

Fig. 2A-2C illustrate placement of a first integrated passive device according to some embodiments.

Fig. 3 illustrates encapsulation of a first integrated passive device according to some embodiments.

Fig. 4 illustrates the formation of another redistribution structure according to some embodiments.

Fig. 5A-5B illustrate the formation of an integrated passive device stack, according to some embodiments.

Fig. 6 illustrates an arrangement of an integrated passive device stack on another redistribution structure according to some embodiments.

Figure 7 illustrates the connection of a redistribution structure to a substrate according to some embodiments.

Fig. 8 illustrates an integrated passive device stack using a face-to-back configuration according to some embodiments.

Fig. 9A-9C illustrate a multi-connection via according to some embodiments.

Fig. 10A-10B illustrate a three layer integrated passive device stack according to some embodiments.

Fig. 11 illustrates a five-layer integrated passive device stack according to some embodiments.

Fig. 12 illustrates a top view of an integrated passive device stack, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1-5B illustrate cross-sectional views of intermediate steps during a process of forming a first Integrated Passive Device (IPD) stack 500 (not fully shown in fig. 1, but shown in fig. 5A), according to some embodiments. A first package region 100A is shown that may be adjacent to a second package region (not separately shown) and one or more first IPD die 50A are packaged to form an integrated circuit package in each of the package regions (e.g., first package region 100A and second package region). Integrated circuit packages may also be referred to as integrated fan out (InFO) packages.

In fig. 1, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer such that multiple packages may be formed on the carrier substrate 102 at the same time.

The release layer 104 may be formed of a polymer-based material that may be removed with the carrier substrate 102 from the overlying structures (e.g., the backside redistribution structures 106) formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based thermal release material, such as a light-to-heat conversion (LTHC) release coating, that loses its adhesion upon heating. In other embodiments, the release layer 104 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer 104 may be dispensed in liquid form and cured, may be a laminated film laminated on the carrier substrate 102, or may be similar. The top surface of the release layer 104 may be flush and may have a high degree of coplanarity.

Fig. 1 also shows that a backside redistribution structure 106 may be formed on the release layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108, one or more metallization patterns 110 (sometimes referred to as redistribution layers or redistribution lines), and one or more dielectric layers 112. The backside redistribution structure 106 is optional. In some embodiments, instead of the backside redistribution structure 106, a dielectric layer without metallization patterns is formed on the release layer 104.

A dielectric layer 108 may be formed on the release layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In other embodiments, the dielectric layer 108 is formed of a nitride, such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; or the like. The dielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, CVD, lamination, or the like, or combinations thereof.

A metallization pattern 110 may be formed on the dielectric layer 108. As an example of forming the metallization pattern 110, a seed layer is formed over the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, Physical Vapor Deposition (PVD) or the like. Thereafter, a photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating (such as electroplating or electroless plating). The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Thereafter, the photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etch process (such as wet or dry etching). The remaining portions of the seed layer and the conductive material form a metallization pattern 110.

A dielectric layer 112 may be formed on the metallization pattern 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., that may be patterned using a photolithographic mask. In other embodiments, the dielectric layer 112 is formed of a nitride, such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 112 is then patterned to form openings that expose portions of the metallization pattern 110. The pattern may be formed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material or by etching using, for example, anisotropic etching. If dielectric layer 112 is a photosensitive material, dielectric layer 124 can be developed after exposure.

It should be understood that the backside redistribution structure 106 may include any number of dielectric layers and metallization patterns, such as one or more layers of dielectric layers and metallization patterns. The above steps and processes may be repeated if more dielectric layers and metallization patterns are to be formed. The metallization pattern may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming a seed layer and a conductive material of the metallization pattern in openings of the underlying dielectric layer. Thus, the conductive vias may interconnect and electrically couple the various wires.

In fig. 2A, a first via 116 is formed in the opening and extends away from the topmost dielectric layer (e.g., dielectric layer 112) of the backside redistribution structure 106. As an example of forming the first vias 116, a seed layer (not shown) is formed over the backside redistribution structure 106, e.g., on the dielectric layer 112 and on portions of the metallization pattern 110 exposed by the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive via. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Portions of the photoresist and seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping (such as using an oxygen plasma) process. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etch process (such as by wet or dry etching). The remaining portion of the seed layer and the conductive material form a first via 116.

Fig. 2A also shows one or more or two or more IPD die 50 adhered to dielectric layer 112 by adhesive 221 using, for example, a pick and place process. A desired type and number of IPD die 50 are adhered in each of the package regions (e.g., first package region 100A). In the illustrated embodiment, a plurality of IPD die 50 are adhered adjacent to each other, including a first IPD die 50A and a second IPD die 50B. The first and second IPD die 50A and 50B may be dies that include passive components, such as deep trench capacitors (with, e.g., MOM or MIM capacitors), multilayer ceramic capacitors (MLCCs), coil inductors, thin film resistors, microstrip lines, impedance matching elements, counterbalances, combinations of these, and so forth.

Fig. 2B-2C show close-up views of the first IPD die 50A, while fig. 2C shows a close-up view of the dashed box 201 in fig. 2B. As can be seen in fig. 2C, in embodiments where the first IPD die 50A is a deep trench capacitor die, the first IPD die 50A may include a second substrate 203 and openings 205 filled with multiple layers of conductive material 207 alternating with layers of dielectric material 209. The first IPD die 50A may include a plurality of deep trench capacitors interconnected in a parallel arrangement, and each deep trench capacitor includes two openings 205 filled with conductive material 207 and dielectric material 209. The second substrate 203 may comprise an active layer of doped or undoped bulk silicon, or a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

An opening 205 is formed in the second substrate 203 to accommodate a deep trench capacitor formed using conductive material 207 and dielectric material 209. In an embodiment, the opening 205 may be formed using one or more photolithographic masking and etching processes, such as using a photomask, and then by an anisotropic etching process to remove portions of the second substrate 203. However, any suitable process may be utilized.

Once the openings 205 have been formed, the liner 211 may be deposited lining the openings 205, followed by a series of alternating layers of conductive material 207 and dielectric material 209. In an embodiment, the liner 211 may be a dielectric material, such as silicon oxide, the conductive material 207 may be a conductive material, such as titanium nitride, and the dielectric material 209 may be one or more layers of a high-k dielectric material (such as zirconium oxide, aluminum oxide, hafnium oxide, combinations of these, and the like). Each layer may be deposited using a deposition process (such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, and the like) until four layers of conductive material 207 and four layers of dielectric material 209 are present. However, any suitable materials, processes, and number of alternating layers may be utilized.

Once the conductive material 207 and the dielectric material 209 have been formed, these layers may be patterned (e.g., by one or more photolithographic masking and etching processes), a contact etch stop layer may be deposited, and contacts 213 to the overlying metallization layer 215 may be formed. In embodiments where the contacts 213 and overlying metallization layer 215 may be formed using a damascene or dual damascene process, such as by first depositing a dielectric layer (not separately shown), the dielectric layer is patterned to expose the underlying conductive material, overfill the openings with another conductive material, and planarize the conductive material to form the contacts 213 and metallization layer 215. However, any suitable method may be utilized to form the contacts 213 and the metallization layer 215.

Returning now to fig. 2B, once the desired number of metallization layers 215 have been formed, external die contacts 217 may be formed to provide external connections to the internally formed capacitors. In an embodiment, the external die contacts 217 may be conductive pillars, such as copper pillars, and may comprise one or more conductive materials, such as copper, tungsten, other conductive metals, and the like, and may be formed by electroplating, electroless plating, and the like, for example, using a seed layer and a photoresist that is placed and patterned. In an embodiment, an electroplating process is used in which the seed layer and photoresist are immersed or dipped into an electroplating solution, such as one containing copper sulfate (CuSO)₄) The solution of (1). The seed layer surface is electrically connected to the negative side of an external DC power source, such that the seed layer acts as a cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolving into solution, the cathode (e.g. seed crystal)Layer) to take dissolved atoms therefrom, thereby plating exposed conductive regions of the seed layer within the openings of the photoresist. Once formed, the photoresist may be removed and the underlying exposed seed layer may be removed.

In another embodiment, the external die contacts 217 may be contact bumps, such as micro-bumps or controlled collapse chip connection (C4) bumps, and may comprise a material such as tin, or other suitable material such as silver or copper. In embodiments where the external die contacts 217 are contact bumps, the external die contacts 217 may comprise a material such as tin, or other suitable material such as silver, lead-free tin, or copper. In embodiments where the external die contacts 217 are tin solder bumps, the external die contacts 217 may be formed by first forming a layer of tin to a thickness of, for example, about 100 μm using such common methods (such as evaporation, plating, printing, solder transfer, ball placement, etc.). Once the tin layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape.

Once the outer die contacts 217 have been formed, a passivation layer 219 may be formed over the outer die contacts 217. In an embodiment, the passivation layer 219 may be Polybenzoxazole (PBO), but any suitable material may be utilized, such as polyimide or a polyimide derivative. The passivation layer 219 may be placed to a thickness between about 5 μm and about 25 μm, such as about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may be used. Once in place, the passivation layer 219 may be planarized with the external die contacts 217 using, for example, a chemical mechanical polishing process.

In addition, although the process of forming the external die contacts 217 and then surrounded by the passivation layer 219 has been described, this sequence is merely exemplary and not limiting. Also, any suitable sequence of process steps may be utilized, such as first depositing a passivation layer 219, patterning the passivation layer 219 to form openings for the external die contacts 217, and then forming the external die contacts 217 within the openings. Any suitable process for forming the external die contacts 217 and the passivation layer 219 may be utilized and all such processes are fully intended to be included within the scope of the embodiments.

In some embodiments, first IPD die 50A and second IPD die 50B can be formed in the process of the same technology node, or can be formed in the process of different technology nodes. For example, first IPD die 50A may have a higher level process node than second IPD die 50B. First IPD die 50A and 50B may have different dimensions (e.g., different heights and/or surface areas), or may have the same dimensions (e.g., the same heights and/or surface areas).

Returning to fig. 2A, adhesive 221 is placed on the backside of first IPD die 50A and 50B, and first IPD die 50A and 50B are adhered to backside redistribution structure 106, such as to dielectric layer 112. The adhesive may be any suitable adhesive, epoxy, Die Attach Film (DAF), or the like. An adhesive may be applied to the backside of the first IPD die 50A and the backside of 50B, or may be applied over the surface of the carrier substrate 102. For example, adhesive may be applied to the backside of first IPD die 50A and the backside of 50B before singulation to connect first IPD die 50A and 50B.

In fig. 3, an encapsulant 120 is formed over and around the various components to form a first bottom layer 301 of a first IPD stack 500. After formation, encapsulant 120 encapsulates first via 116 and first IPD die 50A and 50B. The encapsulant 120 may be a molding compound, an epoxy, or the like. Encapsulant 120 may be applied by compression molding, transfer molding, etc., and may be formed over carrier substrate 102 such that first via 116 and/or first IPD die 50A and 50B are buried or covered. Encapsulant 120 is further formed in the gap regions between IPD die 50. The encapsulant 120 may be applied in liquid or semi-liquid form and then cured.

Fig. 3 also shows that a planarization process is performed on the encapsulant 120 to expose the first via 116 and the external die contact 217. The planarization process may also remove material of the first via 116, the passivation layer 219, and/or the external die contact 217 until the external die contact 217 and the first via 116 are exposed. After the planarization process, the top surface of the first via 116, the top surface of the external die contact 217, the top surface of the passivation layer 219, and the top surface of the encapsulant 120 are coplanar. The planarization process may be, for example, Chemical Mechanical Polishing (CMP), an abrasive process, or the like. In some embodiments, planarization may be omitted, for example, if the first via 116 and/or the external die contact 217 have been exposed.

Once formed, the first bottom layer 301 may have dimensions that help to reduce the overall footprint of the first IPD stack 500, while still obtaining an increase in a desired parameter (such as capacitance). For example, a first one of the first IPD die 50A may have a first height H between about 40 μm and about 500 μm₁Such as about 90 μm, and a second one of IPD die 50B may have a height H that may be equal to or equal to first height H₁Different second height H₂Such as a second height H₂Between about 40 μm and about 500 μm, such as about 90 μm. Similarly, first IPD die 50A may have a first width W between about 0.1mm and about 20mm₁Such as about 5mm, and a second one of IPD die 50B may have a width W that may be equal to or equal to first width W₁Different second width W₂Such as the second width W₂Between about 0.1mm and about 20mm, such as about 5 mm. However, any suitable size may be utilized.

Similarly, the encapsulant 120 may have a height H greater than the first height H₁And a second height H₂Third height H of₃Such as between about 50 μm and about 700 μm, such as about 100 μm. The backside redistribution structure 106 may have a height H less than the third height H₃Fourth height H of₄Such as a fourth height H₄Between about 10 μm and about 150 μm, such as about 40 μm. However, any suitable height may be used for the encapsulant 120 and the backside redistribution structure 106.

Finally, a first one of the first IPD die 50A may be spaced apart from an edge of encapsulant 120. In an embodiment, a first one of the first IPD die 50A may be spaced apart by less than the first width W₁Third width W of₃Such as the third width W₃Between about 50 μm and about 2000 μm, such as about 500 μm. However, any suitable size may be utilized.

In fig. 4, a front side redistribution structure 122 is formed over encapsulant 120, over first via 116, and over first IPD die 50A and 50B, and is electrically connected to first via 116 and external die contacts 217. The front side redistribution structure 122 includes

dielectric layers

124, 128, and 132; and

metallization patterns

126, 130, and 134. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The front-side redistribution structure 122 is shown as an example with three metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 122. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

In an embodiment, a dielectric layer 124 is deposited over the encapsulant 120, over the first vias 116, and over the external die contacts 217. In some embodiments, the dielectric layer 124 is formed of a photosensitive material such as PBO, polyimide, BCB, and the like, which can be patterned using a photolithographic mask. The dielectric layer 124 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. Then, the dielectric layer 124 is patterned. The patterning forms an opening that exposes a portion of the first via 116 and a portion of the external die contact 217. Patterning may be performed by acceptable processes, such as by exposing the dielectric layer 124 to light when the dielectric layer 124 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 124 is a photosensitive material, the dielectric layer 124 can be developed after exposure.

A metallization pattern 126 is then formed. Metallization pattern 126 includes line portions (also referred to as conductive lines) that are located on and extend along a major surface of dielectric layer 124. Metallization pattern 126 also includes via portions (also referred to as conductive vias) that extend through dielectric layer 124 to physically and electrically couple first via 116 and IPD die 50. As an example of forming metallization pattern 126, a seed layer is formed over dielectric layer 124 and in an opening extending through dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. Openings are patterned through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the underlying portions of the seed layer form a metallization pattern 126. Portions of the photoresist and seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etch process (such as by wet or dry etching).

A dielectric layer 128 is deposited over metallization pattern 126 and over dielectric layer 124. Dielectric layer 128 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124. Once formed, the dielectric layer 128 may be patterned using, for example, a photolithographic masking and etching process to expose underlying portions of the metallization pattern 126. However, any suitable methods and materials may be utilized.

A metallization pattern 130 is then formed. Metallization pattern 130 includes line portions that are located on and extend along a major surface of dielectric layer 128. Metallization pattern 130 also includes via portions that extend through dielectric layer 128 to physically and electrically couple metallization pattern 126. Metallization pattern 130 may be formed in a similar manner and of a similar material as metallization pattern 126. In some embodiments, metallization pattern 130 has a different size than metallization pattern 126. For example, the conductive lines and/or vias of metallization pattern 130 may be wider or thicker than the conductive lines and/or vias of metallization pattern 126. In addition, the metallization patterns 130 may be formed at a larger pitch than the metallization patterns 126.

A dielectric layer 132 is deposited over the metallization pattern 130 and over the dielectric layer 128. Dielectric layer 132 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124. Once formed, the dielectric layer 132 may be patterned using, for example, a photolithographic masking and etching process to expose portions of the underlying metallization pattern 130. However, any suitable methods and materials may be utilized.

A metallization pattern 134 is then formed. In the embodiment shown, metallization pattern 134 includes only via portions that extend through dielectric layer 132 to physically and electrically couple metallization pattern 130, although other embodiments may utilize line portions in addition to via portions. Metallization pattern 134 may be formed in a similar manner and of a similar material as metallization pattern 126. However, any suitable method, such as a damascene process or a dual damascene process, and any suitable material may be utilized.

Metallization pattern 134 is the topmost metallization pattern of front-side redistribution structure 122. As such, all intermediate metallization patterns (e.g., metallization patterns 126 and 130) of front-side redistribution structure 122 are disposed between metallization pattern 134 and first IPD die 50A and 50B. In some embodiments, metallization pattern 134 has a different size than

metallization patterns

126 and 130. For example, the conductive lines and/or vias of metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of

metallization patterns

126 and 130. In addition, the metallization pattern 134 may be formed at a larger pitch than the metallization pattern 130.

Fig. 5A shows the placement of second IPD die 50C and 50D. In an embodiment, second IPD die 50C and 50D may be similar to first IPD die 50A and 50B, and are designed for use with first IPD die 50A and 50B to provide more powerful functions than is possible in such a small footprint. For example, in embodiments where the first IPD die 50A and 50B and the second IPD die 50C and 50D are capacitor dies (such as deep trench capacitor dies), the combination of the first IPD die 50A and 50B and the second IPD die 50C and 50D provides greater capacitance in a smaller footprint than can be achieved with a single layer device.

In an embodiment, the second IPD die 50C and 50D can be similar to the first IPD die 50A and 50B, such as by having a third substrate 503 (similar to the second substrate 203), a second external die contact 505 (similar to the first external die contact 217), and a second passivation layer 511 (similar to the passivation layer 219) with deep trench capacitors formed thereon and thereon. However, any suitable structure may be utilized.

In an embodiment, second IPD die 50C and 50D can be placed in contact with metallization pattern 134 using, for example, a pick and place process, to bring second external die contacts 505 into physical contact with metallization pattern 134. Once in physical contact, second IPD die 50C and 50D can be connected to metallization pattern 134 using any suitable bonding process (such as fusion bonding, hybrid bonding, metal-to-metal bonding, combinations of these, and the like). However, any suitable bonding process may be utilized.

Fig. 5A also shows the formation of encapsulant 136 over and around second IPD die 50C and 50D to form first top layer 501 of first IPD stack 500. After formation, encapsulant 136 encapsulates second IPD die 50C and 50D. The encapsulant 136 may be a molding compound, epoxy, or the like. Encapsulant 136 may be applied by compression molding, transfer molding, etc., and may be formed over carrier substrate 102 such that second IPD die 50C and 50D are buried or covered. Encapsulant 136 is also formed in the gap region between second IPD die 50C and 50D. The encapsulant 136 may be applied in liquid or semi-liquid form and then cured.

In an embodiment, second IPD die 50C may have a fifth height H between about 40 μm and about 500 μm₅Such as about 90 μm. Second IPD die 50D may have a height H that may be equal to fifth height H₅Same, greater or less than the fifth height H₅A sixth height H₆Such as a sixth height H₆Between about 40 μm and about 500 μm, such as about 90 μm. However, any suitable height may be utilized.

In addition, the sealant 136 may be formed to have a height H greater than the fifth height H₅And a sixth height H₆A seventh height H of the two₇. For example, the sealant 136 may be formed to have a structure ofA seventh height H between about 50 μm and about 700 μm₇Such as about 100 μm. However, any suitable height may be utilized.

Finally, a first one of the second IPD die 50C may be spaced apart from the edge of encapsulant 136. In an embodiment, a first one of the second IPD die 50C may be larger, smaller or equal to the third width W₃A fourth width W (within the first substrate 301)₄Spaced apart, such as a fourth width W₄Between about 50 μm and about 2000 μm, such as about 500 μm. At a fourth width W₄Is greater than the third width W₃In embodiments, the structure may better balance the warpage of the entire structure. However, in the fourth width W₄Is greater than the third width W₃In embodiments of (1), the second IPD die 50C may be larger, resulting in a higher total capacitance. However, any suitable size may be utilized.

Fig. 5A additionally illustrates peeling of the carrier substrate to separate (or "peel off") the carrier substrate 102 from the backside redistribution structure 106 (e.g., the dielectric layer 108). According to some embodiments, the peeling includes projecting light (such as laser or UV light) onto the release layer 104 such that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 may be removed. The structure is then inverted and placed on a belt.

Conductive connections 152 are formed to extend through the dielectric layer 108 to contact the metallization pattern 110. In an embodiment, the conductive connection 152 may be placed by first forming an opening through the dielectric layer 108 to expose a portion of the metallization pattern 110. The openings may be formed, for example, using laser drilling, etching, and the like. The conductive connections 152 may be contact bumps, such as micro-bumps or controlled collapse chip connection (C4) bumps, and may comprise a material such as tin, or other suitable materials such as silver or copper. In embodiments where the conductive connections 152 are contact bumps, the conductive connections 152 may comprise a material such as tin, or other suitable materials such as silver, lead-free tin, or copper. In embodiments where the conductive connections 152 are tin solder bumps, the conductive connections 152 may be formed by initially forming a layer of tin to a thickness of, for example, about 100 μm using such common methods (such as evaporation, plating, printing, solder transfer, ball placement, etc.). Once the tin layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape.

In other embodiments, the conductive connections 152 may be conductive pillars, such as copper pillars, and may comprise one or more conductive materials, such as copper, tungsten, other conductive metals, and the like, and may be formed by electroplating, electroless plating, and the like, for example, using a seed layer and a photoresist that is placed and patterned. In an embodiment, an electroplating process is used in which the seed layer and photoresist are immersed or dipped into an electroplating solution (such as one containing copper sulfate (CuSO)₄) Solution of (b). The seed layer surface is electrically connected to the negative side of an external DC power source, such that the seed layer acts as a cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve into the solution, from which the cathode (e.g., seed layer) picks up the dissolved atoms, plating the exposed conductive regions of the seed layer within the openings of the photoresist. Once formed, the photoresist may be removed and the underlying exposed seed layer may be removed.

Additionally, the conductive connections 152 may be arranged in an array of rows and columns along the bottom of the dielectric layer 108. Furthermore, each row may include only ground connections, while adjacent rows may include only power connections. Thus, there is a parallel connection of ground and power connections along the bottom of the dielectric layer 108. However, any suitable arrangement may be utilized.

Once the second IPD die 50C and 50D are encapsulated, a singulation process is performed by sawing along scribe areas, for example, between the first package area 100A and other package areas to form the first IPD stack 500. The resulting singulated first IPD stack 500 comes from the first package area 100A. However, any suitable singulation process may be utilized.

Fig. 5B shows an equivalent circuit representing an equivalent capacitance that can be obtained by the first IPD stack 500. In this embodiment, the capacitance (C) available from the first bottom layer 301_a) Dashed box 507 (where each capacitance of each capacitor is labeled C₁、C₂Etc.) are shown, andcapacitance (C) available from the first top layer 501_b) Dashed box 509 (where each capacitance of each capacitor is labeled C₁、C₂Etc.). It can be seen that by stacking and interconnecting the capacitors in each of the IPD dies (e.g., first IPD dies 50A and 50B and second IPD dies 50C and 50D), the IPD dies can be interconnected in a parallel arrangement. Thus, the total capacitance (C) of the first IPD stack 500_T) May be a capacitance (C) available from the first underlayer 301_a) And capacitance (C) available from the first top layer 501_b) Sum of (e.g. C)_T＝C_a+C_b). In this way, a greater capacitance can be achieved without increasing the total footprint.

Fig. 6 illustrates the placement of the first IPD stack 500 over the third redistribution structure 138. In an embodiment, the third redistribution structure 138 may be formed similar to the backside redistribution structure 106. For example, the third redistribution structure 138 may be formed on a carrier substrate (not separately shown), and then one or more sides of the third redistribution structure 138 may be exposed to provide locations for further bonding. However, the third redistribution structure 138 may be formed using any suitable processes and materials.

Once the third redistribution structure 138 has been formed, the first IPD stack 500 may be attached to the third redistribution structure 138. In an embodiment, the first IPD stack 500 may be placed in contact with the third redistribution structure 138 using, for example, a pick and place process. Once in physical contact, the first IPD stack 500 can be bonded to the third redistribution structure 138 using any suitable bonding process (such as a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, combinations of these, and the like).

Fig. 6 also shows, in addition to the first IPD stack 500, a first functional die 60A and a second functional die 60B that are also bonded to the third redistribution structure 138. In an embodiment, the first functional die 60A may be a logic device, such as a system on a chip (SoC), a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a microcontroller, or the like. The second functional die 60B may be a memory device such as a High Bandwidth Memory (HBM) module, a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Hybrid Memory Cube (HMC) module, or the like. In some embodiments, the first functional die 60A may be an SoC die, while the second functional die 60B may be a high bandwidth memory. The first functional die 60A and the second functional die 60B may be formed in the same technology node process or may be formed in different technology node processes. For example, the first functional die 60A may have a higher level process node than the second functional die 60B. The first functional die 60A and the second functional die 60B may have different dimensions (e.g., different heights and/or surface areas) or may have the same dimensions (e.g., the same heights and/or surface areas).

In an embodiment, the first and second functional dies 60A, 60B may be brought into contact with the third redistribution structure 138 using, for example, a pick and place process to place external contacts (similar to the conductive connectors 152 in some embodiments) in physical contact with conductive portions of the third redistribution structure 138. Once in physical contact, the first and second functional dies 60A, 60B may be bonded to the third redistribution structure 138 using any suitable bonding process (e.g., reflow process, fusion bonding process, hybrid bonding process, metal-to-metal bonding process, combinations of these, etc.).

In some embodiments, an underfill 144 is formed between the third redistribution structure 138 and the first functional die 60A, between the third redistribution structure 138 and the second functional die 60B, and between the third redistribution structure 138 and the first IPD stack 500. The underfill 144 may reduce stress and protect the joint due to reflow of the conductive connection 152. The underfill 144 may be formed by a capillary flow process after attaching the first functional die 60A, the second functional die 60B, and the first IPD stack 500, or may be formed by a suitable deposition method before attaching the first functional die 60A, the second functional die 60B, and the first IPD stack 500.

Fig. 6 also shows that an encapsulant 146 is formed over and around the first functional die 60A, the second functional die 60B, and the first IPD stack 500 to form a first package structure 601. In an embodiment, the encapsulant 146 may be a molding compound, an epoxy, or the like. The encapsulant 146 may be applied by compression molding, transfer molding, or the like, and may be formed around the first functional die 60A, the second functional die 60B, and the first IPD stack 500 such that the first IPD stack 500, the first functional die 60A, and the second functional die 60B are buried or covered. Encapsulant 146 is also formed in the gap region between first IPD stack 500, first functional die 60A and second functional die 60B. The encapsulant 146 may be applied in liquid or semi-liquid form and then cured.

Fig. 6 also shows that the planarization process is performed on the sealant 120. The planarization process may also remove material of the first IPD stack 500, the first functional die 60A and the second functional die 60B. After the planarization process, the top surface of the first IPD stack 500, the top surface of the first functional die 60A, the top surface of the second functional die 60B and the top surface of the encapsulant 146 are coplanar. The planarization process may be, for example, Chemical Mechanical Polishing (CMP), an abrasive process, or the like. In some embodiments, planarization may be omitted.

Once the encapsulant 146 has been placed, a second conductive connection 603 may be placed or formed on the side of the third redistribution structure 138 opposite the first IPD stack 500. In an embodiment, the second conductive connection 603 may be similar to the conductive connection 152, such as by being a conductive ball (such as a solder ball or a conductive post). However, any suitable materials and methods may be utilized.

Fig. 7 shows that once the first IPD stack 500, the first functional die 60A and the second functional die 60B have been encapsulated, a first package structure 601 may be attached to the substrate 150. In an embodiment, the substrate 150 may include an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin, such as FR 4. In other embodiments, the core material comprises bismaleimide-triazine (BT) resin, other Printed Circuit Board (PCB) material, or a film. Build-up films, such as Ajinomoto build-up film (ABF), or other laminates may also be used for substrate 150.

The substrate 150 may include active and passive devices (not shown). A variety of devices (such as transistors, capacitors, resistors, combinations of these, and the like) may be used to generate the structural and functional requirements of the design. The device may be formed using any suitable method.

The substrate 150 may also include metallization layers and conductive vias 208 on either side of the insulating core. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) (vias with interconnecting conductive material layers), and may be formed by any suitable process, such as deposition, damascene, dual damascene, and the like. In other embodiments, the substrate 150 is substantially free of active and passive devices.

The substrate 150 may have bond pads 204 on a first side of the substrate 150 and bond pads 206 on a second side of the substrate 150, opposite the first side of the substrate 150, to couple to a second conductive connection 603. In some embodiments,

bond pads

204 and 206 are formed by forming recesses (not shown) in a dielectric layer (not shown) on the first side and on the second side of substrate 150. Recesses may be formed to allow the

bond pads

204 and 206 to be embedded in the dielectric layer. In other embodiments, the recess is omitted because the

bond pads

204 and 206 may be formed on a dielectric layer. In some embodiments,

bond pads

204 and 206 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or combinations thereof. The conductive material of

bond pads

204 and 206 may be deposited over a thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, Atomic Layer Deposition (ALD), PVD, the like, or combinations thereof. In an embodiment, the conductive material of the

bond pads

204 and 206 is copper, tungsten, aluminum, silver, gold, or the like, or combinations thereof.

In an embodiment, bond pad 204 and bond pad 206 are UBMs that include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers (such as a chromium/chromium-copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement) may be used for the formation of

bond pads

204 and 206. Any suitable material or layer of material that may be used for

bond pads

204 and 206 is fully intended to be included within the scope of the present application.

In some embodiments, an underfill 154 is formed between the first package structure 601 and the substrate 150. The underfill 154 may reduce stress and protect a joint due to reflow of the second conductive connection 603. The underfill 154 may be formed by a capillary flow process after attaching the structure, or may be formed by a suitable deposition method before attaching the structure.

In some embodiments, the second conductive connectors 603 are reflowed to attach the first package structure 601 to the bond pads 206. The second conductive connection 603 electrically and/or physically couples the structure comprising the metallization layer 208 located in the substrate 150 to the first package structure 601. In some embodiments, the solder resist is formed on the substrate core 302. The first package structure 601 may be disposed in an opening in the solder resist to electrically and mechanically couple to the bond pad 206. The solder resist may be used to protect areas of the substrate 150 from external damage.

By utilizing the first IPD stack 500, increased capacitance can be attached to the entire structure to work with the first functional die 60A and the second functional die 60B. In addition, this can be achieved without requiring a larger footprint, which can negatively impact the overall size of the device. Finally, by selecting the number and size of the individual IPD die, accurate capacitance can be obtained without the need to completely redesign the entire structure.

Fig. 8 illustrates another embodiment in which first IPD die 50A and 50B and second IPD die 50C and 50D are connected in a face-to-back configuration, rather than in a face-to-face configuration as illustrated above with respect to fig. 2A-7. In particular, in this embodiment, the first IPD die 50A and 50B are not attached to the backside redistribution structure 106 using adhesive, but are physically and electrically bonded to the backside redistribution structure 106 prior to applying the encapsulant 120.

In a particular embodiment, the first IPD die 50A and 50B are bonded to the back-side redistribution structure 106 using external die contacts 217 and a process similar to that used to bond the second IPD die 50C and 50D to the front-side redistribution structure 122, as described above with respect to fig. 5A. For example, a pick and place process may be utilized to make physical and electrical contact between the first IPD die 50A and 50B and the backside redistribution structure 106. Once in physical contact, the first IPD die 50A and 50B are then bonded using, for example, a hybrid bonding process, a dielectric bonding process, or any other suitable bonding process. However, any suitable bonding process or other attachment process may be utilized.

Once the first IPD die 50A and 50B are bonded, the process may continue as described above with respect to fig. 3-8. For example, encapsulant 120 may be applied and thinned to expose first vias 116 (although encapsulant 120 may remain over first IPD die 50A and 50B because no electrical connection is to be made on that side), front-side redistribution structure 122 may be formed in electrical connection with first vias 116, second IPD die 50C and 50D will be bonded to front-side redistribution structure 122, and encapsulant 136 may be applied to encapsulate second IPD die 50C and 50D to form first IPD stack 500. In addition, the first IPD stack 500 may be placed over the third redistribution structure 138 along with the first functional die 60A and the second functional die 60B, the encapsulant 146 may be applied, and the structure may be connected to the substrate 150.

Fig. 9A-9C illustrate another embodiment in which the first IPD stack 500 is formed with second external connections 156, in addition to the first vias 116, to connect the back-side redistribution structures 106 and the front-side redistribution structures 122. In this embodiment, as shown in fig. 9A, the backside redistribution structure 106 is formed as described above with respect to fig. 1. For example, a dielectric layer 108 is formed over the carrier substrate 102 (not separately shown in fig. 9A), and one or more metallization patterns 110 are formed over the dielectric layer 108 to form the backside redistribution structure 106.

Once the back side redistribution structure 106 has been formed, first vias 116 may be formed that are electrically connected with the back side redistribution structure 106. In an embodiment, the backside redistribution structure 106 may be formed as described above with respect to fig. 2A. For example, a seed layer is formed, a photoresist is placed and patterned over the seed layer, the material of the first via 116 is plated into the opening of the photoresist, the photoresist is removed, and the uncovered portion of the seed layer is removed. However, the first via 116 may be formed using any suitable method and material.

In this embodiment, however, the first vias 116 are not intended to be the only connection between the back-side redistribution structure 106 and the front-side redistribution structure 122. In this way, first via 116 need not be as tall as first IPD die 50A and 50B, and is formed to have a smaller height than first IPD die 50A and 50B. For example, in this embodiment, the first via 116 may be formed to have a first thickness T between about 10 μm and about 650 μm₁Such as about 50 μm. However, any suitable thickness may be utilized.

Fig. 9B illustrates the formation of a front-side redistribution structure 122. In this embodiment, however, instead of forming the front-side redistribution structures 122 on the encapsulant 120, the front-side redistribution structures 122 are separated from the back-side redistribution structures 106, such as by being formed on a second carrier wafer (not separately shown) similar to the carrier substrate 102. For example, a dielectric layer 124 would be formed over the second carrier wafer and release layer 104, and one or more metallization patterns 126 are formed over the dielectric layer 124.

Fig. 9B additionally shows that once front-side redistribution structure 122 is formed, second IPD die 50C and 50D are bonded to front-side redistribution structure 122. In an embodiment, second IPD die 50C and 50D are bonded as described above with respect to fig. 5A. For example, second IPD die 50C and 50D are placed by a pick and place process, and second IPD die 50C and 50D are bonded using, for example, a hybrid bonding process. However, any suitable method of bonding second IPD die 50C and 50D may be utilized.

Further, once the second IPD die 50C and 50D are bonded to the front-side redistribution structure 122, the second IPD die 50C and 50D are encapsulated with an encapsulant 136. In an embodiment, the sealant 136 may be applied as described above with respect to fig. 5A. However, any suitable seal may be used.

Finally, fig. 9B illustrates the placement of a second external connection 156 in electrical connection with the front side redistribution structure 122, where the second external connection 156 is used in conjunction with the first via 116 to connect the back side redistribution structure 106 with the front side redistribution structure 122. In an embodiment, the placement of the second external connections 156 may be initiated by first removing the second carrier wafer and the adhesion layer to expose the dielectric layer 124 of the front side redistribution structure 122. In an embodiment, although the second carrier wafer is removed as described above with respect to the first carrier wafer, any suitable removal process may be utilized.

Once the dielectric layer 124 has been exposed, the dielectric layer 124 may be patterned to expose portions of one or more metallization patterns 126. In an embodiment, the dielectric layer 124 may be patterned using, for example, a laser drilling method. In this approach, a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax (protective) layer (not separately shown in fig. 9B), is first deposited over the dielectric layer 124. Once protected, the laser is directed to those portions of the dielectric layer 124 where removal is desired. During the laser drilling process, the drilling energy may range from 0.1mJ to about 30mJ, and the drilling angle is about 0 degrees to about 85 degrees relative to a normal to the dielectric layer 124. However, any suitable method may be utilized, such as a photolithographic masking and etching process.

Once the dielectric layer 124 has been patterned, a second external connection 156 is placed through the dielectric layer 124 and electrically connected with the front side redistribution structure 122. The second external connections 156 may be contact bumps, such as micro bumps or controlled collapse chip connection (C4) bumps, and may comprise a material such as tin or other suitable material, such as silver or copper. In embodiments where the second external connections 156 are tin solder bumps, the second external connections 156 may be formed by first forming a layer of tin by any suitable method (such as evaporation, plating, printing, solder transfer, ball placement, etc.) to a thickness of, for example, about 100 μm. Once the tin layer is formed on the structure, reflow is performed to shape the material into the desired bump shape.

Fig. 9C illustrates the bonding of the second external connection 156 to the first via 116, thereby electrically connecting the back-side redistribution structure 106 and the front-side redistribution structure 122. In an embodiment, once the second external connection member 156 has been formed, the second external connection member 156 is aligned with the first through hole 116 and placed in physical contact with the first through hole 116, and engagement is effected. For example, in embodiments where the second external connection member 156 is a solder bump, the bonding process may include a reflow process whereby the temperature of the second external connection member 156 is raised to a point where the second external connection member 156 will liquefy and flow, thereby bonding the second external connection member 156 to the first through hole 116 once the second external connection member 156 is re-solidified. However, any suitable bonding process may be utilized.

Fig. 9C also shows that once the second external connection 156 is bonded to the first via 116, an encapsulant 120 may be placed around the second external connection 156, the first via 116, and the first IPD die 50A and 50B to provide additional support between the back-side redistribution structure 106 and the front-side redistribution structure 122. In an embodiment, the encapsulant 120 may be placed as described above with respect to fig. 3. For example, the encapsulant 120 may be applied by compression molding, transfer molding, or the like. However, any suitable method of applying the encapsulant 120 between the back side redistribution structure 106 and the front side redistribution structure 122 may be utilized.

In another embodiment, the encapsulant 120 may be an underfill material. In this embodiment, the sealant 120 may be formed through a capillary flow process after the second external connection member 156 has been bonded to the first through hole 116. However, any suitable methods and materials may be utilized.

Once the first IPD stack 500 has been formed in this embodiment, the process may continue as described above with respect to fig. 6-8. For example, the first IPD stack 500 may be placed together with the first functional die 60A and the second functional die 60B onto the third redistribution structure 138, the encapsulant 146 may be applied, and the structure may be connected to the substrate 150. However, any suitable method may be utilized to connect the first IPD stack 500 to other structures.

Fig. 10A shows yet another embodiment where the first IPD stack 500 is formed with more layers than just the first bottom layer 301 and the first top layer 501. In the embodiment shown in fig. 10A, the first bottom layer 301 is formed as described above with respect to fig. 1-8 (although the embodiment shown is in a face-to-back configuration, any of the disclosed configurations may be utilized).

Once the first bottom layer 301 is formed, the first intermediate layer 303 is formed over the first bottom layer 301 prior to the formation of the first top layer 501. In an embodiment, the first intermediate layer 303 includes a fourth redistribution layer 305, a second via 307, third IPD die 50E and 50F and a third encapsulant 309. In an embodiment, the fourth redistribution layer 305 is formed using methods and materials similar to the front-side redistribution structure 122 described above with respect to fig. 4. For example, a series of dielectric layers and metallization layers are alternately deposited to establish the fourth redistribution layer 305. However, any suitable methods and materials may be utilized.

Once the fourth redistribution layer 305 is formed, a second via 307 is formed in electrical connection with the fourth redistribution layer 305. In an embodiment, the second via 307 may be formed using similar methods and materials as the first via 116 described above with respect to fig. 2A. For example, a seed layer is deposited over the fourth redistribution layer 305, a photoresist is placed over the seed layer and patterned, second vias 307 are formed within the pattern of photoresist, the photoresist is removed, and uncovered portions of the seed layer are removed. However, any suitable methods and materials may be utilized.

In addition, once second via 307 has been formed, third IPD die 50E and 50F can be placed adjacent to second via 307. In an embodiment, the third IPD die 50E and 50F may be similar to the first IPD die 50A and 50B (e.g., may be capacitor dies) and may be placed in physical and electrical contact with the fourth redistribution layer 305 using, for example, a pick and place process. Once in physical contact, third IPD die 50E and 50F can be bonded using, for example, a hybrid bonding process, a metal-to-metal bonding process, a dielectric bonding process, a combination of these, and the like. However, any suitable process may be utilized.

Fig. 10A also shows that once the third IPD die 50E and 50F have been bonded, a third encapsulant 309 can be placed over the third IPD die 50E and 50F and thinned to expose the second vias 307. In an embodiment, the third encapsulant 309 may be deposited using similar materials and methods as described above with respect to encapsulant 120 of fig. 3. However, any suitable methods and materials may be utilized.

Once the first middle layer 303 has been formed, a first top layer 501 may be formed over the first middle layer 303 and the conductive connectors 152 placed in connection with the first bottom layer 301. In an embodiment, the first top layer 501 may be formed as described above with respect to fig. 4-5B. For example, front side redistribution structure 122 is formed, second IPD die 50C and 50D are placed and bonded to front side redistribution structure 122, and encapsulant 136 is used to encapsulate second IPD die 50C and 50D. Similarly, the conductive connections 152 may be placed as described above with respect to fig. 5A. However, any suitable method and material may be utilized to form and/or place the first top layer 501 and the conductive connections 152.

Fig. 10B shows an equivalent circuit representing an equivalent capacitance that can be achieved with the first IPD stack 500 and the three layers. In this embodiment, the capacitance (C) available from the first bottom layer 301_a) Indicated in dashed box 507 (where the individual capacitances of the individual capacitors are labeled C₁、C₂Etc.); capacitance (C) available from the first top layer 501_b) Indicated in dashed box 509 (where the individual capacitances of the individual capacitors are labeled C₁、C₂Etc.); and a capacitance (C) obtainable from the first intermediate layer 303_c) Indicated in dashed box 1001 (where the individual capacitances of the individual capacitors are labeled C₁、C₂Etc.). It can be seen that by stacking and interconnecting the IPD dies (e.g., first IPD dies 50A and 50B; second IPD dies 50C and 50D; and third IPD dies 50E and 50F) in the first IPD stack 500, the IPD dies can be interconnected in a parallel arrangement. Thus, the total capacitance (C) of the first IPD stack 500_T) May be a capacitance (C) available from the first underlayer 301_a) (ii) a Capacitance (C) available from the first top layer 501_b) (ii) a And a capacitance (C) obtainable from the first intermediate layer 303_c) Sum of (e.g. C)_T＝C_a+C_b+C_c). In this way, a greater capacitance can be obtained without increasing the total footprint, and this can be done simplyThe number of layers within each layer or the number of IPD dies is increased or decreased to scale the capacitance as desired.

Fig. 11 illustrates yet another embodiment utilizing five layers within the first IPD stack 500. For example, in this embodiment, first bottom layer 301, first intermediate layer 303, and first top layer 501 are formed as described herein, but with only a single one of the IPD die in each layer. Also in this embodiment, a second intermediate layer 1101 and a third intermediate layer 1103 are formed, which may be similar to the first intermediate layer 303 described above with respect to fig. 10A (but with a single one of the IPD dies). However, any suitable number of layers may be utilized.

In this embodiment, the entire first IPD stack 500 with five layers may have a total height H of 670 μm_o(e.g., 100 μm per IPD die plus 30 μm per redistribution layer and molding compound on either side of four of the IPD die, and plus 100 μm redistribution layer and molding compound on either side of the first top layer 501). In addition, each of the individual IPD dies may have a width of 1.1 μ F/mm²And the IPD die has a capacitance of 32.27mm²In embodiments of the active region of (a), each of the monolayers may then have a monolayer capacitance of 35.5 muf. Thus, the total capacitance of the first IPD stack 500 in this particular embodiment is about 178 μ F. However, any suitable parameter may be utilized.

Fig. 12 shows a top-down version of one possible layout with a first package structure and a substrate 150. In the illustrated embodiment, a first IPD stack 500 is placed over substrate 150 between a first one of the second functional dies 60B and a second one of the second functional dies 60B (e.g., between two high-bandwidth memory dies). In addition, one of the first functional dies 60A (e.g., a system-on-chip die) is connected to the substrate 150 adjacent to each of the first one of the second functional dies 60B, the second one of the second functional dies 60B, and the first IPD stack 500. However, any suitable layout may be utilized.

In an embodiment, the first functional die 60A may have a first dimension D between about 10mm and about 100mm₁Such as about 33mm, and at aboutA second dimension D of between 8mm and about 95mm₂Such as about 25 mm. Similarly, each of the second functional dies 60B may have a third dimension D between about 3mm and about 20mm₃Such as about 12mm, and a fourth dimension D between about 2mm and about 20mm₄Such as about 8 mm. However, any suitable size may be utilized.

With respect to the first IPD stack 500, the first IPD stack 500 may be formed to have a size suitable for within a small footprint left by the first functional die 60A and the second functional die 60B. As such, the first IPD stack 500 may have a fifth dimension D between about 2mm and about 20mm₅Such as about 8mm, while having a sixth dimension D of between about 2mm and about 20mm₆Such as about 8 mm. However, any suitable size may be utilized.

By packaging multiple IPD dies in a package using the first IPD stack 500, larger parameters (e.g., larger capacitance) can be obtained without requiring a larger footprint. Furthermore, both the number of layers desired and the number and/or size of IPD dies desired can be used to precisely adjust the desired capacitance. In this way, any desired capacitance can be achieved without sacrificing size.

According to an embodiment, a semiconductor device includes: a first Integrated Passive Device (IPD); a first molding compound encapsulating the first IPD; a redistribution structure located over the first IPD and electrically connected to the first IPD; a second IPD located on a side of the redistribution structure opposite the first IPD, wherein the second IPD is electrically connected to the first IPD through the redistribution structure; and a second molding compound encapsulating the second IPD. In an embodiment, a face of the first IPD faces a face of the second IPD. In an embodiment, a face of the first IPD faces a back of the second IPD. In an embodiment, the semiconductor device further includes a conductive via extending through the first molding compound. In an embodiment, the semiconductor device further includes a conductive feature extending through the first molding compound, the conductive feature including: a conductive via; and a solder region on the conductive via. In an embodiment, the first IPD is electrically connected to the redistribution structure through a copper pillar. In an embodiment, the first IPD is electrically connected to the redistribution structure through a solder region.

According to another embodiment, a semiconductor device includes: a first redistribution structure; a first functional die bonded to the first redistribution structure; and a first integrated passive-device stack coupled to the first redistribution structure, the first integrated passive-device stack comprising: a second redistribution structure; a first integrated passive device located over the second redistribution structure; a third redistribution structure located on the first integrated passive device, the third redistribution structure connected to the second redistribution structure through the first via; and a second integrated passive device located over the third redistribution structure. In an embodiment, the semiconductor device further comprises: a third integrated passive device located between the second redistribution structure and the third redistribution structure; and a first encapsulant surrounding the third integrated passive device and the first integrated passive device. In an embodiment, the first via includes a copper pillar. In an embodiment, the first via comprises: a copper pillar; and solder balls in physical contact with the copper pillars. In an embodiment, the first integrated passive device and the second integrated passive device are configured in a face-to-face configuration. In an embodiment, the first integrated passive device and the second integrated passive device are configured in a back-to-face configuration. In an embodiment, the first integrated passive-device stack further comprises: a fourth redistribution structure located over the second integrated passive device, the fourth redistribution structure connected to the third redistribution structure by a second via; and a third integrated passive device located over the fourth redistribution structure.

According to still another embodiment, a method of manufacturing a semiconductor device includes: forming a first redistribution structure over the carrier wafer; forming a via over the first redistribution structure; placing a first integrated passive device on a first redistribution structure adjacent to a via; sealing the first integrated passive device and the via with an encapsulant; forming a second redistribution structure over the encapsulant in electrical connection with the via; and placing a second integrated passive device on the second redistribution structure and electrically connected with the via. In an embodiment, placing the first integrated passive device on the first redistribution structure places the first integrated passive device in electrical connection with the first redistribution structure. In an embodiment, placing the first integrated passive device on the first redistribution structure utilizes an adhesive. In an embodiment, the first integrated passive device is placed placing the integrated passive capacitor. In an embodiment, the method further includes bonding the first redistribution structure to a third redistribution layer. In an embodiment, the method further comprises: bonding the first functional die to the third redistribution layer; and encapsulating the first functional die in an encapsulant.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a first Integrated Passive Device (IPD);

a first molding compound encapsulating the first integrated passive device;

a redistribution structure located over and electrically connected to the first integrated passive device;

a second integrated passive device located on an opposite side of the redistribution structure from the first integrated passive device, wherein the second integrated passive device is electrically connected to the first integrated passive device through the redistribution structure; and

a second molding compound encapsulating the second integrated passive device.

2. The semiconductor device of claim 1, wherein a face of the first integrated passive device faces a face of the second integrated passive device.

3. The semiconductor device of claim 1, wherein a face of the first integrated passive device faces a back of the second integrated passive device.

4. The semiconductor device of claim 1, further comprising a conductive via extending through the first molding compound.

5. The semiconductor device of claim 1, further comprising a conductive feature extending through the first molding compound, wherein the conductive feature comprises:

a conductive via; and

a solder region on the conductive via.

6. The semiconductor device of claim 1, wherein the first integrated passive device is electrically connected to the redistribution structure through copper pillars.

7. The semiconductor device of claim 1, wherein the first integrated passive device is electrically connected to the redistribution structure through a solder region.

8. A semiconductor device, comprising:

a first redistribution structure;

a first functional die bonded to the first redistribution structure; and

a first integrated passive device stack bonded to the first redistribution structure, the first integrated passive device stack comprising:

a second redistribution structure;

a first integrated passive device located over the second redistribution structure;

a third redistribution structure located over the first integrated passive component, the third redistribution structure connected to the second redistribution structure by first vias; and

a second integrated passive device located over the third redistribution structure.

9. The semiconductor device of claim 8, further comprising:

a third integrated passive device located between the second redistribution structure and the third redistribution structure; and

a first encapsulant surrounding the third integrated passive device and the first integrated passive device.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a first redistribution structure over the carrier wafer;

forming a via over the first redistribution structure;

placing a first integrated passive device on the first redistribution structure adjacent to the via;

sealing the first integrated passive device and the via with an encapsulant;

forming a second redistribution structure over the encapsulant in electrical connection with the via; and

placing a second integrated passive device on the second redistribution structure and in electrical connection with the via.