DE102020116106A1 - SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS - Google Patents

Abstract

Semiconductor devices and manufacturing methods are provided in which multiple integrated passive devices are integrated together using an integrated fan-out process to manufacture a larger device with a smaller footprint. In particular embodiments, the multiple integrated passive devices are capacitors that, when stacked one on top of the other, can be used to provide greater overall capacitance than can be achieved with a single passive device of similar footprint.

Description

Priority claim and cross-reference

This application claims priority from U.S. provisional patent application filed on November 22, 2019 with file number 62 / 939 , 147, which is incorporated by reference.

background

The semiconductor industry has experienced rapid growth due to constant improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density is due to repeated reductions in the smallest feature width, which allows more components to be integrated in a given area. As the demand for miniaturization of electronic devices has become more pressing, a need for smaller and more creative packaging methods for semiconductor dies has arisen. Package-on-Package (PoP) technology is an example of such packaging systems. In a PoP device, an upper semiconductor package is stacked on a lower semiconductor package in order to achieve a high degree of integration and a high component density. PoP technology enables semiconductor devices with improved functionality and small footprints to be fabricated on a printed circuit board (PCB).

Figure list

• 1 zeigt die Herstellung einer Umverteilungsstruktur gemäß einigen Ausführungsformen.
• Die 2A bis 2C zeigen ein Platzieren einer ersten integrierten passiven Vorrichtung gemäß einigen Ausführungsformen.
• 3 zeigt ein Verkapseln der ersten integrierten passiven Vorrichtung gemäß einigen Ausführungsformen.
• 4 zeigt ein Herstellen einer weiteren Umverteilungsstruktur gemäß einigen Ausführungsformen.
• Die 5A und 5B zeigen ein Herstellen eines Stapels von integrierten passiven Vorrichtungen gemäß einigen Ausführungsformen.
• 6 zeigt ein Platzieren des Stapels von integrierten passiven Vorrichtungen auf einer weiteren Umverteilungsstruktur gemäß einigen Ausführungsformen.
• 7 zeigt eine Verbindung der Umverteilungsstruktur mit einem Substrat gemäß einigen Ausführungsformen.
• 8 zeigt den Stapel von integrierten passiven Vorrichtungen, für den eine Vorderseite-an-Rückseite-Konfiguration verwendet wird, gemäß einigen Ausführungsformen.
• Die 9A bis 9C zeigen eine Durchkontaktierung mit mehreren Verbindungen gemäß einigen Ausführungsformen.
• Die 10A und 10B zeigen einen dreischichtigen Stapel von integrierten passiven Vorrichtungen gemäß einigen Ausführungsformen.
• 11 zeigt einen fünfschichtigen Stapel von integrierten passiven Vorrichtungen gemäß einigen Ausführungsformen.
• 12 zeigt eine Top-Down-Ansicht des Stapels von integrierten passiven Vorrichtungen gemäß einigen Ausführungsformen.

Aspects of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be enlarged or reduced as desired.

• 1 Figure 12 shows the manufacture of a redistribution structure in accordance with some embodiments.
• The 2A to 2C FIG. 11 depicts placement of a first integrated passive device in accordance with some embodiments.
• 3rd FIG. 10 shows encapsulation of the first integrated passive device in accordance with some embodiments.
• 4th FIG. 10 shows manufacturing of another redistribution structure in accordance with some embodiments.
• The 5A and 5B FIG. 12 depicts fabricating a stack of integrated passive devices in accordance with some embodiments.
• 6th Figure 12 shows placing the stack of integrated passive devices on another redistribution structure in accordance with some embodiments.
• 7th Figure 12 shows a connection of the redistribution structure to a substrate in accordance with some embodiments.
• 8th Figure 12 shows the stack of integrated passive devices using a front-to-back configuration, in accordance with some embodiments.
• The 9A to 9C illustrate a via with multiple connections in accordance with some embodiments.
• The 10A and 10B show a three-layer stack of integrated passive devices in accordance with some embodiments.
• 11 Figure 11 shows a five-layer stack of integrated passive devices in accordance with some embodiments.
• 12th Figure 12 shows a top-down view of the stack of integrated passive devices in accordance with some embodiments.

Detailed description

The description below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below in order to simplify the present invention. These are of course only examples and are not intended to be limiting. For example, the manufacture of a first element over or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and it can also include embodiments in which additional elements are placed between the first and the second element can be made so that the first and second elements are not in direct contact. In addition, in the present invention, reference numbers and / or letters may be repeated in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself write any relationship between the various embodiments and / or configurations discussed.

In addition, spatially relative terms such as "below", "below", "lower" / "lower", "above", "upper" / "upper" and the like can be used for simplicity Description of the relationship of an element or structure to one or more other elements or structures shown in the figures. The spatially relative terms are intended to include other orientations of the device in use or in operation in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative descriptors used herein can also be interpreted accordingly.

The 1 to 5 Figure 12 shows cross-sectional views of intermediate stages during a process of making a first stack of Integrated Passive Devices (IPD stacks) 500 (the in 1 is not shown in full, but in 5A is shown) according to some embodiments. A first package area is shown 100A , which may be adjacent to a second package area (not shown individually), and in each of the package areas (ie, in the first package area 100A and the second package area) one or more first IPD dies 50A capped to form an integrated circuit package. The integrated circuit packages can also be referred to as integrated fan-out (InFO) packages.

In 1 becomes a carrier substrate 102 provided, and on the carrier substrate 102 becomes a release layer 104 produced. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate or the like. The carrier substrate 102 can be a wafer, so that several packages are simultaneously on the carrier substrate 102 can be produced.

The release layer 104 can be made from a polymer-based material that coexists with the support substrate 102 of structures above (e.g. a rear redistribution structure 106 ) that will be made in later steps can be removed. In some embodiments, the release liner is 104 an epoxy-based heat-releasable material that loses its adhesion when heated, such as an LTHC (light-to-heat conversion) release liner. In other embodiments, the release layer 104 an ultraviolet (UV) adhesive that loses its adhesion when exposed to UV light. The release layer 104 can be distributed as a liquid and cured, or it can be a laminate layer with which the carrier substrate 102 is coated, or the like. A top of the release liner 104 can be leveled and can have a high degree of planarity.

1 also shows that a rearward redistribution structure 106 on the release liner 104 can be produced. In the embodiment shown, the rear-side redistribution structure 106 a dielectric layer 108 , one or more metallization structures 110 (sometimes referred to as redistribution layers or redistribution lines) and one or more dielectric layers 112 on. The rear redistribution structure 106 is optional. In some embodiments, instead of the rear redistribution structure 106 a dielectric layer with no metallization structures on the release layer 104 produced.

On the release layer 104 can be the dielectric layer 108 getting produced. An underside of the dielectric layer 108 can be in contact with the top of the release liner 104 be. In some embodiments, the dielectric layer is 108 made of a polymer such as polybenzoxazole (PBO), polyimide, BCB, or the like. In other embodiments, the dielectric layer is 108 a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 108 can be made by any suitable deposition method such as spin coating, CVD, lamination, or the like, or a combination thereof.

On the dielectric layer 108 can the metallization structure 110 getting produced. For example, the metallization structure 110 be made by first placing a seed layer over the dielectric layer 108 will be produced. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be produced, for example, by physical vapor deposition (PVD) or the like. A photoresist is then produced on the seed layer, which is then structured. The photoresist can be prepared by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the metallization structure 110 . The patterning creates openings through the photoresist in order to expose the seed layer. In the Openings in the photoresist and a conductive material is deposited on the exposed parts of the seed layer. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. Then the photoresist and the parts of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed by a suitable stripping or stripping process, for example using an oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching. The remaining parts of the seed layer and the conductive material form the metallization structure 110 .

On the metallization structure 110 and the dielectric layer 108 can be the dielectric layer 112 getting produced. In some embodiments, the dielectric layer is 112 made of a polymer which can be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithographic mask. In other embodiments, the dielectric layer is 112 a nitride such as silicon nitride; an oxide such as silica, PSG, BSG, or BPSG; or the like. The dielectric layer 112 can be made by spin coating, CVD, lamination, or the like, or a combination thereof. The dielectric layer 112 is then patterned to create openings which are parts of the metallization structure 110 uncover. The patterning can be carried out using a suitable method, such as by exposing the dielectric layer to light 112 when the dielectric layer 112 is a photosensitive material, or by etching, for example by anisotropic etching. When the dielectric layer 112 is a photosensitive material, it can be developed after exposure.

It should be understood that the rearward redistribution structure 106 may include any number of dielectric layers and metallization structures, such as one or more dielectric layers and metallization structures. If more dielectric layers and metallization structures are to be fabricated, the steps and processes discussed above can be repeated. The metallization structures can include conductive lines and conductive vias. The conductive vias can be produced during the production of the metallization structure in that the seed layer and the conductive material of the metallization structure are deposited in an opening of the dielectric layer located below. The conductive vias can electrically connect the various conductive lines to one another.

In 2A become conductive vias in the openings 116 made to stand out from the top dielectric layer of the rear redistribution structure 106 (e.g. the dielectric layer 112 ) extend away. As an example of making the first vias 116 becomes a seed layer (not shown) over the rear redistribution structure 106 manufactured, e.g. B. on the dielectric layer 112 and on parts of the metallization structure 110 exposed by the openings. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be made, for example, by PVD or the like. A photoresist is then produced on the seed layer, which is then structured. The photoresist can be prepared by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the conductive vias 116 . The patterning creates openings through the photoresist in order to expose the seed layer. A conductive material is deposited in the openings of the photoresist and on the exposed parts of the seed layer. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. Then the photoresist and the parts of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed by a suitable stripping or stripping process, for example using an oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching. The remaining parts of the seed layer and the conductive material form the first vias 116 .

2A also shows that one, two or more IPD dies 50 with an adhesive 221 z. B. with a pick-and-place process to the dielectric layer 112 be glued on. In each of the package areas (e.g. in the first package area 100A) will be IPD dies 50 of a desired type and in a desired amount. In the In the illustrated embodiment, multiple IPD dies 50 who have favourited a First IPD Die 50A and a second IPD die 50B embrace, glued side by side. The first IPD die 50A and the second IPD die 50B These can be those that have passive components, such as deep trench capacitors (e.g. with MOM or MIM capacitors), multilayer ceramic capacitors (MLCCs), induction coils, film resistors, microstrip lines, impedance matching elements, baluns, combinations thereof or the like .

The 2 B and 2C show close-up views of the first IPD die 50A , in which 2C a close-up view of a dashed box 201 of 2 B shows. As in 2C can be seen, in an embodiment in which the first IPD Die 50A is a deep trench capacitor, the first IPD die 50A a second substrate 203 and openings 205 having multiple layers of a conductive material 207 alternating with layers of a dielectric material 209 are filled. The first IPD die 50A may have more than one deep trench capacitor connected in parallel, with each deep trench capacitor having two openings 205 having that with the conductive material 207 and the dielectric material 209 are filled. The second substrate 203 may be bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. In general, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates, such as multilayer substrates, gradient substrates, or hybrid orientation substrates, can also be used.

After the openings 205 have been generated, a coating 211 deposited around the openings 205 line, and then several alternating layers of the conductive material are made 207 and the dielectric material 209 deposited. In one embodiment, the covering 211 a dielectric material such as silicon oxide, the conductive material 207 may be a conductive material such as titanium hydride, and the dielectric material 209 may comprise one or more layers of high-k dielectric materials, such as zirconia, alumina, or hafnium oxide, a combination thereof, or the like. The layers can each be deposited using a deposition method such as CVD, PVD, ALD, a combination thereof, or the like, up to four layers of the conductive material 207 and four layers of the dielectric material 209 have been deposited. However, any suitable materials, methods, and numbers of alternating layers can be used.

After the layers of the conductive material 207 and the layers of dielectric material 209 have been made, the layers can e.g. B. be patterned with one or more photolithographic masking and etching processes, a contact etch stop layer can be deposited, and contacts 213 with overlying metallization layers 215 can be made. In one embodiment, the contacts 213 and the overlying metallization layers 215 be produced with a single or dual damascene process as follows: depositing a dielectric layer (not shown individually); Patterning the dielectric layer to expose the conductive material underneath; Overfilling the openings with another conductive material; and planarizing the conductive material around the contacts 213 and the metallization layers 215 to manufacture. However, any suitable method for making the contacts can be used 213 and the metallization layers 215 be used.

Let's come back to 2 B back. After the desired number of metallization layers 215 has been established, the external contacts can 217 to make external connections with the internally manufactured capacitors. In one embodiment, the die external contacts 217 conductive pillars, such as copper pillars, and can comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and they can be made, for example, by electroplating, electroless plating, or the like with a seed layer and a placed and patterned photoresist getting produced. In one embodiment, an electroplating process is used in which the seed layer and photoresist are immersed in an electroplating bath, such as a solution _{containing copper sulfate (CuSO 4} ). The surface of the seed layer is electrically connected to the negative side of an external DC power source so that the seed layer functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the bath and attached to the passive side of the power source. The atoms from the anode are released into the bath and the cathode, e.g. B. the seed layer, picks up the released atoms, thereby plating the exposed conductive areas of the seed layer in the opening of the photoresist. After making the external contacts 217 For example, the photoresist can be removed and the exposed seed layer underneath can also be removed.

In a further embodiment, the die external contacts 217 Contact bumps, such as microbumps or C ₄ contact bumps (C ₄ : Controlled Collapse Chip Bonding), and can comprise a material such as tin or other suitable materials such as silver or copper. In one embodiment in which the die external contacts 217 Contact bumps are, the die-external contacts can 217 comprise a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In one embodiment in which the die external contacts 217 Are solder bumps, the die-external contacts 217 be made by first forming a layer of tin with such commonly used methods as vapor deposition, electroplating, printing, solder transfer, ball placement, etc. to a thickness of e.g. B. is made about 100 microns. After the layer of tin has been produced on the structure, a reflow process can be performed to bring the material into the desired bump shapes.

After the die-external contacts 217 have been produced, a passivation layer 219 over the external contacts 217 getting produced. In one embodiment, the passivation layer 219 Polybenzoxazole (PBO), but any suitable material such as a polyimide or a polyimide derivative can be used. The passivation layer 219 can e.g. B. with a spin coating process with a thickness of about 5 microns to about 25 microns, e.g. About 7 microns, but any suitable method and thickness can be used. Then the passivation layer 219 with the external contacts 217 z. B. be planarized with a CMP process.

Although a process has been described in which the die-external contacts 217 and then from the passivation layer 219 but this order is intended to be illustrative and not restrictive. Rather, any suitable sequence of process steps can be used, such as initially depositing the passivation layer 219 Structuring the passivation layer 219 to create openings for the external contacts of the die 217 and then making the die external contacts 217 in the openings. Any suitable method for producing the die external contacts can be used 217 and the passivation layer 219 can be used, and all of these methods are intended to be entirely within the scope of the embodiments.

In some embodiments, the first IPD die 50A and the second IPD die 50B are produced in processes with the same technology node or in processes with different technology nodes. For example, the first IPD Die 50A a die of a more modern process node than the second IPD die 50B be. The first IPD dies 50A and 50B can have different sizes (e.g. different heights and / or areas), or they can be the same sizes (e.g. the same heights and / or areas).

We come to 2A back. The adhesive 221 is on the back of the first IPD dies 50A and 50B places and sticks the first IPD dies 50A and 50B to the rear redistribution structure 106 such as the dielectric layer 112 . The adhesive 221 can be any suitable adhesive, epoxy, die attach layer (DAF), or the like. The adhesive can be applied to the backs of the first IPD dies 50A and 50B or over the surface of the carrier substrate 102 be applied. For example, the adhesive can be on the backs of the first IPD dies 50A and 50B applied before the first IPD dies 50A and 50B be isolated.

In 3rd becomes an encapsulation material 120 on and around the various components made to form a first lower layer 301 of the first batch of IPDs 500 to manufacture. After its manufacture, the encapsulation material encapsulates 120 the first vias 116 and the first IPD dies 50A and 50B . The encapsulation material 120 can be a molding compound, an epoxy or the like. The encapsulation material 120 can be applied by compression molding, compression molding or the like and can thus be applied over the carrier substrate 102 be applied that the first vias 116 and / or the first IPD dies 50A and 50B buried or covered. The encapsulation material 120 is also used in gap areas between the IPD dies 50 upset. The encapsulation material 120 can be applied in a liquid or semi-liquid form and then cured.

3rd also shows a planarization process on the encapsulation material 120 is performed to the first vias 116 and the external contacts 217 to expose. With the planarization process, material of the first vias 116 , the passivation layer 219 and / or the die-external contacts 217 be removed until the die-external contacts 217 and the first vias 116 are exposed. After the planarization process, there are tops of the first vias 116 , the die-external contacts 217 , the passivation layer 219 and the encapsulation material 120 coplanar. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In some embodiments, the planarization can be omitted, for example when the first vias 116 and / or the die external contacts 217 already exposed.

After its manufacture, the first lower layer can be used 301 Have dimensions that reduce the total footprint of the first IPD stack 500 contribute while still achieving an increase in a desired parameter such as capacity. For example, a first one of the first IPD dies 50A a first height H ₁ of about 40 µm to about 500 µm, e.g. B. of about 90 microns, while a second the IPD dies 50B may have a second height H ₂ , which may be the same as _{or different from the first height H 1} , the second height H _{2 being} about 40 μm to about 500 μm, e.g. B. about 90 microns. Likewise, the first of the first IPD dies 50A a first width W ₁ of about 0.1 mm to about 20 mm, e.g. B. of about 5 mm, while the second of the IPD dies 50B may have a second width W ₂ which may be the same as _{or different from the first width W 1} , the second width W _{2 from} about 0.1 mm to about 20 mm, e.g. B. about 5 mm. However, any suitable dimensions can be used.

The encapsulation material can likewise 120 have a third height H ₃ that is greater than the first height H ₁ and the second height H ₂ and about 50 µm to about 700 µm, e.g. B. about 100 microns. The rear redistribution structure 106 may have a fourth height H ₄ that is less than the third height H ₃ and, for example, about 10 µm to about 150 µm, e.g. B. about 40 microns. However, any suitable heights for the encapsulation material can be used 120 and the rear redistribution structure 106 be used.

Finally, the first of the first IPD may be dies 50A from an edge of the encapsulation material 120 be spaced. In one embodiment, the first of the first IPD dies 50A be spaced with a third width W ₃ which is smaller than the first width W ₁ and about 50 µm to about 2000 µm, e.g. B. about 500 microns. However, any suitable dimensions can be used.

In 4th becomes a front-end redistribution structure 122 over the encapsulation material 120 , the first vias 116 and the first IPD dies 50A and 50B and in electrical communication with the first vias 116 and the external contacts 217 produced. The front-end redistribution structure 122 includes dielectric layers 124 , 128 and 132 and metallization structures 126 , 130 and 134 . The metallization structures can also be referred to as redistribution layers or redistribution lines. The front-end redistribution structure 122 is shown as an example with three layers of metallization structures. In the front redistribution structure 122 more or less dielectric layers and metallization structures and dielectric layers can be produced. If fewer dielectric layers and metallization structures are to be produced, the steps and processes described below can be omitted. If more dielectric layers and metallization structures are to be fabricated, the steps and processes described below can be repeated.

In one embodiment, the dielectric layer is 124 on the encapsulation material 120 , the first vias 116 and the external contacts 217 deposited. In some embodiments, the dielectric layer is 124 made of a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithographic mask. The dielectric layer 124 can be made by spin coating, lamination, CVD, or the like, or a combination thereof. Then the dielectric layer 124 structured. The structuring creates openings, which are parts of the first vias 116 and the external contacts 217 uncover. The structuring can be carried out using a suitable method, such as for example by exposing the dielectric layer to light 124 if it is a photosensitive material, or by etching, for example, anisotropic etching. When the dielectric layer 124 is a photosensitive material, it can be developed after exposure.

Then the metallization structure 126 produced. The metallization structure 126 includes line portions (also referred to as conductive lines) on and along the major surface of the dielectric layer 124 . The metallization structure 126 further includes via portions (also referred to as conductive vias) extending through the dielectric layer 124 extend to the first vias 116 and the external contacts 217 physically and electrically connect. For example, the metallization structure 126 be made by having a seed layer over the dielectric layer 124 and made in the openings extending through the dielectric layer 124 extend. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be made, for example, by PVD or the like. A photoresist is then produced on the seed layer, which is then structured. The photoresist can be prepared by spin coating or the like and can be used for patterning be exposed. The structure of the photoresist corresponds to the metallization structure 126 . The patterning creates openings through the photoresist in order to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed parts of the seed layer. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and parts of the seed layer underneath it forms the metallization structure 126 . Then the photoresist and the parts of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed by a suitable stripping or stripping process, for example using an oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching.

On the metallization structure 126 and the dielectric layer 124 becomes the dielectric layer 128 deposited. The dielectric layer 128 may be made in a similar manner and material as the dielectric layer 124 getting produced. After its production, the dielectric layer 128 can be structured to form parts of the metallization structure underneath 126 z. B. to expose with a photolithographic masking and etching process. However, any suitable method and material can be used.

Then the metallization structure 130 produced. The metallization structure 130 includes lead portions on and along the major surface of the dielectric layer 128 . The metallization structure 130 further includes via portions extending through the dielectric layer 128 extend to the metallization structure 126 physically and electrically connect. The metallization structure 130 can be made in a similar manner and material as the metallization structure 126 getting produced. In some embodiments, the metallization structure has 130 a different size than the metallization structure 126 . For example, the conductive lines and / or vias of the metallization structure 130 wider or thicker than the conductive lines and / or vias of the metallization structure 126 be. In addition, the metallization structure 130 with a greater distance than the metallization structure 126 getting produced.

On the metallization structure 130 and the dielectric layer 128 becomes the dielectric layer 132 deposited. The dielectric layer 132 may be made in a similar manner and material as the dielectric layer 124 getting produced. After its production, the dielectric layer 132 can be structured to form parts of the metallization structure underneath 130 z. B. to expose with a photolithographic masking and etching process. However, any suitable method and material can be used.

Then the metallization structure 134 produced. In the illustrated embodiment, the metallization structure comprises 134 only via parts that extend through the dielectric layer 132 extend to the metallization structure 130 physically and electrically, but in other embodiments lead parts can be used in addition to the via parts. The metallization structure 134 can be made in a similar manner and material as the metallization structure 126 getting produced. However, all suitable methods, such as single and dual damascene processes, and all suitable materials can be used.

The metallization structure 134 is the top metallization structure of the front redistribution structure 122 . All intermediate metallization structures are therefore located in the front-side redistribution structure 122 (e.g. the metallization structures 126 and 130 ) between the metallization structure 134 and the first IPD dies 50A and 50B . In some embodiments, the metallization structure has 134 a different size than the metallization structures 126 and 130 . For example, the conductive lines and / or vias of the metallization structure 134 wider or thicker than the conductive lines and / or vias of the metallization structures 126 and 130 be. In addition, the metallization structure 134 with a greater distance than the metallization structure 130 getting produced.

5A shows placement of second IPD dies 50C and 50D . In one embodiment, the second IPD can die 50C and 50D the first IPD dies 50A and 50B be similar, and they are designed to work in conjunction with the initial IPD dies 50A and 50B work to provide more robust functionality than would otherwise be possible on such a small footprint. For example, in embodiments where the initial IPD dies 50A and 50B and the second IPD dies 50C and 50D Capacitor dies, such as deeper trench capacitor dies, are the combination of the first IPD dies 50A and 50B and the second IPD dies 50C and 50D so as to provide greater capacitance in a smaller footprint than is possible with a single layer of devices.

In one embodiment, the second IPD can die 50C and 50D the first IPD dies 50A and 50B be similar in that they are, for example, a third substrate 503 (that of the second substrate 203 is similar) with deep trench capacitors manufactured in and on it, second die external contacts 505 (the first die-outside contacts 217 are similar) and a second passivation layer 511 (that of the passivation layer 219 is similar). However, any suitable structure can be used.

In one embodiment, the second IPD can die 50C and 50D z. B. with a pick-and-place process in contact with the metallization structure 134 be brought to the second die-external contacts 505 in physical contact with the metallization structure 134 bring to. Then the second IPD dies 50C and 50D with a suitable bonding method, such as melt bonding, hybrid bonding or metal-to-metal bonding, a combination thereof or the like, with the metallization structure 134 get connected. However, any suitable bonding method can be used.

5A also shows that an encapsulation material 136 on and around the second IPD dies 50C and 50D is made to be a first top layer 501 of the first batch of IPDs 500 to manufacture. After its manufacture, the encapsulation material encapsulates 136 the second IPD dies 50C and 50D . The encapsulation material 136 can be a molding compound, an epoxy or the like. The encapsulation material 136 can be applied by compression molding, compression molding or the like and can thus be applied over the carrier substrate 102 be applied that the second IPD dies 50C and 50D buried or covered. The encapsulation material 136 is also used in gap areas between the second IPD dies 50C and 50D upset. The encapsulation material 136 can be applied in a liquid or semi-liquid form and then cured.

In some embodiments, the second IPD die 50C a fifth height H ₅ of about 40 µm to about 500 µm, e.g. B. about 90 microns. The second IPD die 50D may have a sixth height H ₆ , which may be equal to or greater than or less than the fifth height H ₅ and about 40 µm to about 500 µm, e.g. B. 90 microns, can be. However, any suitable heights can be used.

In addition, the encapsulation material 136 can be made with a seventh height H ₇ , which can be greater than the fifth height H ₅ and the sixth height H ₆ . For example, the encapsulation material 136 be made so that the seventh height H ₇ about 50 microns about 700 microns, z. B. about 100 microns. However, any suitable heights can be used.

Finally, the first of the second IPD dies 50C from an edge of the encapsulation material 136 be spaced. In one embodiment, the first of the second IPD dies 50C be spaced with a fourth width W ₄ that is greater than or less than or equal to the third width W ₃ (in the first lower layer 301 ) and about 50 µm to about 2000 µm, e.g. B. about 500 microns. In embodiments in which the fourth width W _{4 is} greater than the third width W ₃ , the structure can better compensate for deformations in the entire structure. However, in embodiments where the fourth width W _{4 is} greater than the third width W ₃ , the second IPD dies 50C be larger, resulting in a higher total capacity. However, any suitable dimensions can be used.

5A also shows a carrier substrate detachment for detaching the carrier substrate 102 from the rear redistribution structure 106 , e.g. B. the dielectric layer 108 . In some embodiments, the stripping includes projecting light, such as laser light or UV light, onto the release liner 104 so that the release layer 104 decomposed by the heat of light and the carrier substrate 102 can be removed. Then the structure is turned over and placed on a belt.

Conductive fasteners 152 are manufactured in such a way that they penetrate the dielectric layer 108 extend to the metallization structure 110 to contact. In one embodiment, the conductive connection elements 152 are placed by first opening openings through the dielectric layer 108 are generated to parts of the metallization structure 110 to expose. The openings can be produced, for example, by laser drilling, etching or the like. The conductive connecting elements 152 can be bumps such as microbumps or C ₄ bumps, and they can comprise a material such as tin or other suitable materials such as silver or copper. In one embodiment in which the conductive connecting elements 152 Contact bumps are, the conductive connecting elements 152 comprise a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In one embodiment in which the conductive connecting elements 152 Solder bumps can be conductive Fasteners 152 be made by first forming a layer of tin with such commonly used methods as vapor deposition, electroplating, printing, solder transfer, ball placement, etc. to a thickness of e.g. B. is made about 100 microns. After the layer of tin has been produced on the structure, a reflow process can be performed to bring the material into the desired bump shapes.

In other embodiments, the conductive connection elements 152 conductive pillars, such as copper pillars, and they can comprise one or more conductive materials, such as copper, tungsten, other conductive materials, or the like, and can be, for example, by electroplating, electroless plating, or the like with a seed layer and a placed and patterned Photoresist can be produced. In one embodiment, an electroplating process is used in which the seed layer and photoresist are immersed in an electroplating bath, such as a solution _{containing copper sulfate (CuSO 4} ). The surface of the seed layer is electrically connected to the negative side of an external DC power source so that the seed layer functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the bath and attached to the passive side of the power source. The atoms from the anode are released into the bath and the cathode, e.g. B. the seed layer, picks up the released atoms, thereby plating the exposed conductive areas of the seed layer in the opening of the photoresist. After the conductive connection elements have been made 152 For example, the photoresist can be removed and the exposed seed layer underneath can also be removed.

In addition, the conductive connecting elements 152 in a matrix of rows and columns along a bottom of the dielectric layer 108 to be ordered. Furthermore, a single row can only include ground connections, while adjacent rows can only include power connections. Hence there are parallel lines with earth connections and power connections along the bottom of the dielectric layer 108 . However, any suitable arrangement can be used.

After the second IPD dies 50C and 50D have been encapsulated, a dicing process is carried out by sawing along scribed trench areas, e.g. B. between the first package area 100A and other package areas, carried out to the first IPD stack 500 to manufacture. The resulting isolated first IPD stack 500 comes from the first package area 100A . However, any singulation process can be used.

5B Figure 12 shows an equivalent circuit representing the equivalent capacitance obtained with the first IPD stack 500 can be achieved. In this embodiment, a capacitance (C _a ) used by the first lower layer 301 can be obtained in a dashed box 507 shown (where the individual capacitances of the individual capacitors _{are labeled C 1} , C ₂ , ...), while a capacitance (C _b ), which is from the first upper layer 501 can be obtained in a dashed box 509 is shown (whereby the individual capacitances of the individual capacitors _{are labeled C 1} , C ₂ , ...). As can be seen, the capacitors in each of the IPD dies (e.g. the first IPD dies 50A and 50B and the second IPD dies 50C and 50D) stacked on top of each other and connected to each other, the IPD dies are connected in parallel with each other. Therefore, the total capacity (C _T ) for the first IPD stack can be 500 the sum of the capacitance (C _a ) by the first lower layer 301 can be obtained and the capacitance (C _b ) that of the first upper layer 501 can be obtained (ie, C _T = C _a + C _b ). Therefore, a larger capacity can be obtained without increasing the total footprint.

6th shows a placement of the first IPD stack 500 on a third redistribution structure 138 . In one embodiment, the third redistribution structure 138 similar to the rear redistribution structure 106 getting produced. For example, the third redistribution structure 138 on a carrier substrate (not shown individually), and then one or more sides of the third redistribution structure 138 are exposed to provide sites for further bonding. However, any suitable methods and materials for producing the third redistribution structure can be used 138 come into use.

After the third redistribution structure 138 has been established, the first IPD stack can 500 on the third redistribution structure 138 attached. In one embodiment, the first IPD stack can 500 z. B. with a pick-and-place process in contact with the third redistribution structure 138 to be brought. After making contact, the first IPD stack 500 with a suitable bonding method, such as melting, fusion bonding, hybrid bonding or metal-to-metal bonding, a combination thereof or the like, to the third redistribution structure 138 be bonded.

6th still shows that except for the first IPD stack 500 also a first functional die 60A and a second functional die 60B to the third redistribution structure 138 be bonded. In one embodiment, the first functional die 60A be a logic device like for example a system-on-a-chip (SoC), a main processor (CPU), a graphics processor (GPU), a microcontroller or the like. The second functional die 60B may be a storage device such as an HBM module (HBM: high bandwidth memory), a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory), an HMC module (HMC: hybrid memory cube ) or similar. In some embodiments, the first functional die 60A one SoC die, and the second functional die 60B can be high bandwidth storage. The first functional die 60A and the second functional die 60B can be produced in processes of the same technology node or in processes with different technology nodes. For example, the first functional Die 60A one die of a more modern process node than the second functional die 60B be. The first functional die 60A and the second functional die 60B can have different sizes (e.g. different heights and / or areas), or they can have the same size (e.g. same heights and / or same areas).

In one embodiment, the first functional die 60A and the second functional die 60B z. B. with a pick-and-place process in contact with the third redistribution structure 138 are brought, whereby external connections (which in some embodiments the conductive connecting elements 152 are similar) in physical contact with conductive parts of the third redistribution structure 138 to be brought. After making contact, the first functional die 60A and the second functional die 60B with a suitable bonding method, such as melting, fusion bonding, hybrid bonding or metal-metal bonding, a combination thereof or the like, with the third metallization structure 138 get connected.

In some embodiments, an underfill 144 between the third redistribution structure 138 and the first functional die 60A , between the third redistribution structure 138 and the second functional die 60B and between the third redistribution structure 138 and the first IPD batch 500 getting produced. The underfill 144 can reduce mechanical tension and protect connection points caused by the melting of the conductive connection elements 152 arise. The underfill 144 can be made with a capillary flow process after the first functional die 60A , the second functional die 60B and the first IPD batch 500 have been attached, or they can be fabricated with a suitable deposition process prior to the first functional die 60A , the second functional die 60B and the first IPD batch 500 attached.

6th also shows that an encapsulation material 146 on and around the first functional die 60A , the second functional die 60B and the first batch of IPDs 500 is applied to a first capped structure 601 to manufacture. The encapsulation material 146 can be applied by compression molding, transfer molding or the like and can thus be applied around the first functional die 60A , the second functional die 60B and the first batch of IPDs 500 applied so that they are buried or covered. The encapsulation material 146 will also be in gap areas between the first IPD stack 500 , the first functional die 60A and the second functional die 60B upset. The encapsulation material 146 can be applied in a liquid or semi-liquid form and then cured.

6th further shows that a planarization process on the encapsulation material 146 is carried out. Material from the first IPD stack can also be used with the planarization process 500 , the first functional dies 60A and the second functional die 60B removed. After the planarization process, there are tops of the first IPD stack 500 , the first functional dies 60A , the second functional die 60B and the encapsulation material 146 coplanar. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In some embodiments, the planarization can be omitted.

After the encapsulation material 146 has been placed, second conductive connecting elements can 603 on one of the first IPD stack 500 opposite side of the third redistribution structure 138 placed or manufactured. In one embodiment, the second conductive connection elements 603 the conductive connecting elements 152 be similar in that they are conductive balls, such as solder balls, or conductive pillars. However, any suitable materials and methods can be used.

7th shows that after encapsulating the first IPD stack 500 , the first functional dies 60A and the second functional die 60B the first masked structure 601 on a substrate 150 can be attached. In one embodiment, the substrate 150 an insulating core such as a glass fiber reinforced resin core. An exemplary core material is fiberglass resin such as FR4. In other embodiments, the core material is a bismaleimide triazine (BT) resin or other printed circuit board (PCB) material or layer. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate 150 be used.

The substrate 150 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors or resistors, combinations thereof, or the like, can be used to meet the structural and functional requirements of the design.

The substrate 150 can metallization layers and conductive vias 208 on both sides of the insulating core. The metallization structures can be fabricated over the active and passive devices and can be designed to interconnect the various devices into functional circuits. The metallization layers can be made from alternating layers of dielectric material (e.g. a low-k dielectric material) and conductive material (e.g. copper), with vias connecting the layers of conductive material together, and the metallization layers can with any suitable method (e.g. deposition, single or dual damascene process, or the like). In other embodiments, the substrate 150 no active or passive devices.

The substrate 150 can bond pads 04 on a first side of the substrate 150 and bond pads 206 on a second side of the substrate 150 have (the second side being the first side of the substrate 150 opposite) to the second conductive connecting elements 603 connect to. In some embodiments, the bond pads 204 and 206 by creating recesses (not shown) in dielectric layers (not shown) on the first and second sides of the substrate 150 produced. The recesses can be created in such a way that the bond pads 204 and 206 can be embedded in the dielectric layers. In other embodiments, the recesses are omitted because the bond pads 204 and 206 can be fabricated on the dielectric layer. In some embodiments, the bond pads include 204 and 206 a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, or the like, or a combination thereof. The conductive material for the bond pads 204 and 206 can be deposited over the thin seed layer. The conductive material can be deposited by electrochemical plating, electroless plating, CVD, ALD, PVD, or the like, or a combination thereof. In one embodiment, the conductive material is the bond pads 204 and 206 Copper, tungsten, aluminum, silver, gold, or the like, or a combination thereof.

In one embodiment, the bond pads are 204 and 206 UBMs that have three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, other arrangements of materials and layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium-tungsten / copper or an arrangement of copper / nickel / gold, can also be used for the production of the bond pads 204 and 206 be used. Any suitable materials or layers of material used for the bond pads 204 and 206 are intended to be entirely within the scope of the present application.

In some embodiments, an underfill 154 between the first masked structure 601 and the substrate 150 getting produced. The underfill 154 can reduce mechanical stress and protect connection points caused by the melting of the second conductive connection elements 603 arise. The underfill 154 can be made with a capillary flow process after the structure has been attached, or it can be made with a suitable deposition process before the structure is attached.

In some embodiments, the second conductive connection elements are 603 melted to the first masked structure 601 on the bond pads 206 to fix. The second conductive connection elements 603 connect the structures, such as the metallization layers 208 in the substrate 150 , electrically and / or physically with the first capped structure 601 . In some embodiments, a solder resist is made on the substrate core. The first hidden structure 601 can be placed in openings in the solder resist to connect with the bond pads 206 to be connected electrically and mechanically. The solder resist can be used to protect areas of the substrate 150 can be used against external damage.

By using the first batch of IPDs 500 the overall structure can be given an increased capacity so that it can cope with the first functional die 60A and the second functional die 60B can work. This can be achieved without requiring a larger footprint, which would affect the overall size of the device. Finally, by choosing the number and size of each IPD die, exact capacity can be obtained without having to completely redesign the overall structure.

8th shows another embodiment in which the first IPD dies 50A and 50B and the second IPD dies 50C and 50D in a Rather than being connected in a front-to-front configuration as described above with reference to FIG 2 to 7th has been described. In particular, in this embodiment, the first IPD dies 50A and 50B physically and electrically to the rear redistribution structure 106 bonded before the encapsulation material 120 is applied instead of using an adhesive on the rear redistribution structure 106 to fix.

In a particular embodiment, the first IPD dies 50A and 50B using the die external contacts 217 and a process similar to the one referring to 5A described process for bonding the second IPD dies 50C and 50D to the front redistribution structure 122 is similar to the rear redistribution structure 106 bonded. For example, a pick-and-place process can be used to make the first IPD dies 50A and 50B in physical and electrical contact with the rear redistribution structure 106 bring to. After making contact, the first IPD dies 50A and 50B z. B. bonded with a hybrid bonding process, a dielectric bonding process or another suitable bonding process. However, any suitable bonding process or other joining process can be used.

After the first IPD dies 50A and 50B have been bonded, the method can continue as described above with reference to FIG 3rd to 8th has been described. For example, the following steps can be carried out: applying and thinning the encapsulation material 120 to get the first vias 116 to expose (but the encapsulation material 120 can also use the first IPD dies 50A and 50B remain in place as no electrical connections need to be made to this side); Manufacture the front redistribution structure 122 to make an electrical connection with the first vias 116 to manufacture; Bonding the second IPD dies 50C and 50D to the front redistribution structure 122 ; and applying the encapsulation material 136 to get the second IPD dies 50C and 50D to encapsulate to the first IPD stack 500 to manufacture. Also, the first IPD batch can 500 along with the first functional die 60A and the second functional die 60B on the third redistribution structure 138 are placed, the encapsulation material 146 can be applied and the structure can be with the substrate 150 get connected.

The 9A to 9C show another embodiment in which the first IPD stack 500 with second external connections 156 in addition to the first vias 116 is made to the rear redistribution structure 106 and the front-end redistribution structure 122 connect to. As in 9A is shown, in this embodiment, the rear redistribution structure 106 prepared as described above with reference to FIG 1 has been set out. For example, the dielectric layer 108 over the carrier substrate 102 (in 9A not shown individually) produced, and the one or more metallization structures 110 are over the dielectric layer 108 made to the rear redistribution structure 106 to manufacture.

After making the rear redistribution structure 106 can make the first vias 116 in electrical connection with the rear redistribution structure 106 getting produced. In one embodiment, the rear redistribution structure 106 can be prepared as described above with reference to FIG 2A has been described. For example, the rear redistribution structure 106 can be produced as follows: producing a seed layer; Placing a photoresist over the seed layer and then patterning the photoresist; Plating the materials of the first vias 116 into the openings of the photoresist; Removing the photoresist; and removing uncovered portions of the seed layer. However, all suitable methods and materials can be used for producing the first vias 116 be used.

In this embodiment, the first vias 116 but not the only link between the rear redistribution structure 106 and the front-end redistribution structure 122 be. Therefore the first need vias 116 not as big as the first IPD dies 50A and 50B and they are made to be of a smaller height than the first IPD dies 50A and 50B to have. For example, in this embodiment, the first vias 116 be made to have a first thickness T ₁ of about 10 µm to about 650 µm, e.g. B. of about 50 microns. However, any suitable thickness can be used.

9B Figure 12 shows a manufacture of the front redistribution structure 122 . In this embodiment, the front-side redistribution structure 122 but not on the encapsulation material 120 but it is created by the rear redistribution structure 106 separately, for example by placing them on a second carrier wafer (not shown individually), which is the carrier substrate 102 is similar, is produced. For example, the dielectric layer 124 over the second carrier wafer and a release liner 104 manufactured, and above the dielectric layer 124 become one or more metallization structures 126 produced.

9B also shows that after the front redistribution structure is made 122 the second IPD dies 50C and 50D to the front redistribution structure 122 be bonded. In one embodiment, the second IPD dies 50C and 50D bonded as described above with reference to FIG 5A has been set out. For example, the second IPD will be dies 50C and 50D placed with a pick-and-place process and then z. B. bonded with a hybrid bonding process. However, any suitable method for bonding the second IPD dies can be used 50C and 50D be used.

After the second IPD dies 50C and 50D to the front redistribution structure 122 have been bonded, they can with the encapsulation material 136 be encapsulated. In one embodiment, the encapsulation material can 136 applied as described above with reference to FIG 5A has been set out. However, any suitable encapsulation method can be used.

Finally shows 9B placing the second external connections 156 in electrical communication with the front redistribution structure 122 , the second external connections 156 along with the first vias 116 used to redistribute the rear structure 106 with the front redistribution structure 122 connect to. In one embodiment, the placement of the second external connections 156 begin by first removing the second carrier wafer and the adhesive layer to form the dielectric layer 124 the front-end redistribution structure 122 to expose. In one embodiment, the second carrier wafer can be removed as set forth above for the first carrier wafer, but any suitable removal method can be used.

After the dielectric layer 124 Once exposed, it can be patterned to form portions of the one or more metallization structures 126 to expose. In one embodiment, the dielectric layer can 124 z. B. be structured by laser drilling. In this process, a protective layer, such as an LTHC layer (LTHC: light-heat conversion) or a HogoMax layer (in 9B not shown individually), over the dielectric layer 124 deposited. A laser is then applied to the parts of the dielectric layer 124 directed to be removed. During laser drilling, the drilling energy can be about 0.1 mJ to about 30 mJ and the drilling angle can be about 0 ° to about 85 ° perpendicular to the dielectric layer 124 be. However, any suitable method can be used, such as photolithographic masking and etching methods.

After the dielectric layer 124 has been structured, the second external connections 156 through the dielectric layer 124 and in electrical communication with the front redistribution structure 122 placed. The second external connections 156 can be bumps such as microbumps or C ₄ bumps, and they can comprise a material such as tin or other suitable materials such as silver or copper. In one embodiment in which the second external connections 156 Solder bumps are, the second external connections can 156 be made by first forming a layer of tin with such commonly used methods as vapor deposition, electroplating, printing, solder transfer, ball placement, etc. to a thickness of e.g. B. is made about 100 microns. After the layer of tin has been produced on the structure, a reflow process can be performed to bring the material into the desired bump shapes.

9C shows bonding of the second external terminals 156 to the first vias 116 , creating the rear redistribution structure 106 and the front-end redistribution structure 122 be electrically connected. In one embodiment, the second external connections 156 after their production to the first vias 116 aligned and brought into physical contact with them, and bonding is performed. For example, in one embodiment in which the second external connections 156 The bonding process is a reflow process in which the temperature of the second external connections 156 is increased to a temperature at which the second external connections 156 liquefy and flow, so that the second external connections 156 to the first vias 116 be bonded after the second external connections 156 have solidified again. However, any suitable bonding technique can be used.

9C also shows that after bonding the second external terminals 156 to the first vias 116 the encapsulation material 120 around the second external connections 156 , the first vias 116 and the first IPD dies 50A and 50B can be applied to provide additional support between the rear redistribution structure 106 and the front-end redistribution structure 122 provide. In one embodiment, the encapsulation material can 120 be upset as it is above with reference to 3rd has been set out. For example, the encapsulation material 120 be applied by compression molding, compression molding or the like. However, any suitable method for applying the encapsulation material can be used 120 between the rear redistribution structure 106 and the front-end redistribution structure 122 be used.

In a further embodiment, the encapsulation material can 120 be an underfill material. In this embodiment, the encapsulation material 120 be made with a capillary flow process after the second external connections 156 to the first vias 116 have been bonded. However, any suitable method and material can be used.

After the first batch of IPD 500 In this embodiment, the method can be continued as described above with reference to FIG 6th to 8th has been set out. For example, the first IPD stack 500 along with the first functional die 60A and the second functional die 60B on the third redistribution structure 138 are placed, the encapsulation material 146 can be applied and the structure can be with the substrate 150 get connected. However, any suitable method for connecting the first IPD stack can be used 500 can be used with other structures.

10A Figure 12 shows yet another embodiment in which the first IPD stack 500 with more layers than just the first lower layer 301 and the first top layer 501 will be produced. In the embodiment shown in 10A is the first lower layer 301 prepared as described above with reference to FIG 1 to 8th has been set forth (wherein the illustrated embodiment is a front-to-back configuration, but any of the disclosed configurations can be used).

After the first lower layer 301 has been made, a first middle layer 303 over the first lower layer 301 made before the first top layer 501 will be produced. In one embodiment, the first middle layer comprises 303 a fourth redistribution layer 305 , second vias 307 , third IPD dies 50E and 50F and a third encapsulation material 309 . In one embodiment, the fourth redistribution layer 305 with similar processes and materials as the front redistribution structure 122 prepared above with reference to 4th has been described. For example, multiple dielectric layers and metallization layers are deposited alternately around the fourth redistribution layer 305 build up. However, any suitable method and material can be used.

After the fourth redistribution layer 305 has been made, the second vias 307 in electrical communication with the fourth redistribution layer 305 produced. In one embodiment, the second vias 307 with similar processes and materials as the first vias 116 prepared above with reference to FIG 2A have been described. For example, the second vias 307 can be made as follows: make a seed layer over the fourth redistribution layer 305 ; Placing a photoresist over the seed layer and then patterning the photoresist, with the second vias 307 made with the structure of the photoresist; Removing the photoresist; and removing uncovered portions of the seed layer. However, any suitable method and material can be used.

After the second vias 307 have been established, the third IPD can die 50E and 50F adjacent to the second vias 307 to be placed. In one embodiment, the third IPD may be dies 50E and 50F the first IPD dies 50A and 50B be similar (e.g. they can be capacitor dies), and they can e.g. B. with a pick-and-place process in physical and electrical contact with the fourth redistribution layer 305 to be brought. Then the third IPD dies 50E and 50F z. B. be bonded with a hybrid bonding process, a metal-metal bonding process, a dielectric bonding process, a combination thereof or the like. However, any suitable method can be used.

10A also shows that after bonding the third IPD dies 50E and 50F a third encapsulation material 309 about the third IPD dies 50E and 50F can be placed and thinned to make the second vias 307 to expose. In one embodiment, the third encapsulation material can 309 with similar processes and materials as the encapsulation material 120 above with reference to FIG 3rd has been described. However, any suitable method and material can be used.

After the first middle layer 303 can be the first top layer 501 over the first middle layer 303 are made, and the conductive connecting elements 152 be with the first lower layer 301 connected. In one embodiment, the first upper layer 501 be prepared as described above with reference to FIG 4th and 5 has been set out. For example, the first top layer 501 can be produced as follows: Production of the front-side redistribution structure 122 ; Place the second IPD dies 50C and 50D and bonding to the front redistribution structure 122 ; and encapsulating the second IPD dies 50C and 50D with the encapsulation material 136 . Likewise, the conductive connecting elements 152 be placed as described above with reference to 5A has been set out. However, any suitable method and material for making and / or placing the first top layer can be used 501 and the conductive connecting elements 152 be used.

10B FIG. 13 shows an equivalent circuit representing the equivalent capacitance obtained with the three-layer first IPD stack 500 can be achieved. In this embodiment, the capacitance (Ca) used by the first lower layer 301 can be obtained in the dashed box 507 shown (whereby the individual capacitances of the individual capacitors are labeled Ci, C2, ...), the capacitance (Cb), that of the first upper layer 501 can be obtained is in the dashed box 509 is shown (where the individual capacitances of the individual capacitors are designated with C ₁ , C ₂ , ...), and a capacitance (C _c ) that of the first middle layer 303 can be obtained is in a dashed box 1001 is shown (whereby the individual capacitances of the individual capacitors _{are labeled C 1} , C ₂ , ...). As can be seen, the fact that the individual IPD dies in the first IPD stack 500 (e.g. the first IPD dies 50A and 50B who have favourited the second IPD dies 50C and 50D and the third IPD dies 50E and 50F) stacked on top of each other and connected to each other, the IPD dies are connected in parallel with each other. Therefore, the total capacity (C _T ) for the first IPD stack can be 500 be the sum of the following capacities: the capacitance (C _a ) by the first lower layer 301 can be obtained of the capacitance (C _b ) that of the first upper layer 501 can be obtained and the capacitance (C _e ) that of the first middle layer 303 can be obtained (ie, C _T = C _a + C _B + C _c ). Therefore, a larger capacity can be obtained without increasing the total footprint, and the capacity can be adjusted, if necessary, simply by increasing or decreasing the number of layers or the number of IPD dies in each layer.

11 Figure 13 shows yet another embodiment where there are five layers in the first IPD stack 500 be used. For example, in this embodiment, the first lower layer 301 , the first middle layer 303 and the first top layer 501 made in the manner described here, but with only one of the IPD dies in each layer. In addition, a second middle layer is used in this embodiment 1101 and a third middle layer 1103 made that of the first middle layer 303 may be similar to those described above with reference to FIG 10A has been described (but with only one of the IPD dies). However, any number of layers can be used.

In this embodiment, the entire first IPD stack 500 with five layers have a total height H _o of 670 µm (e.g. 100 µm per IPD die plus 30 µm per redistribution layer and molding compound on both sides of four of the IPD dies plus 50 µm for the redistribution layer and the molding compound on both sides the first top layer 501 ). In addition, in embodiments in which the individual IPD dies can each have a capacitance of 1.1 μF / mm ² and an active area of 32.27 mm ² , the individual layers can each have a single-layer capacitance of 35.5 μP . Therefore, the total capacity of the first IPD stack is 500 in this particular embodiment about 178 µP. However, any suitable parameters can be used.

12th shows a top-down variant of a possible layout with the first capped structure and the substrate 150 . In the illustrated embodiment, the first IPD stack 500 on the substrate 150 between a first of the second functional dies 60B and a second of the second functional dies 60B (e.g. between two high-bandwidth storage dies). It also becomes one of the first functional dies 60A (e.g. a System-on-a-Chip-Die) with the substrate 150 each adjacent to the first of the second functional dies 60B , the second of the second functional dies 60B and the first IPD batch 500 connected. However, any suitable layout can be used.

In one embodiment, any of the first functional dies 60A a first dimension D ₁ of about 10 mm to about 100 mm, e.g. B. of about 33 mm, and a second dimension D ₂ of about 8 mm to about 95 mm, e.g. B. of about 25 mm. Likewise, each of the second functional dies can 60B a third dimension D ₃ from about 3 mm to about 20 mm, e.g. B. of about 12 mm, and a fourth dimension D ₄ of about 2 mm to about 20 mm, e.g. B. of about 8 mm. However, any suitable dimensions can be used.

The first batch of IPDs 500 can be made to have dimensions that fit the small footprint offered by the first functional dies 60A and the second functional dies 60B is left over. Hence the first IPD batch 500 a fifth dimension D ₅ from about 2 mm to about 20 mm, e.g. B. of about 8 mm, and a sixth dimension D ₆ of also about 2 mm to about 20 mm, z. B. of about 8 mm. However, any suitable dimensions can be used.

By encapsulating multiple IPD dies in one package using the first IPD stack 500 a larger parameter (e.g. a larger capacity) can be obtained without also requiring a larger footprint. In addition, the desired capacity can be tailored exactly by using both a desired number of layers and a desired number and / or size of IPD dies. Therefore, a desired capacity can be achieved without sacrificing size.

According to an embodiment, a semiconductor device comprises: a first integrated passive device (IPD); a first molding compound encapsulating the first IPD; a redistribution structure over and electrically connected to the first IPD; a second IPD on a side of the redistribution structure opposite the first IPD, the second IPD being electrically connected to the first IPD through the redistribution structure; and a second molding compound encapsulating the second IPD. In one embodiment, a front of the first IPD faces a front of the second IPD. In one embodiment, a front side of the first IPD faces a rear side of the second IPD. In one embodiment, the semiconductor device further has a conductive via that extends through the first molding compound. In one embodiment, the semiconductor device further comprises a conductive structure element extending through the first molding compound, the conductive structure element comprising: a conductive via, and a solder area on the conductive via. In one embodiment, the first IPD is electrically connected to the redistribution structure through a copper pillar. In one embodiment, the first IPD is electrically connected to the redistribution structure by a solder area.

According to a further embodiment, a semiconductor device comprises: a first redistribution structure; a first functional die bonded to the first redistribution structure; and a first stack of integrated passive devices bonded to the first redistribution structure, the first stack of integrated passive devices comprising: a second redistribution structure, a first integrated passive device over the second redistribution structure, a third redistribution structure over the first integrated passive Device, wherein the third redistribution structure is connected to the second redistribution structure by first vias, and a second integrated passive device over the third redistribution structure. In one embodiment, the semiconductor device further comprises: a third integrated passive device between the second redistribution structure and the third redistribution structure; and a first encapsulation material enclosing the third integrated passive device and the first integrated passive device. In one embodiment, the first vias comprise copper pillars. In one embodiment, the first vias include: copper pillars; and solder balls in physical contact with the copper pillars. In one embodiment, the first integrated passive device and the second integrated passive device are configured in a front-to-front configuration. In one embodiment, the first integrated passive device and the second integrated passive device are configured in a back-to-front configuration. In one embodiment, the first stack of integrated passive devices further comprises: a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second vias; and a third integrated passive device over the fourth redistribution structure.

According to yet another embodiment, a method for producing a semiconductor device has the following steps: producing a first redistribution structure over a carrier wafer; Making vias over the first redistribution structure; Placing a first integrated passive device on the first redistribution structure adjacent to the vias; Encapsulating the first integrated passive device and the vias with an encapsulation material; Forming a second redistribution structure over the encapsulation material and in electrical communication with the vias; and placing a second integrated passive device on the second redistribution structure and in electrical communication with the vias. In one embodiment, when the first integrated passive device is placed on the first redistribution structure, the first integrated passive device is placed in electrical communication with the first redistribution structure. In one embodiment, an adhesive is used in placing the first integrated passive device on the first redistribution structure. In one embodiment, when the first integrated passive device is placed, an integrated passive capacitor is placed. In one embodiment, the method further comprises bonding the first redistribution structure to a third redistribution layer. In one embodiment, the method further comprises: bonding a first functional die to the third redistribution layer; and encapsulating the first functional die in an encapsulation material.

Features of various embodiments have been described above so that those skilled in the art may better understand aspects of the present invention. It should be understood by those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same goals and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of the present invention.

Claims (20)

Semiconductor device with: a first integrated passive device, IPD; a first molding compound encapsulating the first IPD; a redistribution structure over and electrically connected to the first IPD; a second IPD on a side of the redistribution structure opposite the first IPD, the second IPD being electrically connected to the first IPD through the redistribution structure; and a second molding compound that encapsulates the second IPD. Semiconductor device according to Claim 1 , wherein a front side of the first IPD faces a front side of the second IPD. Semiconductor device according to Claim 1 , with a front side of the first IPD facing a rear side of the second IPD. The semiconductor device of any preceding claim, further comprising a conductive via extending through the first molding compound. The semiconductor device of claim 1, further comprising a conductive structure element extending through the first molding compound, wherein the conductive structure element comprises: a conductive via; and a solder area on the conductive via. A semiconductor device according to any preceding claim, wherein the first IPD is electrically connected to the redistribution structure by a copper pillar. Semiconductor device according to one of the Claims 1 to 5 , wherein the first IPD is electrically connected to the redistribution structure by a solder area. Semiconductor device with: a first redistribution structure; a first functional die bonded to the first redistribution structure; and a first stack of integrated passive devices bonded to the first redistribution structure, the first stack of integrated passive devices comprising: a second redistribution structure, a first integrated passive device over the second redistribution structure, a third redistribution structure over the first integrated passive device, the third redistribution structure being connected to the second redistribution structure by first vias, and a second integrated passive device over the third redistribution structure. Semiconductor device according to Claim 8 further comprising: a third integrated passive device between the second redistribution structure and the third redistribution structure; and a first encapsulation material enclosing the third integrated passive device and the first integrated passive device. Semiconductor device according to Claim 8 or 9 , the first vias having copper pillars. Semiconductor device according to Claim 10 wherein the first vias include: copper pillars; and solder balls in physical contact with the copper pillars. Semiconductor device according to one of the Claims 8 to 11 wherein the first integrated passive device and the second integrated passive device are configured in a front-to-front configuration. Semiconductor device according to one of the Claims 8 to 11 wherein the first integrated passive device and the second integrated passive device are configured in a back-to-front configuration. Semiconductor device according to one of the Claims 8 to 13th wherein the first stack of integrated passive devices further comprises: a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second vias; and a third integrated passive device over the fourth redistribution structure. A method of manufacturing a semiconductor device comprising the steps of: Producing a first redistribution structure over a carrier wafer; Making vias over the first redistribution structure; Placing a first integrated passive device on the first redistribution structure adjacent to the vias; Encapsulating the first integrated passive device and the vias with an encapsulation material; Forming a second redistribution structure over the encapsulation material and in electrical communication with the vias; and Placing a second integrated passive device on the second redistribution structure and in electrical communication with the vias. Procedure according to Claim 15 wherein placing the first integrated passive device on the first redistribution structure places the first integrated passive device in electrical communication with the first redistribution structure. Procedure according to Claim 15 or 16 wherein an adhesive is used in placing the first integrated passive device on the first redistribution structure. Method according to one of the Claims 15 to 17th wherein in placing the first integrated passive device, an integrated passive capacitor is placed. Method according to one of the Claims 15 to 18th which further comprises bonding the first redistribution structure to a third redistribution layer. Procedure according to Claim 19 further comprising: bonding a first functional die to the third redistribution layer; and encapsulating the first functional die in an encapsulation material.

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