CN105679703A - Silicon through hole structure-based metal filling method and silicon through hole structure - Google Patents
Silicon through hole structure-based metal filling method and silicon through hole structure Download PDFInfo
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- CN105679703A CN105679703A CN201610170209.1A CN201610170209A CN105679703A CN 105679703 A CN105679703 A CN 105679703A CN 201610170209 A CN201610170209 A CN 201610170209A CN 105679703 A CN105679703 A CN 105679703A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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Abstract
The invention relates to the technical field of three-dimensional integrated circuits, in particular to a silicon through hole structure-based metal filling method and a silicon through hole structure. The method comprises the following steps: after bonding a bearing substrate and a top silicon wafer, etching a silicon through hole on the top silicon wafer; sequentially depositing an insulating layer and a barrier layer in the silicon through hole; depositing a metal seed layer on the surface of the barrier layer in an atomic layer deposition manner; and depositing a metal conductor layer on the surface of the metal seed layer. The metal seed layer is added between the barrier layer and the metal conductor layer, so that circuit disconnection caused by a conductor fault can be avoided; and meanwhile, the condition that deposition of the metal seed layer has good surface coverage on any shape and form is achieved in the atomic layer deposition manner; the condition that the surface of the barrier layer can completely cover the metal seed layer is ensured; the circuit disconnection caused by the conductor fault is further avoided; and the process reliability of metal filling is improved.
Description
Technical field
The present invention relates to three dimensional integrated circuits technical field, particularly relate to a kind of metal filled method based on through-silicon via structure and through-silicon via structure.
Background technology
At present, the three-dimensional integration technology interconnected based on silicon through hole (ThroughSiliconVias, TSV) is the new direction of semiconductor applications research and development. Wherein, three dimensional integrated circuits is owing to adopting three-dimensional stacked mode, therefore can by MEMS (MicroElectroMechanicalSystem, MEMS), the module such as radio-frequency module, internal memory and processor is integrated in a system, greatly increase the integrated level of system, reduce package body sizes and weight, increase packaging density, make to hold in unit volume maximum assemblies, reduce form factor. Further, realized the interconnected communication of interlayer by TSV, it is possible to effectively shorten wire length, thus reducing dead resistance and the electric capacity of interconnection line, it also reducing time constant signal delay, improve signal transmission rate, adding bandwidth. Further, owing to the length of power consumption and interconnection line has direct relation, the more long power consumption of interconnection line is more big, and the more short power consumption of interconnection line is more little, and therefore, the power consumption of three dimensional integrated circuits is much smaller relative to ordinary two dimensional integrated circuit. Finally, the cost of three dimensional integrated circuits is also low than two-dimensional integrated circuit.
Based in the TSV three-dimensional integration technology interconnected, the difference according to TSV processing technology order, first through hole and two kinds of technology modes of rear through hole can be divided into. First through hole, refers to first etching through hole, refills and is fitted on operation wafer, then thinning, that is, the design phase before complementary mos device (ComplementaryMetalOxideSemiconductor, CMOS) or the interconnection of rear road gets involved. Rear through hole, refers to first by wafer bonding to another chip or wafer, then etching through hole again, i.e. the later stage after the interconnection of rear road or bonding starts. Wherein, rear through hole is to realize the compatible a kind of important mode of CMOS and MEMS, particularly in silicon on glass bonding structure (SiliconOnGlass, SOG).
But, in the silicon of SOG structure devices and glass interface owing to over etching can cause horizontal undercutting, this effect is notch effect (footing/notching), impact due to notch effect, etching process can cause the sidewall of silicon structure and the damage of bottom, thus the filling of subsequent metal will be impacted, generally, metal material is all the surface adopting chemical vapor deposition mode to be deposited on TSV through hole sidewall, no matter it is which kind of is metal filled, in sidewall and bottom damaged portion, all easily conductor fault-layer-phenomenon occurs in Metal deposition process, and then produce space at TSV conductor with circuit part, cause circuit breaker, reduce the reliability of circuit.
Summary of the invention
The present invention, by providing a kind of metal filled method based on through-silicon via structure and through-silicon via structure, solves the technical problem of the circuit breaker that three dimensional integrated circuits brings in prior art due to notch effect.
Embodiments providing a kind of metal filled method based on through-silicon via structure, described method includes:
When after carrying substrate and top wafer bonding, described top silicon chip etches silicon through hole;
Sequentially deposition insulating layer and barrier layer in described silicon through hole;
Atomic layer deposition mode is utilized to deposit metal seed layer on the surface on described barrier layer;
Surface deposition metal conductor layer at described metal seed layer.
Preferably, etching before silicon through hole on the silicon chip of described top, described method also includes:
Bottom circuit is made on the surface of described carrying substrate;
The one side deposited oxide layer at described bottom circuit place on described carrying substrate, and in described oxide layer etching oxidation layer through hole;
By described carrying substrate by the one side at described oxide layer place and described top wafer bonding.
Preferably, described by described carrying substrate by after the one side at described oxide layer place and described top wafer bonding, described method also includes:
Described top silicon chip is carried out thinning.
Preferably, described etching silicon through hole on the silicon chip of described top, including:
Described top silicon chip utilize dry etching mode etch described silicon through hole.
Preferably, the described surface deposition metal conductor layer at described metal seed layer, including:
Chemical vapor deposition mode is utilized to deposit metal conductor layer on the surface of described metal seed layer.
Preferably, by plasma chemical vapor deposition mode to deposition insulating layer in described silicon through hole.
Based on same inventive concept, the embodiment of the present invention also provides for a kind of through-silicon via structure, including:
Carrying substrate;
Bottom circuit, described bottom circuit is positioned at the surface of described carrying substrate;
Oxide layer, the one side that described oxide layer is covered on described carrying substrate described bottom circuit place, described oxide layer is etched with oxide layer through hole;
Top silicon chip, described top wafer bonding is the one side at described oxide layer place on described carrying substrate, and described top silicon chip is etched with silicon through hole, and described silicon through hole is positioned at the surface of described oxide layer through hole;
Insulating barrier, the surface of the described oxide layer that described insulating barrier is deposited in the inner surface of described silicon through hole, described silicon through hole, and the inner surface of described oxide layer through hole;
Barrier layer, described barrier layer deposition is on the surface of described insulating barrier;
Metal seed layer, described metal seed layer is deposited on the surface on described barrier layer;
Metal conductor layer, described metal conductor layer is deposited on the surface of described metal seed layer.
Preferably, the thickness range of described bottom circuit is 1000-10000 angstrom.
Preferably, the thickness range of described metal seed layer is 50-5000 angstrom.
One or more technical schemes in the embodiment of the present invention, at least have the following technical effect that or advantage:
The present invention by increasing metal seed layer between barrier layer and metal conductor layer, it can be avoided that the circuit breaker that conductor tomography brings, simultaneously, any pattern is all had good surface coverage by the deposit realizing metal seed layer in atomic layer deposition mode, ensure that the surface on barrier layer can be completely covered metal seed layer, avoid the circuit breaker that conductor tomography brings further, improve metal filled reliability of technology, and the stability of TSV conductor conduction, achieve the vertical interconnection of interlayer in three dimensional integrated circuits, effectively shorten wire length, improve level of integrated system.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
Fig. 1 is the flow chart of a kind of metal filled method based on through-silicon via structure in the embodiment of the present invention;
Fig. 2 is the sectional view carrying substrate in the embodiment of the present invention;
Fig. 3 is the sectional view after making bottom circuit on carrying substrate in the embodiment of the present invention;
Fig. 4 be in the embodiment of the present invention on carrying substrate sectional view after deposited oxide layer etching oxidation layer through hole;
Fig. 5 is the sectional view after carrying substrate and top wafer bonding in the embodiment of the present invention;
Fig. 6 is the sectional view after etching silicon through hole on the silicon chip of top in the embodiment of the present invention;
Fig. 7 is the sectional view in the embodiment of the present invention after deposition insulating layer;
Fig. 8 is the sectional view in the embodiment of the present invention after barrier layer;
Fig. 9 is the sectional view after depositing metal seed layer in the embodiment of the present invention;
Figure 10 is the sectional view after depositing metal conductor layer in the embodiment of the present invention;
Figure 11 is the enlarged drawing at location A place in the embodiment of the present invention.
Wherein, 1 is carrying substrate, and 2 is bottom circuit, and 3 is oxide layer, and 31 is oxide layer through hole, and 4 is top silicon chip, and 41 is silicon through hole, and 5 is insulating barrier, and 6 is barrier layer, and 7 is metal seed layer, and 8 is metal conductor layer.
Detailed description of the invention
For solving the technical problem of the circuit breaker that three dimensional integrated circuits brings in prior art due to notch effect, the present invention provides a kind of metal filled method based on through-silicon via structure and through-silicon via structure.
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiments. Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
The embodiment of the present invention provides a kind of metal filled method based on through-silicon via structure, is applied to the interconnection of three dimensional integrated circuits interlayer and other three-dimensional stacked interconnection architectures. As it is shown in figure 1, described method includes:
Step 101: when after carrying substrate 1 and top silicon chip 4 bonding, etch silicon through hole 41 on described top silicon chip 4.
Step 102: sequentially deposition insulating layer 5 and barrier layer 6 in described silicon through hole 41.
Step 103: utilize atomic layer deposition mode to deposit metal seed layer 7 on the surface on described barrier layer 6.
Step 104: at the surface deposition metal conductor layer 8 of described metal seed layer 7.
Specifically, before step 101, first, utilize carrying substrate 1 as the substrate of through-silicon via structure, referring to Fig. 2, need optional different types of carrying substrate 1 according to different components. Then, bottom circuit 2 is made on the surface of carrying substrate 1, referring to Fig. 3. The making of bottom circuit 2 being included to deposit and the etching of metal, ultimately form underlying metal lead-in wire, the material of bottom circuit 2 can be aluminum or copper, and the thickness range of bottom circuit 2 is 1000-10000 angstromThen, the one side deposited oxide layer 3 at bottom circuit 2 place on carrying substrate 1, concrete, top from bottom circuit 2, surface deposition oxide layer 3 to carrying substrate 1 and bottom circuit 2, thus, a part of oxide layer 3 covers the surface of carrying substrate 1, another part oxide layer 3 covers the surface of bottom circuit 2, generally, select plasma enhanced CVD mode (PlasmaEnhancedChemicalVaporDeposition, the PECVD) deposited oxide layer 3 of low technological temperature. Further, after having deposited oxide layer 3, etching oxidation layer through hole 31 in oxide layer 3, referring to Fig. 4, the quantity of oxide layer through hole 31 can select according to actual needs. Finally, bonding top silicon chip 4 on carrying substrate 1, referring to Fig. 5. Concrete, carrying substrate 1 is bonded with top silicon chip 4 by the one side at oxide layer 3 place, it is preferred that low-temperature-direct-bonding can be adopted.
In this application, after carrying substrate 1 is bonded with top silicon chip 4, in a step 101, etching silicon through hole 41 on the silicon chip 4 of top, referring to Fig. 6. Concrete, the top silicon chip 4 covered above oxide layer through hole 31 being performed etching, forms silicon through hole 41, silicon through hole 41 is positioned at the surface of oxide layer through hole 31, the position one_to_one corresponding of the oxide layer through hole 31 in oxide layer 3 and the silicon through hole 41 on the silicon chip 4 of top. Preferably, oxide layer through hole 31 and silicon through hole 41 are coaxial, i.e. the dead in line of the axis of oxide layer through hole 31 and silicon through hole 41. It addition, for ensureing the pattern and the degree of depth that etch, reduce the impact of notch effect further, reduce the damage bottom silicon through hole 41, the silicon through hole 41 of the application adopts dry etching.
After silicon through hole 41 has etched, step 102 first to deposition insulating layer 5 in silicon through hole 41, thus, the surface of the oxide layer 3 in the inner surface of silicon through hole 41, silicon through hole 41, and the inner surface of oxide layer through hole 31, be all covered with insulating barrier 5, referring to Fig. 7. Under normal circumstances, the material of insulating barrier 5 is the dielectric such as silicon oxide or silicon nitride. The effect of insulating barrier 5 is to realize the electric isolution between conductive interconnections through hole and quasiconductor carrying substrate 1. In the process of deposition insulating layer 5, PECVD is adopted to be deposited. After deposition insulating layer 5 in silicon through hole 41, then to barrier layer 6 in silicon through hole 41, thus, barrier layer 6 forms the surface at insulating barrier 5, referring to Fig. 8. The material on barrier layer 6 can be titanium or titanium nitride or tantalum or chromium or tantalum nitride. Barrier layer 6 can increase the adhesiveness of metal and insulating barrier 5, thus improving technology stability.
Further, in step 103, forming metal seed layer 7 by atomic layer deposition mode (AtomicLayerDeposition, ALD) on the surface on barrier layer 6, referring to Fig. 9, the thickness range of metal seed layer 7 isFor tungsten for packing material, utilize ALD at the surface deposition tungsten on barrier layer 6.
Further, at step 104, it is preferred that adopting CVD at the surface deposition metal conductor layer 8 of metal seed layer 7, referring to Figure 10, meanwhile, in Figure 10, the enlarged drawing at location A place is referring to Figure 11. Metal conductor layer 8 is as the TSV conductor material interconnected, it is possible to for the material such as tungsten or copper. For tungsten, by CVD at metal seed layer 7 surface deposition tungsten, if tungsten covers the upper strata of top silicon chip 4 during deposit, follow-up by cmp or dry etching mode, the tungsten pushing up silicon chip 4 upper strata is removed. Further, metal conductor layer 8 carries out secondary deposit, i.e. on layer of metal conductor layer 8, deposit layer of metal conductor layer 8 again, by depositing double layer of metal conductor layer 8, it is possible to obtain better transport properties. Finally, metal conductor layer 8 can make upper strata circuit or other structures according to prior art.
The application by increasing metal seed layer 7 between barrier layer 6 and metal conductor layer 8, namely, before utilizing CVD to deposit metal conductor layer 8, layer of metal Seed Layer 7 is provided for CVD, it can be avoided that the circuit breaker that conductor tomography brings, simultaneously, any pattern is all had good surface coverage by the deposit realizing metal seed layer 7 with ALD, ensure that the surface on barrier layer 6 can be completely covered metal seed layer 7, avoid the circuit breaker that conductor tomography brings further, improve metal filled reliability of technology, and the stability of TSV conductor conduction, achieve the vertical interconnection of interlayer in three dimensional integrated circuits, effectively shorten wire length, improve level of integrated system.
It should be noted that the material of metal seed layer 7 can select the material identical with metal conductor layer 8, such as tungsten or aluminum. Metal seed layer 7 adopts ALD to be deposited, and metal conductor layer 8 adopts CVD to be deposited.
It addition, after carrying substrate 1 and top silicon chip 4 being bonded, described method also includes: carry out thinning to top silicon chip 4. The thickness pushing up silicon chip 4 after thinning is determined with depth-to-width ratio by the diameter of required silicon through hole 41, through-silicon via structure for different types of structure, and different demands, the diameter of silicon through hole 41 is all different from depth-to-width ratio, and the diameter range of silicon through hole 41 is generally 0.5-10um, depth-to-width ratio scope 1:1-50:1, such as, the demand diameter of silicon through hole 41 is 3um, and depth-to-width ratio is 10:1, then, the thickness of the top silicon chip 4 after thinning is 30um.
Based on same inventive concept, the embodiment of the present application also provides for a kind of through-silicon via structure, and as shown in Figure 10, described through-silicon via structure includes:
Carrying substrate 1;
Bottom circuit 2, bottom circuit 2 is positioned at the surface of carrying substrate 1;
Oxide layer 3, oxide layer 3 is covered in and carries the one side at bottom circuit 2 place on substrate 1, and oxide layer 3 is etched with oxide layer through hole 31;
Top silicon chip 4, top silicon chip 4 is bonded to and carries the one side at oxide layer 3 place on substrate 1, is positioned on the top silicon chip 4 above oxide layer through hole 31 and is etched with silicon through hole 41;
Insulating barrier 5, the surface of the oxide layer 3 that insulating barrier 5 is deposited in the inner surface of silicon through hole 41, silicon through hole 41, and the inner surface of oxide layer through hole 31;
Barrier layer 6, barrier layer 6 is deposited on the surface of insulating barrier 5;
Metal seed layer 7, metal seed layer 7 is deposited on the surface on barrier layer 6;
Metal conductor layer 8, metal conductor layer 8 is deposited on the surface of metal seed layer 7.
In specific implementation process, carrying substrate 1 is as the substrate of through-silicon via structure.The material of bottom circuit 2 is aluminum or copper, and the thickness range of bottom circuit 2 isThe material of insulating barrier 5 is the dielectric such as silicon oxide or silicon nitride. The material on barrier layer 6 is titanium or titanium nitride or tantalum or chromium or tantalum nitride. The thickness range of metal seed layer 7 is
The present invention by increasing metal seed layer 7 between barrier layer 6 and metal conductor layer 8, it can be avoided that the circuit breaker that conductor tomography brings, improve metal filled reliability of technology, and the stability of TSV conductor conduction, achieve the vertical interconnection of interlayer in three dimensional integrated circuits, effectively shorten wire length, improve level of integrated system.
Technical scheme in above-mentioned the embodiment of the present application, at least has the following technical effect that or advantage:
The present invention by increasing metal seed layer between barrier layer and metal conductor layer, it can be avoided that the circuit breaker that conductor tomography brings, simultaneously, any pattern is all had good surface coverage by the deposit realizing metal seed layer in atomic layer deposition mode, ensure that the surface on barrier layer can be completely covered metal seed layer, avoid the circuit breaker that conductor tomography brings further, improve metal filled reliability of technology, and the stability of TSV conductor conduction, achieve the vertical interconnection of interlayer in three dimensional integrated circuits, effectively shorten wire length, improve level of integrated system.
Although preferred embodiments of the present invention have been described, but those skilled in the art are once know basic creative concept, then these embodiments can be made other change and amendment. So, claims are intended to be construed to include preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, the present invention can be carried out various change and modification without deviating from the spirit and scope of the present invention by those skilled in the art. So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. the metal filled method based on through-silicon via structure, it is characterised in that described method includes:
When after carrying substrate and top wafer bonding, described top silicon chip etches silicon through hole;
Sequentially deposition insulating layer and barrier layer in described silicon through hole;
Atomic layer deposition mode is utilized to deposit metal seed layer on the surface on described barrier layer;
Surface deposition metal conductor layer at described metal seed layer.
2. the method for claim 1, it is characterised in that etching before silicon through hole on the silicon chip of described top, described method also includes:
Bottom circuit is made on the surface of described carrying substrate;
The one side deposited oxide layer at described bottom circuit place on described carrying substrate, and in described oxide layer etching oxidation layer through hole;
By described carrying substrate by the one side at described oxide layer place and described top wafer bonding.
3. method as claimed in claim 2, it is characterised in that described by described carrying substrate by after the one side at described oxide layer place and described top wafer bonding, described method also includes:
Described top silicon chip is carried out thinning.
4. the method for claim 1, it is characterised in that described etching silicon through hole on the silicon chip of described top, including:
Described top silicon chip utilize dry etching mode etch described silicon through hole.
5. the method for claim 1, it is characterised in that the described surface deposition metal conductor layer at described metal seed layer, including:
Chemical vapor deposition mode is utilized to deposit metal conductor layer on the surface of described metal seed layer.
6. the method for claim 1, it is characterised in that by plasma chemical vapor deposition mode to deposition insulating layer in described silicon through hole.
7. a through-silicon via structure, it is characterised in that including:
Carrying substrate;
Bottom circuit, described bottom circuit is positioned at the surface of described carrying substrate;
Oxide layer, the one side that described oxide layer is covered on described carrying substrate described bottom circuit place, described oxide layer is etched with oxide layer through hole;
Top silicon chip, described top wafer bonding is the one side at described oxide layer place on described carrying substrate, and described top silicon chip is etched with silicon through hole, and described silicon through hole is positioned at the surface of described oxide layer through hole;
Insulating barrier, the surface of the described oxide layer that described insulating barrier is deposited in the inner surface of described silicon through hole, described silicon through hole, and the inner surface of described oxide layer through hole;
Barrier layer, described barrier layer deposition is on the surface of described insulating barrier;
Metal seed layer, described metal seed layer is deposited on the surface on described barrier layer;
Metal conductor layer, described metal conductor layer is deposited on the surface of described metal seed layer.
8. through-silicon via structure as claimed in claim 7, it is characterised in that the thickness range of described bottom circuit is 1000-10000 angstrom.
9. through-silicon via structure as claimed in claim 7, it is characterised in that the thickness range of described metal seed layer is 50-5000 angstrom.
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| CN201610170209.1A CN105679703A (en) | 2016-03-23 | 2016-03-23 | Silicon through hole structure-based metal filling method and silicon through hole structure |
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| CN201610170209.1A CN105679703A (en) | 2016-03-23 | 2016-03-23 | Silicon through hole structure-based metal filling method and silicon through hole structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044477A (en) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Making method of metal plug adapter |
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN102593316A (en) * | 2011-01-13 | 2012-07-18 | 三星Led株式会社 | Wafer level light-emitting device package and method of manufacturing the same |
| CN102903670A (en) * | 2012-09-29 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Low-cost TSV (through silicon via) three-dimensional integration process method |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
| US20140015136A1 (en) * | 2012-07-12 | 2014-01-16 | Zhenghao Gan | Ic device including package structure and method of forming the same |
| US20150021784A1 (en) * | 2013-07-16 | 2015-01-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (tsv) |
-
2016
- 2016-03-23 CN CN201610170209.1A patent/CN105679703A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044477A (en) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Making method of metal plug adapter |
| CN102593316A (en) * | 2011-01-13 | 2012-07-18 | 三星Led株式会社 | Wafer level light-emitting device package and method of manufacturing the same |
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| US20140015136A1 (en) * | 2012-07-12 | 2014-01-16 | Zhenghao Gan | Ic device including package structure and method of forming the same |
| CN102903670A (en) * | 2012-09-29 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Low-cost TSV (through silicon via) three-dimensional integration process method |
| US20150021784A1 (en) * | 2013-07-16 | 2015-01-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (tsv) |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
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