CN104716055A - Wafer-level packaging method - Google Patents
Wafer-level packaging method Download PDFInfo
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- CN104716055A CN104716055A CN201310675699.7A CN201310675699A CN104716055A CN 104716055 A CN104716055 A CN 104716055A CN 201310675699 A CN201310675699 A CN 201310675699A CN 104716055 A CN104716055 A CN 104716055A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 103
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000002161 passivation Methods 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 76
- 238000002955 isolation Methods 0.000 claims description 76
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000003085 diluting agent Substances 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 5
- 208000012826 adjustment disease Diseases 0.000 claims description 4
- 238000003466 welding Methods 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 239000003795 chemical substances by application Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005336 cracking Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- -1 Xi Yin Chemical compound 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ZCQWOFVYLHDMMC-UHFFFAOYSA-N Oxazole Chemical compound C1=COC=N1 ZCQWOFVYLHDMMC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NTSDHVIXFWZYSM-UHFFFAOYSA-N [Ag].[Sb].[Sn] Chemical compound [Ag].[Sb].[Sn] NTSDHVIXFWZYSM-UHFFFAOYSA-N 0.000 description 1
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 description 1
- HRPKYGWRFPOASX-UHFFFAOYSA-N [Zn].[Ag].[Sn] Chemical compound [Zn].[Ag].[Sn] HRPKYGWRFPOASX-UHFFFAOYSA-N 0.000 description 1
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000004375 physisorption Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Element Separation (AREA)
Abstract
A wafer-level packaging method comprises the steps that a semiconductor wafer is provided and comprises a first surface and a second surface, and a groove is formed in the first surface of the semiconductor wafer; a bonding auxiliary layer is formed on the semiconductor wafer and the bottom and the side wall of the groove; an isolating layer is formed on the bonding auxiliary layer; the isolating layer and the bonding auxiliary layer are etched along the groove, the isolating layer and the bonding auxiliary layer at the bottom of the groove are removed, and the semiconductor wafer is exposed; a metal interconnecting line layer is formed on the isolating layer, the side wall of the groove and the part, exposed out of the bottom of the groove, of the semiconductor wafer; then, a bonding pad, a passivation layer, a welding ball and other structures are formed on the metal interconnecting line layer, and the wafer-level packaging is finished. According to the technical scheme, the bonding auxiliary layer is formed on the semiconductor wafer, then, the isolating layer is formed above the bonding auxiliary layer, and therefore the bonding strength of the isolating layer and the semiconductor wafer is effectively improved.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of wafer-level packaging method.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) being the one of chip package mode, is, after full wafer wafer production completes, directly on wafer, carry out packaging and testing, single chips is just cut into after completing, must through routing or filler.Wafer-level packaging has the excellent advantage of electrical property after the little and encapsulation of package dimension, and wafer-level packaging also easily assemble compatibility with wafer manufacture and chip, and simplification wafer is fabricated onto the process of product turnout, reduction integral production cost.
Shown in figure 1, in wafer-level packaging process, usually need to stick with glue agent 13 and wafer 10 and substrate 12 are bonded together, then make isolation layer 11 to be kept apart by the conductive structure of crystal column surface and follow-up formation on wafer 10 surface.Lost efficacy in order to avoid adhesive Yin Gaowen, and usually needed to adopt low temperature oxide (Low temperature oxide, LTO) to form isolation layer 11.
But, in testing to isolation layer 11 and wafer 10 bonding strength, shown in figure 2, apply pressure soon to described isolation layer 11 edge, just start to occur crack 10 and 11 between described isolation layer 11 and wafer 10.Wherein, A point is pressurization starting point, and B point is cracking appearance point.Shown in figure 3, after applying certain pressure to isolation layer 11 mid portion, after certain interval of time, there will be larger crack 13 and 14 equally.Wherein, A ' point is pressurization starting point, and B ' point is cracking appearance point.Isolation layer 11 is poor with the bonding strength of wafer 10, and there is separator 11 by the hidden danger that wafer 10 peels off, this hidden danger directly affects subsequent technique and carries out, and the reliability of the final semiconductor device formed.
For this reason, need a kind of new wafer-level packaging method, to improve the bonding strength of isolation layer and wafer, thus preventing isolation layer from cracking occurring or peels off, is the problem that those skilled in the art need solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer-level packaging method, to improve the waterproof ability with isolation layer, prevents isolation layer from cracking occurring or peels off, thus strengthens the buffer action of isolation layer.
For solving the problem, the invention provides a kind of wafer-level packaging method, comprising:
There is provided semiconductor crystal wafer, described semiconductor crystal wafer comprises first surface and second surface, and described first surface is relative with second surface position;
The second surface of described semiconductor crystal wafer is adhered to substrate;
Groove is formed at the first surface of described semiconductor crystal wafer;
At the first surface of described semiconductor crystal wafer, and the bottom of described groove and sidewall are formed and adhere to auxiliary layer;
Described adhesion auxiliary layer forms isolation layer;
Along isolation layer described in described recess etch and adhesion auxiliary layer, remove the isolation layer of described bottom portion of groove and adhere to auxiliary layer, exposing described semiconductor crystal wafer;
At the sidewall of described isolation layer, described groove, and the exposed semiconductor crystal wafer of described bottom portion of groove forms metal interconnecting wires layer;
Described metal interconnecting wires layer forms pad, and described metal interconnecting wires layer is electrically connected with described pad;
Passivation layer is formed layer by layer with on described pad at described metal interconnecting wires;
In described passivation layer, form opening, described opening is exposed to pad described in small part;
On described passivation layer and on exposure pad in the opening, form metal level, and form soldered ball on described metal level.
Alternatively, described adhesion auxiliary layer is silicon dioxide layer.
Alternatively, the thickness of described adhesion auxiliary layer is
Alternatively, the formation process of described adhesion auxiliary layer is PECVD.
Alternatively, the formation process of described adhesion auxiliary layer comprises: the air pressure of adjustment reaction cavity is 2 ~ 4torr, and temperature is 170 ~ 200 DEG C, in reaction cavity, pass into SiH
4and NO
2, wherein, the flow of described SiH4 is 60 ~ 100sccm, NO
2flow be 6000 ~ 10000sccm.
Alternatively, the thickness of described isolation layer is
Alternatively, the formation process of described isolation layer is PECVD.
Wafer-level packaging method as claimed in claim 7, alternatively, the formation process of described isolation layer comprises: the air pressure of adjustment reaction cavity is 3 ~ 4torr, and temperature is 170 ~ 200 DEG C, in reaction cavity, pass into TEOS and O
2or TEOS and O
3, the flow of described TEOS is 1000 ~ 1500sccm, O
2or O
3flow be 2500 ~ 3200sccm.
Alternatively, in described reaction cavity, pass into diluent gas, described diluent gas is inert gas, and flow is 1900 ~ 2300sccm simultaneously.
Alternatively, described diluent gas is He.
Compared with prior art, technical scheme of the present invention has the following advantages:
At the first surface of semiconductor crystal wafer, and bottom in the groove of first surface and sidewall are formed after one deck adheres to auxiliary layer, described adhesion auxiliary layer forms described isolation layer, afterwards along isolation layer described in described recess etch and adhesion auxiliary layer, remove the isolation layer of described bottom portion of groove and adhere to auxiliary layer, exposing described semiconductor crystal wafer; At the sidewall of described isolation layer, described groove, and the exposed semiconductor crystal wafer of described bottom portion of groove forms metal interconnecting wires layer; Afterwards, described metal interconnecting wires layer forms the structures such as pad, passivation layer, soldered ball, completes wafer-level packaging.The adhesion auxiliary layer that technique scheme is formed between described isolation layer and semiconductor crystal wafer effectively can improve the bond strength of described isolation layer and semiconductor crystal wafer, thus the stability of the semiconductor device formed after having improved wafer level packaging.
In further possibility, described adhesion auxiliary layer is with SiH
4and NO
2for presoma, adopt pecvd process to form silicon dioxide layer on the sidewall and bottom of the groove of described semiconductor wafer surface and semiconductor crystal wafer figure, with TEOS be presoma afterwards again and and O
2or O
3reaction, continues with pecvd process the isolation layer forming layer of silicon dioxide on described silicon dioxide layer.In technique scheme, SiH
4first be deposited on semiconductor crystal wafer in chemisorbed mode, afterwards and NO
2reaction forms silicon dioxide layer, and technique scheme can effectively increase the bond strength of silicon dioxide layer and semiconductor crystal wafer, afterwards with TEOS and O
2(or O
3) continued growth silicon dioxide layer on silicon dioxide layer, effectively can increase the thickness of the final silicon dioxide layer formed.In technique scheme, the silicon dioxide layer adhering to auxiliary layer and follow-up formation is integral, as separator, described isolation layer effectively enhances the bond strength of separator and semiconductor crystal wafer while effectively can completely cutting off semiconductor crystal wafer and follow-up conductive structure above described semiconductor crystal wafer.
Accompanying drawing explanation
Fig. 1 is in existing wafer-level packaging process, the schematic diagram of semiconductor package;
Fig. 2 is in the bonding strength test process of semiconductor package in Fig. 1, the test structure schematic diagram of isolation layer and semiconductor die rounded edge;
Fig. 3 is in the bonding strength test process of semiconductor package in Fig. 1, the test structure schematic diagram of isolation layer and semiconductor crystal wafer zone line;
The structural representation of the wafer-level packaging method that Fig. 4 to Fig. 9 provides for the embodiment of the present invention;
The isolation layer of semiconductor package that the wafer-level packaging method that Figure 10 provides for the employing embodiment of the present invention is formed and the test structure schematic diagram of semiconductor die rounded edge;
The isolation layer of semiconductor package that the wafer-level packaging method that Figure 11 provides for the employing embodiment of the present invention is formed and the test structure schematic diagram of semiconductor crystal wafer zone line.
Embodiment
In existing wafer-level packaging method, need first to form one deck low temperature oxide layer as isolation layer at semiconductor wafer surface, come in order to semiconductor crystal wafer and the follow-up conductive structure formed at described semiconductor wafer surface are completely cut off.But find in actual manufacture process; the isolation layer adopting existing technique to be formed at described semiconductor wafer surface and the bond strength of semiconductor crystal wafer poor; often there will be the phenomenon that isolation layer departs from semiconductor crystal wafer, the stability of its semiconductor device formed after seriously reducing encapsulation.
For this reason, the invention provides a kind of wafer-level packaging method, before semiconductor wafer surface forms isolation layer, auxiliary layer is adhered to prior to upper formation one deck of semiconductor crystal wafer, isolation layer is formed afterwards on adhesion auxiliary layer, thus improve the bond strength of isolation layer and semiconductor crystal wafer, prevent isolation layer from being departed from by semiconductor wafer surface.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to the schematic diagram of a kind of wafer-level packaging method that figure 4 and Fig. 6 provides for the present embodiment.
Shown in figure 4, provide semiconductor crystal wafer 100.Described semiconductor crystal wafer 100 comprises first surface 101 and second surface 102.Described first surface 101 and second surface 102 position are oppositely arranged.
In the present embodiment, described first surface 101 is the active face of semiconductor crystal wafer 100, and second surface 102 is the back side of semiconductor crystal wafer 100.The second surface 102 of described semiconductor crystal wafer 100 adheres to substrate 120.
Described semiconductor crystal wafer 100 is Silicon Wafer.In described semiconductor crystal wafer 100, be formed with multiple chip unit (not shown), e.g., described chip unit can be image sensor chip unit etc.Have Cutting Road between each chip unit, each chip unit can form one single chip after encapsulation and cutting.
In the present embodiment, described substrate 120 is chosen as glass substrate.Described substrate 120 is fixedly connected with described semiconductor crystal wafer 100 by the adhesive 110 being coated on described second surface 102.
In the present embodiment, adhesive 100 adopts organic adhesion agent.Described organic adhesion agent has adhesion speed soon, does not affect bonded structure, readily removable except, cost is low and adhesive strength high.Particularly, described adhesive is chosen as epoxyn.
The first surface 101 of described semiconductor crystal wafer 100 offers groove 103, described groove 103 is corresponding with the device position in described semiconductor crystal wafer 100, follow-uply can form interconnection line in described groove 103, with the device in semiconductor crystal wafer described in conducting 100 and external devices.
Described groove 103 formation process comprises: first on described first surface 101, apply photoresist layer,
After the techniques such as exposure imaging form photoetching agent pattern on photoresist layer, with photoetching agent pattern for the first surface 101 of semiconductor crystal wafer described in mask etching 100 is to form described groove 103, remove described photoresist layer afterwards.These steps are art technology mature technology, do not repeat them here.
It should be noted that, in other embodiment of the present invention except the present embodiment, first surface 101 can be the back side of semiconductor crystal wafer 100, and second surface 102 can be the active face of wafer 100, now, wafer 100 level packaging methods is a kind of flip-chip (flip chip) method for packing.These simply change all in protection scope of the present invention.
Shown in figure 5, on the first surface 101 of described semiconductor crystal wafer 100, and the sidewall of described groove 103 and bottom are formed and adhere to auxiliary layer 130.
Described adhesion auxiliary layer 130 is chosen as low temperature oxide layer.In the present embodiment, described adhesion auxiliary layer 130 is chosen as silicon dioxide (SiO
2).Described adhesion auxiliary layer 130 forms method and is chosen as PECVD(Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method).Specifically comprise:
The air pressure of the reaction cavity of adjustment PECVD is 2 ~ 4torr, and it is 170 ~ 200 DEG C that temperature controls, in reaction cavity, pass into SiH
4and NO
2as reacting gas.Wherein, described SiH
4flow be 60 ~ 100sccm, NO
2flow be 6000 ~ 10000sccm.
In the present embodiment, described SiH
4after passing into reaction cavity, rapid adsorption on the first surface 101 of described semiconductor crystal wafer 100, afterwards and NO
2there is redox reaction, thus form solid-state SiO on described first surface 101
2layer.
In the present embodiment, the air pressure of described reaction cavity is about 3torr alternatively further, described SiH
4flow be about 800sccm, NO
2flow be about 8000sccm.The flow control of above-mentioned reacting gas, can effective control SiH
4and NO
2reaction rate, thus on the first surface 101 of described semiconductor crystal wafer 100, form the uniform SiO of a layer thickness
2layer.
In conjunction with reference to shown in figure 6, after the described adhesion auxiliary layer 130 of formation, then form one deck isolation layer 140 above described adhesion auxiliary layer 130.The material of described isolation layer 140 is chosen as low temperature oxide.
In the present embodiment, described low temperature oxide layer is chosen as silicon dioxide layer.
In the present embodiment, the adhesive 100 for bond described semiconductor crystal wafer 100 and substrate 120 adopts organic adhesion agent, and described adhesive heat resisting temperature is lower.In the present embodiment, described adhesion auxiliary layer 130 and isolation layer 140 material are low temperature oxide layer, thus when forming isolation layer, can effectively prevent adhesive 300 be heated too high and lose bonding effect.
In the present embodiment, the formation process of described isolation layer 140 is chosen as PECVD, comprises particularly:
The air pressure of reaction cavity of adjustment PECVD is 3 ~ 4torr(is about 3.5torr further alternatively) temperature controls to be 170 ~ 200 DEG C, passes into TEOS(tetraethoxysilane in reaction cavity) and O
2, or TEOS and O
3.Passing into TEOS and O in described reaction chamber
2(or O
3) after, described TEOS is at O
2(or O
3) effect generation decomposition reaction, thus one deck SiO is formed on the first surface 101 of described semiconductor crystal wafer 100
2layer.And the temperature in PECVD is less than 200 DEG C, adhesive 300 can be effectively prevented to be heated too high and to lose bonding effect.
In the present embodiment, the flow of described TEOS is that 1000 ~ 1500sccm(is chosen as about 1200sccm further) described O
2or O
3flow be that 2500 ~ 3200sccm(is chosen as about 2900sccm further).Above-mentioned reactant flow controls to form the uniform isolation layer 140 of thickness on described adhesion auxiliary layer 130.
Further alternatively, described TEOS and O is being passed into
2(or O
3) time, simultaneously can pass into inert gas in described reaction chamber, using as diluent gas.In the present embodiment, described inert gas is chosen as helium (He), and flow is chosen as 1900sccm ~ 2300sccm, is chosen as about 2100sccm further.The inert gas of above-mentioned flow control, can the reaction rate of effective control TEOS, to form the uniform SiO of thickness
2layer simultaneously, improves the fail safe of reaction system.
In the present embodiment, first with SiH
4on the first surface 101 of described semiconductor crystal wafer 100, one deck SiO is formed as presoma
2after layer, then TEOS is adopted to be that presoma is at established SiO
2continued growth one deck SiO on layer
2layer, two-layer SiO
2layer as an entirety as isolation layer.
In the present embodiment, the thickness of described adhesion auxiliary layer 130 is chosen as
the thickness of described isolation layer 140 is chosen as
described adhesion auxiliary layer, effectively can improve the isolation layer 140 of follow-up formation and the bonding strength of semiconductor crystal wafer 100.In the present embodiment, (be less than if described adhesion auxiliary layer 130 thickness is too small
), then can reduce its adhesion, if blocked up
the intensity that it connects isolation layer 140 and semiconductor crystal wafer 100 can be affected equally.(be less than if described isolation layer is excessively thin
) good insulating effect cannot be played, (be greater than if blocked up
) increase process costs simultaneously, increase the structure of the semiconductor device of follow-up formation.
Shown in figure 7, at the first surface 101 of described semiconductor crystal wafer 100, and after described isolation layer 140 is formed on the sidewall of groove 103 and bottom, adhesion auxiliary layer 130 bottom described groove 103 and isolation layer 140 is etched, until expose the semiconductor crystal wafer 100 bottom described groove 103 along described groove 103.
Shown in figure 8, on described isolation layer 140, and the sidewall of groove 103, and the surface of semiconductor crystal wafer 100 exposed bottom described groove 130 forms metal interconnecting wires layer 150, described metal interconnecting wires layer 150 is electrically connected with the device in described semiconductor crystal wafer 100.
In the present embodiment, the material of described metal interconnecting wires layer 150 is chosen as Al.Its formation process can be PVD(physical vaporous deposition).
Shown in figure 9, described metal interconnecting wires layer 150 forms pad 160, described metal interconnecting wires layer 150 is electrically connected with described pad 160, forms passivation layer 170 afterwards on described metal interconnecting wires layer 150 and described pad 160; Etch described passivation layer 170, opening (not indicating in figure) is formed in described passivation layer 170, described opening is exposed to pad 160 described in small part, afterwards, described passivation layer 170 and exposure pad 160 in the opening form metal level 180, and form soldered ball 190 on described metal level 180.
In the present embodiment, the material of described pad 610 can comprise one or more the combination in any in aluminium, copper, silver, gold, nickel, tungsten.The material of passivation layer 170 both can be the organic materials such as epoxy resin (Epoxy), polyimides (PI), benzocyclobutene, polyphenyl oxazole, also can be the inorganic material such as silicon nitride, silicon oxynitride or silica.Metal level 180 can include the sandwich constructions such as diffusion layer, barrier layer, wetting layer and anti oxidation layer.The material of soldered ball 190 can be one or more the combination in any in the metals such as tin, Xi Yin, tin lead, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony, and can include activating agent in soldered ball 190, soldered ball 190 is formed by electroplating technology and reflow soldering process.
Figure 10 and Figure 11 for after form isolation layer 140 on described semiconductor crystal wafer 100, in the bonding strength test of described semiconductor crystal wafer 100 and isolation layer 140, the syndeton schematic diagram of described semiconductor crystal wafer 100 and isolation layer 140.
Fine powder 15 in Figure 10 and the fine powder in Figure 11 16 are after applying pressure to semiconductor package, the powder formed after pulverizing described semiconductor crystal wafer 100.
Wherein, Figure 10 is the structural representation of the test result of isolation layer (comprising the entirety of described adhesion auxiliary layer 130 and isolation layer 140 formation) and semiconductor crystal wafer frontside edge.
With reference to shown in Figure 10, C point is applied voltage test starting point, after applied voltage test a period of time, even if cracked situation (pressure is excessive) appears in semiconductor crystal wafer 100, does not also occur the situation that significantly ftractures between described isolation layer and semiconductor crystal wafer 100.The connection state of described isolation layer and semiconductor crystal wafer 100 is good.
Figure 11 is the structural representation of the test result of isolation layer and semiconductor crystal wafer 100 zone line.
With reference to shown in Figure 11, D point is applied voltage test starting point, after applied voltage test a period of time, even if cracked situation (pressure is excessive) appears in semiconductor crystal wafer 100, does not also occur the situation that significantly ftractures between described isolation layer and semiconductor crystal wafer 100.The connection state of described isolation layer and semiconductor crystal wafer 100 is good.
Shown in Figure 10 and Figure 11, described isolation layer and each position of semiconductor crystal wafer 100 all there is good syndeton.Analyzing its reason may be:
If be that presoma forms SiO on a semiconductor wafer with TEOS
2in the technical scheme of layer, described TEOS is deposited on institute's semiconductor crystal wafer and forms SiO after decomposing
2layer, it is equivalent to physisorption, and absorption affinity is more weak.In the present embodiment, with SiH
4as presoma, be chemisorbed on the surface of semiconductor crystal wafer, afterwards again with NO
2reaction forms SiO
2layer, it can effectively strengthen formed SiO
2layer and the bonding strength of semiconductor crystal wafer.But, in practical operation, adopt SiH
4sidewall as the groove 103 of presoma in described semiconductor crystal wafer 100 only can form thin layer SiO
2layer, is difficult to form thicker SiO
2layer.If single with SiH
4as the SiO that presoma cannot meet the demands at the sidewall formation thickness of groove 103
2layer.During isolation layer bottom the described groove 103 of follow-up etching prepared by semiconductor, adopt SiH
4the thinner SiO formed
2layer is easily consumed totally.Thus with SiH
4for presoma forms the SiO of layer
2after layer, then be that presoma is at established SiO with TEOS
2layer continues form one deck SiO
2layer, two-layer SiO
2the bonding strength of layer is high, and both shapes are in aggregates as isolation layer, to guarantee the thickness of the isolation layer formed.In the present embodiment, two-layer SiO
2the isolation layer that layer is integrated, while guaranteeing isolation layer effect, effectively increases the bonding strength of isolation layer and semiconductor crystal wafer 100.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a wafer-level packaging method, is characterized in that, comprising:
There is provided semiconductor crystal wafer, described semiconductor crystal wafer comprises first surface and second surface, and described first surface is relative with second surface position;
The second surface of described semiconductor crystal wafer is adhered to substrate;
Groove is formed at the first surface of described semiconductor crystal wafer;
At the first surface of described semiconductor crystal wafer, and the bottom of described groove and sidewall are formed and adhere to auxiliary layer;
Described adhesion auxiliary layer forms isolation layer;
Along isolation layer described in described recess etch and adhesion auxiliary layer, remove the isolation layer of described bottom portion of groove and adhere to auxiliary layer, exposing described semiconductor crystal wafer;
At the sidewall of described isolation layer, described groove, and the exposed semiconductor crystal wafer of described bottom portion of groove forms metal interconnecting wires layer;
Described metal interconnecting wires layer forms pad, and described metal interconnecting wires layer is electrically connected with described pad;
Passivation layer is formed layer by layer with on described pad at described metal interconnecting wires;
In described passivation layer, form opening, described opening is exposed to pad described in small part;
On described passivation layer and on exposure pad in the opening, form metal level, and form soldered ball on described metal level.
2. wafer-level packaging method as claimed in claim 1, it is characterized in that, described adhesion auxiliary layer is silicon dioxide layer.
3. wafer-level packaging method as claimed in claim 1, it is characterized in that, the thickness of described adhesion auxiliary layer is
4. wafer-level packaging method as claimed in claim 1, it is characterized in that, the formation process of described adhesion auxiliary layer is PECVD.
5. wafer-level packaging method as claimed in claim 4, it is characterized in that, the formation process of described adhesion auxiliary layer comprises: the air pressure of adjustment reaction cavity is 2 ~ 4torr, and temperature is 170 ~ 200 DEG C, in reaction cavity, pass into SiH
4and NO
2, wherein, described SiH
4flow be 60 ~ 100sccm, NO
2flow be 6000 ~ 10000sccm.
6. wafer-level packaging method as claimed in claim 1, it is characterized in that, the thickness of described isolation layer is
7. wafer-level packaging method as claimed in claim 1, it is characterized in that, the formation process of described isolation layer is PECVD.
8. wafer-level packaging method as claimed in claim 7, it is characterized in that, the formation process of described isolation layer comprises: the air pressure of adjustment reaction cavity is 3 ~ 4torr, and temperature is 170 ~ 200 DEG C, in reaction cavity, pass into TEOS and O
2or TEOS and O
3, the flow of described TEOS is 1000 ~ 1500sccm, O
2or O
3flow be 2500 ~ 3200sccm.
9. wafer-level packaging method as claimed in claim 8, is characterized in that, in described reaction cavity, pass into diluent gas, described diluent gas is inert gas, and flow is 1900 ~ 2300sccm simultaneously.
10. wafer-level packaging method as claimed in claim 9, it is characterized in that, described diluent gas is He.
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| WO2022068153A1 (en) * | 2020-09-30 | 2022-04-07 | 中国科学院微电子研究所 | Packaging method for semiconductor structure, packaging structure, and chip |
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| CN104716055B (en) | 2017-09-29 |
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