CN104183481A - Method for improving deposition quality of metal barrier layer - Google Patents
Method for improving deposition quality of metal barrier layer Download PDFInfo
- Publication number
- CN104183481A CN104183481A CN201410428647.4A CN201410428647A CN104183481A CN 104183481 A CN104183481 A CN 104183481A CN 201410428647 A CN201410428647 A CN 201410428647A CN 104183481 A CN104183481 A CN 104183481A
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- China
- Prior art keywords
- metal barrier
- semiconductor substrate
- barrier layer
- deposition
- deposition quality
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Abstract
The invention provides a method for improving the deposition quality of a metal barrier layer. The method comprises the steps that before dehumidification processing is conducted on the surface of a semiconductor substrate, preheating processing is conducted on the surface of the semiconductor substrate, and preheating processing enables the back face of the edge of the semiconductor substrate to generate stripping substances due to uneven heating; the stripping substances are removed through a scrubbing process, then a subsequent dehumidification process, a subsequent pre-cleaning process and a subsequent metal barrier layer depositing process are conducted, the defect that stripping happens after deposition of an existing metal barrier layer is overcome, the deposition quality of the metal barrier layer is improved, smooth conducting of the subsequent processes is facilitated, and the quality of the entire device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of method that improves metal barrier deposition quality.
Background technology
Along with development and the critical size of integrated circuit technology are scaled, some new technologies are constantly introduced into, and such as the metal barrier layer process in last part technology, refer to Fig. 1, for the schematic flow sheet of existing metal barrier deposition method, its key step comprises:
Step L01: high temperature is removed the moisture of semiconductor substrate surface; The temperature of removing moisture is higher, generally 350 DEG C of left and right.
Step L02: semiconductor substrate surface is carried out to precleaning;
Step L03: on semiconductor substrate surface plated metal barrier layer.
After above-mentioned metal barrier deposition, usually produce and peel off defect, reason is as follows: due to the complexity of last part technology, before plated metal barrier layer, inevitably will have the defects such as surface irregularity near the position at the back side in semiconductor substrate edge; The hot environment of the removal moisture of process above-mentioned steps L01, can cause the semiconductor substrate edge back side to occur the problem that thermal stress is inhomogeneous, thereby cause the semiconductor substrate edge back side to produce overburden, what overburden may drop on semiconductor substrate surface comprises functional areas Anywhere.
Conventionally solve the method for above-mentioned overburden defect, after metal barrier depositing operation completes, semiconductor substrate surface is scrubbed to technique, although scrub technique and can remove the defect of peeling off of semiconductor substrate surface, but, also removed part metals barrier layer, destroyed the completing property of metal barrier simultaneously.Because overburden is usually located at the functional areas of Semiconductor substrate, can be with the peeling off and remove of overburden so be covered in metal barrier on overburden, this may cause the metal barrier disappearance of functional areas; Metal barrier is very important for subsequent technique, and therefore, the method for studying this overburden removal is very important.
Separately have a kind of method, optimized by the etching technics that increases semiconductor substrate edge, but this method needs professional etching machine bench, and need to assess its impact on whole technique, expend a large amount of manpower and materials, therefore, neither optimized mode.
Summary of the invention
In order to overcome above problem, the present invention aims to provide a kind of method that improves metal barrier deposition quality, thereby before plated metal barrier layer, the overburden of semiconductor substrate surface is removed, and avoids metal barrier deposition to produce and peel off defect afterwards.
The invention provides a kind of method that improves metal barrier deposition quality, it comprises:
Step 01: provide a surface to there is the Semiconductor substrate of dielectric layer;
Step 02: described Semiconductor substrate is carried out to the pre-heat treatment;
Step 03: described semiconductor substrate surface is scrubbed to technique;
Step 04; Remove the moisture of described semiconductor substrate surface and carry out precleaning process;
Step 05: plated metal barrier layer in described Semiconductor substrate.
Preferably, in described step 01, comprising: the formation of described dielectric layer comprises deposition-etch barrier layer and metallic spacer in Semiconductor substrate successively; Described step 05 comprises: at described metallic spacer surface deposition metal barrier.
Preferably, in described step 02, the temperature that described the pre-heat treatment adopts is 350-450 DEG C.
Preferably, in described step 02, described the pre-heat treatment is carried out under vacuum environment, and the time adopting is greater than 3 seconds.
Preferably, in described step 03, described in carrying out, employing water scrubs technique.
A kind of method that improves metal barrier deposition quality of the present invention, by before semiconductor substrate surface is carried out to dehumidification treatments, first it is carried out to the pre-heat treatment, the pre-heat treatment can cause the semiconductor substrate edge back side due to the inhomogeneous overburden that produces that is heated.Through scrubbing technique, overburden is removed again, and then carry out follow-up dehumidification process, pre-clean process and metal barrier depositing operation, thereby after having avoided existing metal barrier deposition, defect is peeled off in generation, improve metal barrier deposition quality, be conducive to the quality of carrying out and improve smoothly whole device of subsequent technique.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of existing metal barrier deposition method
Fig. 2 is the schematic flow sheet of the method for the raising metal barrier deposition quality of a preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
As previously mentioned, due to the complexity of last part technology, before metal barrier deposition, the back side in semiconductor substrate edge there will be the problems such as out-of-flatness, adopt existing metal barrier depositing operation, can experience the process of removing moisture, the process need hot environment of this removal moisture, can cause the semiconductor substrate edge back side to occur the problem that thermal stress is inhomogeneous, thereby cause semiconductor substrate surface to produce overburden.Once overburden drops on the functional areas of Semiconductor substrate, metal barrier is deposited thereon, follow-up scrubbing after technique, the metal barrier of functional areas can be removed, thereby affect carrying out smoothly and the performance of whole device of subsequent technique, even cause scrapping of device.Thus, the present invention proposes a kind of method that improves metal barrier deposition quality, by before semiconductor substrate surface is carried out to dehumidification treatments, first it is carried out to the pre-heat treatment, the pre-heat treatment can cause the semiconductor substrate edge back side due to the inhomogeneous overburden that produces that is heated.Through scrubbing technique, overburden is removed again, and then carried out follow-up dehumidification process, pre-clean process and metal barrier depositing operation, thereby after having avoided existing metal barrier deposition, defect is peeled off in generation.
Below with reference to accompanying drawing 2 and specific embodiment, the method for raising metal barrier deposition quality of the present invention is described in further detail.It should be noted that, accompanying drawing all adopts very the form simplified, uses non-ratio accurately, and only in order to object convenient, that clearly reach aid illustration the present embodiment.
Referring to Fig. 2, is the schematic flow sheet of the method for the raising metal barrier deposition quality of a preferred embodiment of the present invention, and the method for the raising metal barrier deposition quality of the present embodiment, comprising:
Step 01: provide a surface to there is the Semiconductor substrate of dielectric layer;
Concrete, the formation of the dielectric layer of semiconductor substrate surface can comprise deposition-etch barrier layer and metallic spacer in Semiconductor substrate successively, this is not used in and limits the scope of the invention; In the present invention, dielectric layer can comprise multilayer, such as, under metallic spacer, can also include teos layer (TEOS).Semiconductor substrate can be any substrate in last part technology, such as, in the Semiconductor substrate below dielectric layer, there is contact hole structure or metal interconnect structure etc.
Step 02: Semiconductor substrate is carried out to the pre-heat treatment;
Concrete, the concrete technology parameter of the pre-heat treatment can be, but not limited to comprise: under vacuum environment, and inert atmosphere, temperature is 350-450 DEG C, the time of employing is greater than 3 seconds.Inert atmosphere can adopt nitrogen or argon gas etc.
Herein, carry out the pre-heat treatment, can make Semiconductor substrate be in certain hot environment, produce overburden thereby the thermal stress that causes the semiconductor substrate edge back side is inhomogeneous, like this, through the pre-heat treatment, the overburden at the semiconductor substrate edge back side is just peeled off out from Semiconductor substrate, scrubs so that follow-up.
Step 03: semiconductor substrate surface is scrubbed to technique;
Concrete, the cleaning fluid of scrubbing process using can be water.Such as deionized water, ultra-pure water etc., to avoid that semiconductor substrate surface is caused to corrosion.Scrub technique and also can adopt the existing method of scrubbing, the present invention does not repeat them here.
As can be seen here, thinking of the present invention is in brief: first utilize high temperature and the process of scrubbing that overburden is removed, then plated metal barrier layer.
Step 04; Remove the moisture of semiconductor substrate surface and carry out precleaning process;
Concrete, this step 04 can adopt conventional removal moisture and the process of precleaning, and the present invention is not restricted this.
Step 05: plated metal barrier layer in Semiconductor substrate.
Concrete, because the outermost dielectric layer of semiconductor substrate surface in the present embodiment is metallic spacer, therefore, at metallic spacer surface deposition metal barrier, the deposition process of metal barrier can be, but not limited to adopt physical vaporous deposition.
It should be noted that, after step 03, can also comprise other step in existing metal barrier depositing operation, the present invention is not restricted this.
In sum, the present invention can effectively avoid the defect of peeling off defect producing after existing metal barrier deposition, has improved metal barrier deposition quality, and what be conducive to subsequent technique carries out and improve the quality of whole device smoothly.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (5)
1. a method that improves metal barrier deposition quality, is characterized in that, comprising:
Step 01: provide a surface to there is the Semiconductor substrate of dielectric layer;
Step 02: described Semiconductor substrate is carried out to the pre-heat treatment;
Step 03: described semiconductor substrate surface is scrubbed to technique;
Step 04; Remove the moisture of described semiconductor substrate surface and carry out precleaning process;
Step 05: plated metal barrier layer in described Semiconductor substrate.
2. the method for raising metal barrier deposition quality according to claim 1, is characterized in that, in described step 01, comprising: the formation of described dielectric layer comprises deposition-etch barrier layer and metallic spacer in Semiconductor substrate successively; Described step 05 comprises: at described metallic spacer surface deposition metal barrier.
3. the method for raising metal barrier deposition quality according to claim 1, is characterized in that, in described step 02, the temperature that described the pre-heat treatment adopts is 350-450 DEG C.
4. the method for raising metal barrier deposition quality according to claim 1, is characterized in that, in described step 02, described the pre-heat treatment is carried out under vacuum environment, and the time adopting is greater than 3 seconds.
5. the method for raising metal barrier deposition quality according to claim 1, is characterized in that, in described step 03, described in employing water carries out, scrubs technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410428647.4A CN104183481B (en) | 2014-08-27 | 2014-08-27 | Method for improving deposition quality of metal barrier layer |
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| CN201410428647.4A CN104183481B (en) | 2014-08-27 | 2014-08-27 | Method for improving deposition quality of metal barrier layer |
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| CN104183481A true CN104183481A (en) | 2014-12-03 |
| CN104183481B CN104183481B (en) | 2019-12-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110459479A (en) * | 2018-05-07 | 2019-11-15 | 北京北方华创微电子装备有限公司 | Barrier deposition method, underlying metal film of golden convex block and preparation method thereof |
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| US20050101157A1 (en) * | 2003-11-10 | 2005-05-12 | Semiconductor Leading Edge Technologies, Inc. | Method for manufacturing semiconductor device |
| CN1674215A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Method for producing blocking-layer |
| CN1992221A (en) * | 2005-12-28 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating complementary metal oxide silicon image sensor |
| KR100875819B1 (en) * | 2007-09-20 | 2008-12-26 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
| CN101728229A (en) * | 2008-10-31 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal pad |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030054625A1 (en) * | 2001-09-20 | 2003-03-20 | Volker Kahlert | Metallization process sequence |
| US20050101157A1 (en) * | 2003-11-10 | 2005-05-12 | Semiconductor Leading Edge Technologies, Inc. | Method for manufacturing semiconductor device |
| CN1674215A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Method for producing blocking-layer |
| CN1992221A (en) * | 2005-12-28 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating complementary metal oxide silicon image sensor |
| KR100875819B1 (en) * | 2007-09-20 | 2008-12-26 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
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| CN110459479A (en) * | 2018-05-07 | 2019-11-15 | 北京北方华创微电子装备有限公司 | Barrier deposition method, underlying metal film of golden convex block and preparation method thereof |
| CN110459479B (en) * | 2018-05-07 | 2021-07-13 | 北京北方华创微电子装备有限公司 | Barrier layer deposition method, bottom metal film of gold bump and preparation method thereof |
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| CN104183481B (en) | 2019-12-13 |
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Effective date of registration: 20200414 Address after: 201203 1060, room 1, 298 Cambridge East Road, Pudong New Area, Shanghai. Patentee after: SHANGHAI HUALI INTEGRATED CIRCUIT MANUFACTURING Co.,Ltd. Address before: 201210, Gauss road 568, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: Shanghai Huali Microelectronics Corp. |