CN103779275A - CMOS manufacturing method - Google Patents

CMOS manufacturing method Download PDF

Info

Publication number
CN103779275A
CN103779275A CN201210395537.3A CN201210395537A CN103779275A CN 103779275 A CN103779275 A CN 103779275A CN 201210395537 A CN201210395537 A CN 201210395537A CN 103779275 A CN103779275 A CN 103779275A
Authority
CN
China
Prior art keywords
source
substrate
lifting district
pmos region
lifting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201210395537.3A
Other languages
Chinese (zh)
Inventor
殷华湘
闫江
陈大鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210395537.3A priority Critical patent/CN103779275A/en
Publication of CN103779275A publication Critical patent/CN103779275A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a CMOS manufacturing method, which comprises the following steps: forming a grid stacking structure in an NMOS area and a PMOS area on a substrate; forming a grid side wall around the grid stacking structure; forming a first source drain lifting area in an NMOS area and a PMOS area on a substrate; selectively etching the substrate of the PMOS region, and forming source drain grooves on two sides of the grid side wall; and forming a second source drain raised region in the source drain groove. According to the CMOS manufacturing method, the NMOS raised source and drain are epitaxially grown globally selectively, and then the PMOS raised source and drain are selectively etched and epitaxially grown, so that the process steps are reduced, the cost is reduced, and the reliability of the device is improved.

Description

CMOS manufacture method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to the integrated approach of a kind of cmos device source leakage selective epitaxial.
Background technology
From 90nm CMOS integrated circuit technology, along with constantly dwindling of device feature size, play more and more important effect to improve channel carrier mobility as object stressed channels engineering (Strain ChannelEngineering).Multiple single shaft technique is led to stress to be integrated in device technology and is gone, thereby also introduces compression or tension stress enhancing carrier mobility at channel direction, improves device performance.For example, in 90nm technique, adopt embedded S iGe (e-SiGe) source Lou Huo100 crystal orientation substrate and provide the compression in pMOS device in conjunction with tension stress etch barrier (tCESL); In 65nm technique, on 90nm technique basis, further adopt first generation source-drain electrode stress memory technique (SMT × 1), and adopted two etch barrier; In 45nm technique, on basis, adopting second generation source-drain electrode stress memory technique (SMT before × 2), adopt e-SiGe technology in conjunction with single tCESL or two CESL, and adopted stress closely to face technology (Stress Proximity Technique, SPT), adopt 110 substrates and adopt 100 substrates for nMOS for pMOS in addition; After 32nm, adopt third generation source-drain electrode stress memory technique (SMT × 3), also having selected embedded SiC source to leak to strengthen the tension stress in nMOS device on basis before.
On the other hand, in the following technique of 32nm, source-drain contact resistance proportion in the resistance of whole device is increasing, has seriously restricted device performance raising.In order to reduce source-drain contact resistance, the method for conventionally taking is the source-drain area that epitaxial growth forms lifting on source-drain area, or forms metal silicide at contact area.Specifically be applied on the basis of aforesaid stresses channel engineering, not only will leak selective epitaxial SiGe for the source in PMOS district, also will leak selective epitaxial Si or Si:C for the source of nmos area.The manufacture method of the equal extension lifting of this NMOS, PMOS is normally utilized mask or block layer; the lifting source that first a kind of MOSFET region etching formation source therein leakage groove selective epitaxial form a kind of material leaks; deposit subsequently the second mask or block layer, then leak the lifting source that groove selective epitaxial form another kind of material in etching formation source, another kind of MOSFET region and leak.This kind of manufacture method utilized twice mask etching, extension respectively, the complex procedures needing, and cost is higher, consuming time more, and easily brings integrity problem.
Summary of the invention
From the above mentioned, the object of the present invention is to provide the CMOS manufacture method of a kind of energy low cost, the selective epitaxial of source leakage efficiently.
For this reason, the invention provides a kind of CMOS manufacture method, comprising: territory, nmos area and PMOS region form gate stack structure on substrate; Around gate stack structure, form grid curb wall; On substrate, territory, nmos area and PMOS region form the first Yuan Lou lifting district; Selective etch PMOS region substrate, leaks groove in formation source, grid curb wall both sides; Leak in groove and form the second Yuan Lou lifting district in source.
Wherein, gate stack structure is false grid stacked structure, comprises pad oxide and false grid material layer, and false grid material layer comprises polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
Wherein, selective epitaxial growth is to form the first Yuan Lou lifting district and/or the second Yuan Lou lifting district.
Wherein, the step of selective etch PMOS region substrate further comprises: form protective layer, cover the first Yuan Lou lifting district in territory, nmos area, and expose PMOS region; The first Yuan Lou lifting district and substrate that etching PMOS region exposes, groove is leaked in formation source.
Wherein, source is leaked the profile morphology of groove and is comprised rectangle, trapezoidal, inverted trapezoidal, Σ shape, D shape, C shape and combination thereof.
Wherein, form the second Yuan Lou lifting district and also comprise formation cap rock afterwards.
Wherein, the first Yuan Lou lifting district comprises Si, Si:C.
Wherein, the second Yuan Lou lifting district comprises SiGe, SiGe:C.
Wherein, cap rock comprises Si.
Wherein, protective layer comprises silicon nitride, silica and combination thereof.
According to CMOS manufacture method of the present invention, first overall selective epitaxial growth NMOS lifting source leaks, and rear selective etch, epitaxial growth PMOS lifting source leak, and have reduced processing step, have reduced cost, have improved the reliability of device.
Accompanying drawing explanation
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 5 is the generalized section according to the each step of CMOS manufacture method of the present invention; And
Fig. 6 is the indicative flowchart according to CMOS manufacture method of the present invention.
Embodiment
Referring to accompanying drawing and describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment, disclosing can low cost, the CMOS manufacture method of selective epitaxial is leaked in source efficiently.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
Describe in detail according to the each step of method, semi-conductor device manufacturing method of the present invention below with reference to the flow chart of Fig. 6 and referring to figs. 1 through the generalized section of Fig. 5.
As shown in Figure 1, on substrate, form (vacation) gate stack structure.Substrate 1 is provided.Substrate 1 needs and choose reasonable according to device purposes, can comprise monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (StrainedSi), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.Preferably, substrate 1 for body Si or SOI so that with CMOS process compatible for making large scale integrated circuit.
In substrate 1, form shallow trench isolation from (STI) 2, such as first photoetching/etched substrate 1 forms shallow trench and then adopts the routine techniques such as LPCVD, PECVD deposition insulation isolated material cmp planarization until expose substrate 1, form STI2, wherein the packing material of STI2 can be the conventional insulating material such as oxide, nitride, nitrogen oxide, can also be Bi 0.95la 0.05niO 3, BiNiO 3, ZrW 2o 8, Ag 3[Co (CN) 6] etc. there is the material of super large (positive/negative) thermal coefficient of expansion (absolute value of the temperature lower linear coefficient of cubical expansion of 100K be greater than 10 -4/ K) thus to further improve carrier mobility by stress STI2 to channel region stress application.The region that STI2 surrounds forms active region, and wherein in Fig. 1, left field is corresponding to territory, nmos area, and right side area is corresponding to PMOS region.Although territory, nmos area and PMOS region are only one and adjacent in Fig. 1, in fact need according to layout design, two kinds of MOSFET regions can be multiple, also can be non-conterminous.
Also be that substrate 1 and STI2 surface deposit gate insulator 3 and gate material layers 4 successively in whole wafer surface, and etching form the gate stack structure (3/4) that is positioned at active region.In one embodiment of the invention, grid technique after adopting, therefore gate stack structure is false grid stacked structure, will in subsequent technique, remove.Therefore gate insulator 3 is preferably the bed course of silica; Gate material layers 4 is false grid material layers, is preferably polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
It should be noted that in addition, in other embodiments of the invention, can adopt front grid technique, gate stack structure will retain in subsequent technique.Therefore gate insulator 3 is preferably silica, nitrating silica, silicon nitride or other hafnium, and high k material includes but not limited to comprise and is selected from HfO 2, HfS iO x, HfS iON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is according to multi-element metal component proportion and chemical valence difference, and oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material; 4 of gate material layers can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be doped with elements such as C, F, N, O, B, P, As with regulatory work function in gate material layers 4.The barrier layer (not shown) that also preferably forms nitride between gate material layers 4 and gate insulator 3 by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.More preferably, gate material layers 4 not only adopts upper and lower stacked lamination layer structure with barrier layer, can also adopt the dopant implant layer structure mixing, also form gate material layers 4 and be deposited on gate insulator 3 with the material on barrier layer simultaneously, therefore grid conducting layer comprises the material on above-mentioned barrier layer.
Preferably, on gate material layers 4, can also further form hard mask layer or the block layer (not shown) of the materials such as such as silicon nitride, to protect gate stack structure in subsequent etching process.Preferably, can, after forming gate stack structure, carry out Implantation as mask, make substrate respective regions there is light dope and form source and drain extension or leakage doped region, dizzy shape source (not shown).
As shown in Figure 2, on the substrate 1 around (vacation) gate stack structure 3/4, form grid curb wall 5.Adopt the conventional deposition process such as PECVD, HDPCVD, the insulating barrier of the material such as deposited silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC) on substrate 1, gate stack structure 3/4, photoetching subsequently/etching forms grid curb wall 5.Grid curb wall 5 is for limiting the position of source-drain area after a while.
As shown in Figure 3, on the active area of NMOS and PMOS, carry out overall selective epitaxial simultaneously, by method selective epitaxial growths such as CVD, UHVCVD, HDPCVD, MBE, ALD, thermal decompositions, on the substrate 1 of gate stack structure both sides, form the first lifting source drain region 1N, its material is for example Si or the Si:C that is applicable to NMOS.Preferably, can after simultaneously in-situ doped or epitaxial growth of epitaxial growth, carry out Implantation, formation heavy-doped source drain region (not shown), can Doping Phosphorus P, arsenic As for NMOS, antimony Sb etc.This lifting source drain region 1N can effectively reduce the source-drain contact resistance in territory, nmos area, can, to NMOS channel region stress application, increase carrier mobility in addition.
As shown in Figure 4, selective etch, leaks groove in formation source, PMOS region.On whole device, deposition is for example the protective layer 6 of silicon nitride or silica and composite bed, and the part that etching is removed PMOS region is to expose the substrate in PMOS region, only leaves partial protection layer 6 in territory, nmos area to cover the first lifting source drain region 1N.Adopt subsequently TMAH wet etching or fluorine-based, chlorine-based gas dry plasma etch, leak groove 1T in formation source, PMOS region.The profile morphology that groove 1T is leaked in source can be rectangle, trapezoidal, inverted trapezoidal, (multistage broken line is connected Σ shape, recessed towards channel region, also be the width that the width at groove middle part is greater than top and/or bottom), D shape (1/2 curve, curve comprises circle, oval, hyperbola), C shape (be greater than 1/2 curve, curve comprises circle, oval, hyperbola).The degree of depth of source leakage groove 1T is preferably less than thickness/degree of depth of STI2.
As shown in Figure 5, in leaking groove, the source in PMOS region forms the second lifting source drain region 1P.By method selective epitaxial growths such as PECVD, HDPCVD, MBE, ALD, thermal decompositions, in groove 1T is leaked in the source of the gate stack structure both sides in PMOS region, deposition is filled and is formed the second lifting source drain region 1P, and its material is SiGe, SiGe:C.Preferably, can after simultaneously in-situ doped or epitaxial growth of epitaxial growth, carry out Implantation, formation heavy-doped source drain region (not shown), doped with boron B, aluminium Al, gallium Ga, indium In etc. for PMOS.This lifting source drain region 1P can effectively reduce the source-drain contact resistance in PMOS region, can, to PMOS channel region stress application, increase carrier mobility in addition.Preferably, on the second lifting source drain region 1P, also further epitaxial growth has formed cap rock 7, and its material is for example Si.
After this, can carry out subsequent technique, for example deposit the interlayer dielectric layer (ILD of low-k materials, not shown), etching ILD forms drain contact hole, source until expose lifting source drain region 1N/1P, in drain contact hole, source, form metal silicide, plated metal is filled formation source drain contact plug, finally completes device manufacture.For rear grid technique, can be after forming ILD, remove the stacking formation gate trench of false grid, in gate trench, deposit the final gate stack structure that the gate insulator of high k material and the grid conducting layer of metal material form, and then carry out follow-up technique.
In addition,, although only shown the CMOS schematic diagram of planar channeling in accompanying drawing of the present invention, what those skilled in the art should know is that the present invention also can be applicable to other device architectures, such as three-dimensional multiple-grid, vertical-channel, nano-wire devices etc.
According to CMOS manufacture method of the present invention, first overall selective epitaxial growth NMOS lifting source leaks, and rear selective etch, epitaxial growth PMOS lifting source leak, and have reduced processing step, have reduced cost, have improved the reliability of device.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the modification of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (10)

1. a CMOS manufacture method, comprising:
On substrate, territory, nmos area and PMOS region form gate stack structure;
Around gate stack structure, form grid curb wall;
On substrate, territory, nmos area and PMOS region form the first Yuan Lou lifting district;
Selective etch PMOS region substrate, leaks groove in formation source, grid curb wall both sides;
Leak in groove and form the second Yuan Lou lifting district in source.
2. method as claimed in claim 1, wherein, gate stack structure is false grid stacked structure, comprises pad oxide and false grid material layer, false grid material layer comprises polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
3. method as claimed in claim 1, wherein, selective epitaxial growth is to form the first Yuan Lou lifting district and/or the second Yuan Lou lifting district.
4. method as claimed in claim 1, wherein, the step of selective etch PMOS region substrate further comprises:
Form protective layer, cover the first Yuan Lou lifting district in territory, nmos area, and expose PMOS region;
The first Yuan Lou lifting district and substrate that etching PMOS region exposes, groove is leaked in formation source.
5. method as claimed in claim 1, wherein, source is leaked the profile morphology of groove and is comprised rectangle, trapezoidal, inverted trapezoidal, Σ shape, D shape, C shape and combination thereof.
6. method as claimed in claim 1, wherein, forms the second Yuan Lou lifting district and also comprises formation cap rock afterwards.
7. method as claimed in claim 1, wherein, the first Yuan Lou lifting district comprises Si, Si:C.
8. method as claimed in claim 1, wherein, the second Yuan Lou lifting district comprises SiGe, SiGe:C.
9. method as claimed in claim 6, wherein, cap rock comprises Si.
10. method as claimed in claim 4, wherein, protective layer comprises silicon nitride, silica and combination thereof.
CN201210395537.3A 2012-10-17 2012-10-17 CMOS manufacturing method Pending CN103779275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210395537.3A CN103779275A (en) 2012-10-17 2012-10-17 CMOS manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210395537.3A CN103779275A (en) 2012-10-17 2012-10-17 CMOS manufacturing method

Publications (1)

Publication Number Publication Date
CN103779275A true CN103779275A (en) 2014-05-07

Family

ID=50571380

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210395537.3A Pending CN103779275A (en) 2012-10-17 2012-10-17 CMOS manufacturing method

Country Status (1)

Country Link
CN (1) CN103779275A (en)

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030059995A1 (en) * 2001-09-24 2003-03-27 Hsu Sheng Teng Deep sub-micron raised source/drain CMOS structure and method of making the same
US20060128105A1 (en) * 2003-10-31 2006-06-15 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
CN101170079A (en) * 2006-10-27 2008-04-30 台湾积体电路制造股份有限公司 Semiconductor structure forming method
US20080217686A1 (en) * 2007-03-09 2008-09-11 International Business Machines Corporation Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension
CN101304043A (en) * 2007-05-07 2008-11-12 台湾积体电路制造股份有限公司 Semiconductor structure
US20090283852A1 (en) * 2008-05-19 2009-11-19 Alois Gutmann Stress-Inducing Structures, Methods, and Materials
CN101661957A (en) * 2008-08-26 2010-03-03 台湾积体电路制造股份有限公司 Structure and method for a cmos device with doped conducting metal oxide as the gate electrode
US20100123197A1 (en) * 2008-11-17 2010-05-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102024813A (en) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 Semiconductor device, complementary oxide semiconductor device and integrated circuit
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
US20110201164A1 (en) * 2010-02-12 2011-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Dual EPI Process For Semiconductor Device
CN102214608A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN102299077A (en) * 2010-06-28 2011-12-28 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030059995A1 (en) * 2001-09-24 2003-03-27 Hsu Sheng Teng Deep sub-micron raised source/drain CMOS structure and method of making the same
US20060128105A1 (en) * 2003-10-31 2006-06-15 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
CN101170079A (en) * 2006-10-27 2008-04-30 台湾积体电路制造股份有限公司 Semiconductor structure forming method
US20080217686A1 (en) * 2007-03-09 2008-09-11 International Business Machines Corporation Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension
CN101304043A (en) * 2007-05-07 2008-11-12 台湾积体电路制造股份有限公司 Semiconductor structure
US20090283852A1 (en) * 2008-05-19 2009-11-19 Alois Gutmann Stress-Inducing Structures, Methods, and Materials
CN101661957A (en) * 2008-08-26 2010-03-03 台湾积体电路制造股份有限公司 Structure and method for a cmos device with doped conducting metal oxide as the gate electrode
US20100123197A1 (en) * 2008-11-17 2010-05-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102024813A (en) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 Semiconductor device, complementary oxide semiconductor device and integrated circuit
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
US20110201164A1 (en) * 2010-02-12 2011-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Dual EPI Process For Semiconductor Device
CN102214608A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN102299077A (en) * 2010-06-28 2011-12-28 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
CN103227202B (en) FinFET body contact and manufacture method thereof
US9196613B2 (en) Stress inducing contact metal in FinFET CMOS
US9892912B2 (en) Method of manufacturing stacked nanowire MOS transistor
CN104934474B (en) Combine FinFET and forming method thereof
US8652891B1 (en) Semiconductor device and method of manufacturing the same
CN103311185B (en) Method of hybrid high-k/metal-gate stack fabrication
US9548387B2 (en) Semiconductor device and method of manufacturing the same
US20200091343A1 (en) Dopant Concentration Boost in Epitaxially Formed Material
CN103311281A (en) Semiconductor device and method for manufacturing the same
CN110299358A (en) Semiconductor devices and its manufacturing method including fin FET
US10199392B2 (en) FinFET device having a partially dielectric isolated fin structure
CN103325684B (en) Semiconductor structure and manufacturing method thereof
CN103456782B (en) Semiconductor device and method for manufacturing the same
CN103066122A (en) MOSFET and manufacturing method thereof
CN103579314A (en) Semiconductor device and method for manufacturing the same
CN103325787B (en) CMOS device and method for fabricating the same
KR20160005858A (en) Field effect transistor and methods for manufacturing the same
CN103426907B (en) Semiconductor device and method for manufacturing the same
CN103367227B (en) Semiconductor device manufacturing method
CN104332399A (en) Semiconductor device manufacturing method
CN103367226A (en) Semiconductor device manufacturing method
CN108074870A (en) Transistor and forming method thereof
CN103779275A (en) CMOS manufacturing method
CN103779276A (en) CMOS manufacturing method
CN104124165A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140507