CN103779276A - CMOS manufacturing method - Google Patents

CMOS manufacturing method Download PDF

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Publication number
CN103779276A
CN103779276A CN201210395581.4A CN201210395581A CN103779276A CN 103779276 A CN103779276 A CN 103779276A CN 201210395581 A CN201210395581 A CN 201210395581A CN 103779276 A CN103779276 A CN 103779276A
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source
substrate
pmos region
pmos
groove
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殷华湘
闫江
陈大鹏
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210395581.4A priority Critical patent/CN103779276A/en
Priority to PCT/CN2012/001542 priority patent/WO2014059565A1/en
Publication of CN103779276A publication Critical patent/CN103779276A/en
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The invention discloses a CMOS manufacturing method. The method comprises the following steps: forming a grid stacked structure at an NMOS area and a PMOS area on a substrate; forming a grid side wall at the circumference of the grid stacked structure; selectively etching the substrate of the PMOS area, and forming a source-drain trench at the two sides of the grid side wall; forming a first source-drain uplifting area in the source-drain trench; and forming a covering layer at the NMOS area and the PMOS area on the substrate. According to the CMOS manufacturing method provided by the invention, firstly a PMOS uplifting source drain is selectively etched and grown in an epitaxial mode, and then an NMOS uplifting source drain is globally and selectively grown in an epitaxial mode so that the process procedures are reduced, the cost is lowered, and the device reliability is improved.

Description

CMOS manufacture method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to the integrated approach of a kind of cmos device source leakage selective epitaxial.
Background technology
From 90nm CMOS integrated circuit technology, along with constantly dwindling of device feature size, play more and more important effect to improve channel carrier mobility as object stressed channels engineering (Strain Channel Engineering).Multiple single shaft technique is led to stress to be integrated in device technology and is gone, thereby also introduces compression or tension stress enhancing carrier mobility at channel direction, improves device performance.For example, in 90nm technique, adopt embedded SiGe (e-SiGe) source Lou Huo100 crystal orientation substrate and provide the compression in pMOS device in conjunction with tension stress etch barrier (tCESL); In 65nm technique, on 90nm technique basis, further adopt first generation source-drain electrode stress memory technique (SMT × 1), and adopted two etch barrier; In 45nm technique, on basis, adopting second generation source-drain electrode stress memory technique (SMT before × 2), adopt e-SiGe technology in conjunction with single tCESL or two CESL, and adopted stress closely to face technology (Stress Proximity Technique, SPT), adopt 110 substrates and adopt 100 substrates for nMOS for pMOS in addition; After 32nm, adopt third generation source-drain electrode stress memory technique (SMT × 3), also having selected embedded SiC source to leak to strengthen the tension stress in nMOS device on basis before.
On the other hand, in the following technique of 32nm, source-drain contact resistance proportion in the resistance of whole device is increasing, has seriously restricted device performance raising.In order to reduce source-drain contact resistance, the method for conventionally taking is the source-drain area that epitaxial growth forms lifting on source-drain area, or forms metal silicide at contact area.Specifically be applied on the basis of aforesaid stresses channel engineering, not only will leak selective epitaxial SiGe for the source in PMOS district, also will leak selective epitaxial Si or Si:C for the source of nmos area.The manufacture method of the equal extension lifting of this NMOS, PMOS is normally utilized mask or block layer; the lifting source that first a kind of MOSFET region etching formation source therein leakage groove selective epitaxial form a kind of material leaks; deposit subsequently the second mask or block layer, then leak the lifting source that groove selective epitaxial form another kind of material in etching formation source, another kind of MOSFET region and leak.This kind of manufacture method utilized twice mask etching, extension respectively, the complex procedures needing, and cost is higher, consuming time more, and easily brings integrity problem.
Summary of the invention
From the above mentioned, the object of the present invention is to provide the CMOS manufacture method of a kind of energy low cost, the selective epitaxial of source leakage efficiently.
For this reason, the invention provides a kind of CMOS manufacture method, comprising: territory, nmos area and PMOS region form gate stack structure on substrate; Around gate stack structure, form grid curb wall; Selective etch PMOS region substrate, leaks groove in formation source, grid curb wall both sides; Leak in groove and form the first Yuan Lou lifting district in source; On substrate, territory, nmos area and PMOS region form cap rock.
Wherein, gate stack structure is false grid stacked structure, comprises pad oxide and false grid material layer, and false grid material layer comprises polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
Wherein, selective epitaxial growth is to form the first Yuan Lou lifting district and/or cap rock.
Wherein, the step of selective etch PMOS region substrate further comprises: on whole device, form protective layer; Selective etch protective layer, the substrate in exposure PMOS region; The substrate that etching PMOS region exposes, groove is leaked in formation source.
Wherein, source is leaked the profile morphology of groove and is comprised rectangle, trapezoidal, inverted trapezoidal, Σ shape, D shape, C shape and combination thereof.
Wherein, cap rock is also as the second Yuan Lou lifting district in territory, nmos area.
Wherein, cap rock comprises Si, Si:C.
Wherein, the first Yuan Lou lifting district comprises SiGe, SiGe:C.
Wherein, protective layer comprises silicon nitride, silica and combination thereof.
Wherein, form the first Yuan Lou lifting district and also comprise removal protective layer afterwards.
According to CMOS manufacture method of the present invention, first selective etch, epitaxial growth PMOS lifting source leak, and rear overall selective epitaxial growth NMOS lifting source leaks, and has reduced processing step, has reduced cost, has improved the reliability of device.
Accompanying drawing explanation
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 5 is the generalized section according to the each step of CMOS manufacture method of the present invention; And
Fig. 6 is the indicative flowchart according to CMOS manufacture method of the present invention.
Embodiment
Referring to accompanying drawing and describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment, disclosing can low cost, the CMOS manufacture method of selective epitaxial is leaked in source efficiently.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
Describe in detail according to the each step of method, semi-conductor device manufacturing method of the present invention below with reference to the flow chart of Fig. 6 and referring to figs. 1 through the generalized section of Fig. 5.
As shown in Figure 1, on substrate, form (vacation) gate stack structure.Substrate 1 is provided.Substrate 1 needs and choose reasonable according to device purposes, can comprise monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.Preferably, substrate 1 for body Si or SOI so that with CMOS process compatible for making large scale integrated circuit.
In substrate 1, form shallow trench isolation from (STI) 2, such as first photoetching/etched substrate 1 forms shallow trench and then adopts the routine techniques such as LPCVD, PECVD deposition insulation isolated material cmp planarization until expose substrate 1, form STI 2, wherein the packing material of STI 2 can be the conventional insulating material such as oxide, nitride, nitrogen oxide, can also be Bi 0.95la 0.05niO 3, BiNiO 3, ZrW 2o 8, Ag 3[Co (CN) 6] etc. there is the material of super large (positive/negative) thermal coefficient of expansion (absolute value of the temperature lower linear coefficient of cubical expansion of 100K be greater than 10 -4/ K) thus to further improve carrier mobility by stress STI 2 to channel region stress application.The region that STI 2 surrounds forms active region, and wherein in Fig. 1, left field is corresponding to territory, nmos area, and right side area is corresponding to PMOS region.Although territory, nmos area and PMOS region are only one and adjacent in Fig. 1, in fact need according to layout design, two kinds of MOSFET regions can be multiple, also can be non-conterminous.
Also be that substrate 1 and STI 2 surfaces deposit gate insulator 3 and gate material layers 4 successively in whole wafer surface, and etching form the gate stack structure (3/4) that is positioned at active region.In one embodiment of the invention, grid technique after adopting, therefore gate stack structure is false grid stacked structure, will in subsequent technique, remove.Therefore gate insulator 3 is preferably the bed course of silica; Gate material layers 4 is false grid material layers, is preferably polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
It should be noted that in addition, in other embodiments of the invention, can adopt front grid technique, gate stack structure will retain in subsequent technique.Therefore gate insulator 3 is preferably silica, nitrating silica, silicon nitride or other hafnium, and high k material includes but not limited to comprise and is selected from HfO 2, HfSiO x, HfSiON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is according to multi-element metal component proportion and chemical valence difference, and oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material; 4 of gate material layers can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be doped with elements such as C, F, N, O, B, P, As with regulatory work function in gate material layers 4.The barrier layer (not shown) that also preferably forms nitride between gate material layers 4 and gate insulator 3 by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.More preferably, gate material layers 4 not only adopts upper and lower stacked lamination layer structure with barrier layer, can also adopt the dopant implant layer structure mixing, also form gate material layers 4 and be deposited on gate insulator 3 with the material on barrier layer simultaneously, therefore grid conducting layer comprises the material on above-mentioned barrier layer.
Preferably, on gate material layers 4, can also further form hard mask layer or the block layer (not shown) of the materials such as such as silicon nitride, to protect gate stack structure in subsequent etching process.Preferably, can, after forming gate stack structure, carry out Implantation as mask, make substrate respective regions there is light dope and form source and drain extension or leakage doped region, dizzy shape source (not shown).
As shown in Figure 2, on the substrate 1 around (vacation) gate stack structure 3/4, form grid curb wall 5, and form protective layer 6 on whole device.Adopt the conventional deposition process such as PECVD, HDPCVD, the insulating barrier of the material such as deposited silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC) on substrate 1, gate stack structure 3/4, photoetching subsequently/etching forms grid curb wall 5.Grid curb wall 5 is for limiting the position of source-drain area after a while.By the method such as PECVD, HDPCVD, on whole device, the protective layer 6 of the material such as deposited silicon nitride, has covered substrate 1, gate stack structure in territory, nmos area and PMOS region.
As shown in Figure 3, selective etch, leaks groove in formation source, PMOS region.Etching is removed the partial protection layer 6 in PMOS region to expose the substrate in PMOS region, only leaves partial protection layer 6 in territory, nmos area.Adopt subsequently TMAH wet etching or fluorine-based, chlorine-based gas dry plasma etch, leak groove 1T in formation source, PMOS region.The profile morphology that groove 1T is leaked in source can be rectangle, trapezoidal, inverted trapezoidal, (multistage broken line is connected Σ shape, recessed towards channel region, also be the width that the width at groove middle part is greater than top and/or bottom), D shape (1/2 curve, curve comprises circle, oval, hyperbola), C shape (be greater than 1/2 curve, curve comprises circle, oval, hyperbola).The degree of depth of source leakage groove 1T is preferably less than thickness/degree of depth of STI 2.
As shown in Figure 4, form the first lifting source drain region 1P.By method selective epitaxial growths such as CVD, UHVCVD, HDPCVD, MBE, ALD, thermal decompositions, in leaking groove, the source in PMOS region forms the first lifting source drain region 1P, its top is preferably higher than substrate 1 top, and its material is for example SiGe, the SiGe:C that is applicable to PMOS.Preferably, can after simultaneously in-situ doped or epitaxial growth of epitaxial growth, carry out Implantation, formation heavy-doped source drain region (not shown), doped with boron B, aluminium Al, gallium Ga, indium In etc. for PMOS.This lifting source drain region 1P can effectively reduce the source-drain contact resistance in PMOS region, can, to PMOS channel region stress application, increase carrier mobility in addition.
As shown in Figure 5, remove protective layer 6, form cap rock in territory, nmos area and PMOS region simultaneously.By wet etching and/or dry etching, remove the remaining protective layer 6 in territory, nmos area.Subsequently, on the active area of NMOS and PMOS, carry out overall selective epitaxial simultaneously, by method selective epitaxial growths such as PECVD, HDPCVD, MBE, ALD, thermal decompositions, on the substrate 1 of gate stack structure both sides and the first lifting source drain region 1P, form cap rock 7, its material is for example Si or the Si:C that is applicable to NMOS.This cap rock 7 also can be used as the second lifting source drain region 1N in territory, nmos area.Preferably, can after simultaneously in-situ doped or epitaxial growth of epitaxial growth, carry out Implantation, formation heavy-doped source drain region (not shown), can Doping Phosphorus P, arsenic As for NMOS, antimony Sb etc.In territory, nmos area, this cap rock 7/ lifting source drain region 1N can effectively reduce the source-drain contact resistance in territory, nmos area, can, to NMOS channel region stress application, increase carrier mobility in addition.
After this, can carry out subsequent technique, for example deposit the interlayer dielectric layer (ILD of low-k materials, not shown), etching ILD forms drain contact hole, source until expose lifting source drain region 1N/1P, in drain contact hole, source, form metal silicide, plated metal is filled formation source drain contact plug, finally completes device manufacture.For rear grid technique, can be after forming ILD, remove the stacking formation gate trench of false grid, in gate trench, deposit the final gate stack structure that the gate insulator of high k material and the grid conducting layer of metal material form, and then carry out follow-up technique.
In addition,, although only shown the CMOS schematic diagram of planar channeling in accompanying drawing of the present invention, what those skilled in the art should know is that the present invention also can be applicable to other device architectures, such as three-dimensional multiple-grid, vertical-channel, nano-wire devices etc.
According to CMOS manufacture method of the present invention, first selective etch, epitaxial growth PMOS lifting source leak, and rear overall selective epitaxial growth NMOS lifting source leaks, and has reduced processing step, has reduced cost, has improved the reliability of device.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the modification of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (10)

1. a CMOS manufacture method, comprising:
On substrate, territory, nmos area and PMOS region form gate stack structure;
Around gate stack structure, form grid curb wall;
Selective etch PMOS region substrate, leaks groove in formation source, grid curb wall both sides;
Leak in groove and form the first Yuan Lou lifting district in source;
On substrate, territory, nmos area and PMOS region form cap rock.
2. method as claimed in claim 1, wherein, gate stack structure is false grid stacked structure, comprises pad oxide and false grid material layer, false grid material layer comprises polysilicon, amorphous silicon, microcrystal silicon, amorphous germanium and combination thereof.
3. method as claimed in claim 1, wherein, selective epitaxial growth is to form the first Yuan Lou lifting district and/or cap rock.
4. method as claimed in claim 1, wherein, the step of selective etch PMOS region substrate further comprises:
On whole device, form protective layer;
Selective etch protective layer, the substrate in exposure PMOS region;
The substrate that etching PMOS region exposes, groove is leaked in formation source.
5. method as claimed in claim 1, wherein, source is leaked the profile morphology of groove and is comprised rectangle, trapezoidal, inverted trapezoidal, ∑ shape, D shape, C shape and combination thereof.
6. method as claimed in claim 1, wherein, cap rock is also as the second Yuan Lou lifting district in territory, nmos area.
7. method as claimed in claim 1, wherein, cap rock comprises Si, Si:C.
8. method as claimed in claim 1, wherein, the first Yuan Lou lifting district comprises SiGe, SiGe:C.
9. method as claimed in claim 4, wherein, protective layer comprises silicon nitride, silica and combination thereof.
10. method as claimed in claim 4, wherein, forms the first Yuan Lou lifting district and also comprises removal protective layer afterwards.
CN201210395581.4A 2012-10-17 2012-10-17 CMOS manufacturing method Pending CN103779276A (en)

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