CN106158595A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN106158595A CN106158595A CN201510192196.3A CN201510192196A CN106158595A CN 106158595 A CN106158595 A CN 106158595A CN 201510192196 A CN201510192196 A CN 201510192196A CN 106158595 A CN106158595 A CN 106158595A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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Abstract
The forming method of a kind of semiconductor devices, comprising: provide layer to be etched, described surface layer to be etched is formed with initial lithographic glued membrane；Carry out photoetching process to described initial lithographic glued membrane, form the photoresist layer with the first line width roughness；Carry out sidewall backflow repair process to described photoresist layer, the photoresist layer after sidewall backflow repair process has the second line width roughness less than the first line width roughness；After the backflow repair process of described sidewall, form cured layer at described photoresist layer top surface and sidewall surfaces；Described cured layer forms repairing sizes layer.The present invention reduces the line width roughness of etching mask pattern layer to be etched, and makes size and the goal-selling consistent size of mask pattern, improves performance and the yield of the semiconductor devices of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly to the forming method of a kind of semiconductor devices.
Background technology
Technological process at semiconductor fabrication includes photoetching and two important processing steps of etching.
In a photolithographic process, first by photoresistance rotary coating on substrate, then the photoresistance of rotary coating is carried out
Soft drying, makes solid film；Then it is exposed to photoresistance processing and development treatment, at photoresistance
The desired photoengraving pattern of middle formation；Then with described photoengraving pattern as mask, step is performed etching to substrate,
Photoengraving pattern is transferred in substrate.After completing the etching to substrate, make already without wanting photoresistance
Protective layer, can remove it.
With the progress of semiconductor fabrication, semiconductor devices is in order to reach faster arithmetic speed, more
Big data storage amount and more function, semiconductor chip develops to more high integration direction；And half
The integrated level of conductor chip is higher, the characteristic size (CD, Critical Dimension) of semiconductor devices
Less, receiving CD control unprecedented challenge after the photoetching process play an important role.After photoetching
Distance between the edge of the photoengraving pattern being formed is referred to as live width (Line Width), line width roughness (LWR,
Line Width Roughness) and line edge roughness (LER, Line Edge Roughness) for weighing apparatus
One of important indicator of amount live width.Line width roughness determines the live width of CD to a certain extent, so
The importance of LWR control appears day by day.
During live width is diminishing, CD tool that problem that LWR causes will exceed in semiconductor manufacturing
Standby admissible error, thus affect the performance of semiconductor devices, reduce the yield of semiconductor devices.
Content of the invention
The problem that the present invention solves is the same of the line width roughness of reduction etching mask pattern layer to be etched
When so that the size of mask pattern is consistent with goal-selling size, thus improves the semiconductor devices of formation
Performance and yield.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor devices, comprising: provide
Layer to be etched, described surface layer to be etched is formed with initial lithographic glued membrane；Described initial lithographic glued membrane is entered
Row photoetching process, forms the photoresist layer with the first line width roughness；Side is carried out to described photoresist layer
Wall backflow repair process, the photoresist layer after sidewall backflow repair process has less than the first line width roughness
The second line width roughness；After the backflow repair process of described sidewall, at described photoresist layer top table
Face and sidewall surfaces form cured layer；Described cured layer forms repairing sizes layer.
Optionally, it is placed in described photoresist layer in the first plasma environment, use the first plasma
Process technique and carry out the backflow repair process of described sidewall.
Optionally, the gas forming described first plasma includes H2。
Optionally, the gas forming described first plasma also includes N2、He、Ar、CH2F2Or CH3F。
Optionally, in described first plasma treatment procedure, for producing the first of the first plasma
The pattern of radio frequency power source is pulse mode；In described first plasma treatment procedure, to described
One plasma applies the first bias power.
Optionally, the technological parameter of described first plasma treatment is: H2Flow be 10sccm extremely
500sccm, N2Flow is 0sccm to 500sccm, chamber pressure be 10 millitorrs to 200 millitorrs,
The power of one radio frequency power source is 200 watts to 1000 watts, and the frequency of the first radio frequency power source is 0.1KHz
To 100KHz, the first bias power is 0 watt to 200 watts, and the dutycycle of the first radio frequency power source is 10%
To 90%.
Optionally, described cured layer is class equadag coating.
Optionally, it is placed in described photoresist layer in the second plasma environment, use the second plasma
Process technique and form described cured layer.
Optionally, the gas forming described second plasma includes HBr.
Optionally, in described second plasma treatment procedure, for forming the second of the second plasma
The pattern of radio frequency power source is pulse mode；In described second plasma treatment procedure, to described
Two plasmas apply the second bias power.
Optionally, the technological parameter of described second plasma treatment is: the flow of HBr be 50sccm extremely
500sccm, O2Flow is 0sccm to 100sccm, and Ar flow is 100sccm to 500sccm, chamber
Pressure is 10 millitorrs to 200 millitorrs, and the power of the second radio frequency power source is 200 watts to 1000 watts, the
The frequency of two radio frequency power sources is 0.1KHz to 100KHz, and the second bias power is 0 watt to 200 watts,
The dutycycle of described second radio frequency power source is 10% to 90%.
Optionally, the gas containing HBr is used to form described repairing sizes layer on described cured layer surface.
Optionally, the technological parameter forming described repairing sizes layer is: HBr flow be 50sccm extremely
500sccm, O2Flow is 0sccm to 100sccm, CH2F2Flow is 0sccm to 100sccm, Ar
Flow is 100sccm to 500sccm, and chamber pressure is 10 millitorrs to 200 millitorrs, provides radio frequency source work(
Rate is 200 watts to 1000 watts, provides bias power to be 0 watt to 200 watts.
Optionally, described first line width roughness includes the first low frequency line width roughness；Described second live width
Roughness includes the second low frequency line width roughness.
Optionally, after forming cured layer, before formation repairing sizes layer, further comprise the steps of: to institute
State cured layer and photoresist layer carries out direct current repair process, form silicon layer, and institute on described cured layer surface
State silicon layer and there is the 3rd line width roughness less than the second line width roughness.
Optionally, the low frequency line width roughness of described silicon layer is less than the low frequency line width roughness of cured layer.
Optionally, the method for described direct current repair process includes: be placed in described cured layer and photoresist layer
Process in chamber, and process chamber inner wall material includes silicon；There is provided plasma, described plasma exists
Bombardment processing chamber inner wall under the effect of DC offset voltage, makes the silicon atom of process chamber inner wall come off,
The described silicon atom coming off is attached to cured layer surface, forms described silicon layer.
Optionally, the technological parameter forming described silicon layer is: N2Flow is 50sccm to 500sccm, Ar
Flow is 100sccm to 500sccm, and chamber pressure is 10 millitorrs to 200 millitorrs, and offer source power is
200 watts to 1000 watts, providing bias power to be 0 watt to 200 watts, the DC offset voltage of offer is-50V
To-500V.
Optionally, described photoresist layer has goal-selling size；The size of described repairing sizes layer, silicon
The size sum of the photoresist layer after the size of layer, the size of cured layer and sidewall reflow treatment is equal to
Goal-selling size.
Optionally, further comprise the steps of: after forming described repairing sizes layer, with described photoresist layer,
Cured layer and repairing sizes layer are mask, etch described formation etch layer layer to be etched.
Compared with prior art, technical scheme has the advantage that
In the technical scheme of the forming method of the semiconductor devices that the present invention provides, to initial lithographic glued membrane
After carrying out photoetching process, form the photoresist layer with the first line width roughness；Then photoresist layer is entered
Row sidewall backflow repair process so that photoresist layer has thick less than the second live width of the first line width roughness
Rugosity；Then form cured layer at photoresist layer top surface and sidewall surfaces, prevent photoresist layer from occurring
Excessive backward flow causes deformation；Last formation repairing sizes layer on cured layer.Repairing sizes layer, cured layer
The photoresist layer being formed after being significantly less than photoetching process with the line width roughness of the laminated construction of photoresist layer
Line width roughness, and repairing sizes layer can also make up photoresist layer loss size, with described lamination
Structure be mask etching layer to be etched when, the pattern of mask pattern is good and size is consistent with goal-selling,
Thus improve the electric property of semiconductor devices, improve the yield of semiconductor devices.
Further, described first line width roughness is the first low frequency line width roughness；Described second live width is thick
Rugosity is the second low frequency line width roughness, thus the low frequency wire improving etching mask layer to be etched is broad and rough rough
Degree, the effective pattern improving the etching rear etch layer being formed layer to be etched.
Further, after forming described cured layer, before forming repairing sizes layer, at described cured layer
Surface forms silicon layer, and the low frequency line width roughness of described silicon layer is less than the low frequency line width roughness of cured layer,
Thus reduce the low frequency line width roughness of etching mask layer to be etched further.
Brief description
The cross-section structure signal of the semiconductor devices forming process that Fig. 1 to Fig. 7 provides for the embodiment of the present invention
Figure.
Detailed description of the invention
From background technology, in the technical process forming semiconductor devices, the live width of photoresist layer is thick
Rugosity is one of key factor affecting performance of semiconductor device and yield.
It has been investigated that, photoresist layer is in addition to line width roughness, and " roughness profile " of photoresist layer is also
Can include line edge roughness, also short, in, the broad and rough variation of roughness of long-distance line, its parameter corresponds to
The direction that changes along live width and present different length scales.Except line width roughness or line limit
Outside the absolute value of edge roughness, the length scale that this change occurs is also the key that semiconductor devices manufactures
One of.
The broad and rough variation of roughness of photoresist layer long-distance line is coarse corresponding to low frequency (Low Frequency) live width
Degree；In photoresist layer, the broad and rough variation of roughness of range line is thick corresponding to intermediate frequency (Middle Frequency) live width
Rugosity；Photoresist layer short distance roughness changes corresponding to high frequency (High Frequency) line width roughness.
Wherein, the low frequency line width roughness of photoresist layer is the master causing semiconductor devices electric property difference yield low
Want one of reason.
To this end, the present invention provides the forming method of a kind of semiconductor devices, light is carried out to initial lithographic glued membrane
Carving technology, forms the photoresist layer with the first line width roughness；Carry out sidewall to described photoresist layer to return
Stream repair process, the photoresist layer after sidewall backflow repair process has the less than the first line width roughness
Two line width roughness；After the backflow repair process of described sidewall, at described photoresist layer top surface and
Sidewall surfaces forms cured layer；Described cured layer forms repairing sizes layer.The present invention is reducing mask
While the low frequency line width roughness of figure so that the size of mask pattern is consistent with goal-selling size,
Thus improve the yield of the semiconductor devices of formation, improve the performance of semiconductor devices.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The cross-section structure signal of the semiconductor devices forming process that Fig. 1 to Fig. 7 provides for the embodiment of the present invention
Figure.
With reference to Fig. 1, provide substrate 100 and be positioned at described substrate 100 surface layer to be etched 101；?
Described 101 surfaces layer to be etched form initial lithographic glued membrane 102.
The material of described substrate 100 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium；
Described substrate 100 can also be the silicon substrate on insulator or the germanium substrate on insulator.
The described material of layer to be etched 101 includes monocrystalline silicon, polysilicon, non-crystalline silicon, amorphous carbon, oxidation
Silicon, silicon nitride, low k dielectric materials, high K medium material, copper, aluminium or tungsten etc..
In the present embodiment, described substrate 100 is silicon substrate, and the described material of layer to be etched 101 is polycrystalline
Silicon.
Some functional layers, described functional layer can also be formed between described substrate 100 and layer to be etched 101
Material can for silica, silicon nitride, silicon oxynitride, high K medium material, low k dielectric materials or
The insulating materials such as person's ultra-low k dielectric material, the material of described functional layer can also be copper, aluminium, tungsten, nitrogen
Change the conductive materials such as titanium, tantalum nitride or aluminium nitride.
Described initial lithographic glued membrane 102 is for being subsequently formed the photoresist layer of definition figure.In the present embodiment,
Use spin coating process, form described initial lithographic glued membrane 102.
In order to improve figure transmitting accuracy, improve the exposure accuracy in post-exposure processing procedure, it is to avoid
Initial lithographic glued membrane 102 is exposed on layer to be etched 101 with just by unnecessary in exposure process
Form organic rotary coating layer between beginning photoresist film 102 and be positioned at the anti-of organic rotary coating layer surface
Reflectance coating.
With reference to Fig. 2, photoetching treatment is carried out to described initial lithographic glued membrane 102 (with reference to Fig. 1), forms tool
There is the photoresist layer 103 of the first line width roughness.
Concrete, it is exposed to described initial lithographic glued membrane 102 processing and development treatment, form institute
State photoresist layer 103.Described photoresist layer 103 defines pattern and the chi of subsequent etching layer to be etched 102
Very little；Follow-up with described photoresist layer 103 as mask, etch layer to be etched 101, by photoresist layer 103
Figure pattern and size are transferred to layer to be etched 101.
Described first line width roughness includes the first low frequency line width roughness.Limited by photoetching process,
The line width roughness of described photoresist layer 103 is relatively big, and now photoresist layer 103 has the first low frequency live width
Roughness；If follow-up directly perform etching to layer to be etched 101 with described photoresist layer 103 for mask,
The figure pattern then being formed after 101 etchings layer to be etched will be relatively big with target deviation, to this end, this reality
Photoresist layer 103 is repaired by extended meeting after executing example, broad and rough rough with the low frequency wire reducing photoresist layer 103
Degree, ensures that the dimension of picture that subsequent etching layer to be etched 101 is formed is consistent with target simultaneously.
With reference to Fig. 3, carry out sidewall backflow repair process, sidewall backflow repair place to described photoresist layer 102
Photoresist layer 103 after reason has the second line width roughness less than the first line width roughness.
Described second line width roughness includes the second low frequency line width roughness；After sidewall backflow repair process,
Described second low frequency line width roughness is less than the first low frequency line width roughness.
It is placed in described photoresist layer 103 in first plasma environment, use the first plasma treatment
Technique carries out the backflow repair process of described sidewall.The gas forming described first plasma includes H2；Shape
The gas becoming described first plasma also includes N2、He、Ar、CH2F2Or CH3F。
By H2After plasmarized, can produce H group, ion and VUV (Vacuum Ultra Violet,
Vacuum ultraviolet) photon, the certain thickness photoresist in photoresist layer 103 surface can be with ion and VUV
Photon reacts, thus under the synergy of ion and VUV light so that photoresist layer 103
Glass transition temperature (glass transition temperature) reduces, or, photoresist layer 103 surface
Certain thickness photoresist can react with H group and VUV light, thus at H group and VUV
Under the synergy of photon so that the glass transition temperature of photoresist layer 103 reduces, or, photoresist
The certain thickness photoresist in layer surface can react with H group, ion and VUV light so that light
The stripping conversion temperature of photoresist reduces, and the glass transition temperature reduction of photoresist layer 103 can make photoresist
The polymer chain of layer is recombinated, and polymer chain restructuring can be ordered about photoresist layer 103 and reflux
(reflow) so that the sidewall of photoresist layer 103 is more smooth, so reduce photoresist layer low frequency wire
Broad and rough rugosity.
In described first plasma treatment procedure, for producing the first radio-frequency power of the first plasma
The pattern in source is pulse mode so that for producing the first radio frequency power source of the first plasma periodically
Opening and closing, with reduce VUV light content, the degree of back flow preventing photoresist layer 103 is excessive
And cause photoresist layer 103 figure to cave in.
In a specific embodiment, the dutycycle of described first radio frequency power source is 10% to 90%, i.e.
The time sum that the time that first radio frequency power source is opened opens and closes with the first radio frequency power source is 10%
To 90%.
In described first plasma treatment procedure, apply the first biasing work(to described first plasma
Rate so that the first plasma can move along the direction being perpendicular to 101 surfaces layer to be etched so that
Photoresist layer 103 is bombarded by the direction that the first plasma can be perpendicular to 101 surfaces layer to be etched,
Under the bombardment effect of the first plasma, photoresist layer 103 can be modified so that photoresist
The low frequency line width roughness of layer 103 reduces further.
Described first bias power is unsuitable excessive, and the size of photoresist layer 103 otherwise can be caused seriously to reduce.
In a specific embodiment, described first bias power is 0 watt to 200 watts.
In the present embodiment, the technological parameter of described sidewall backflow repair process is: H2Flow be 10sccm extremely
500sccm, N2Flow is 0sccm to 500sccm, chamber pressure be 10 millitorrs to 200 millitorrs,
The power of one radio frequency power source is 200 watts to 1000 watts, and the frequency of the first radio frequency power source is 0.1KHz
To 100KHz, the first bias power is 0 watt to 200 watts, and the dutycycle of the first radio frequency power source is 10%
To 90%.
After sidewall backflow repair process, photoresist layer 103 has the second line width roughness, described second line
Broad and rough rugosity is less than the first line width roughness；Photoresist layer 103 has the second low frequency line width roughness, and
Described second low frequency line width roughness is less than the first low frequency line width roughness.
With reference to Fig. 4, after the backflow repair process of described sidewall, at described photoresist layer 103 top surface
Form cured layer 104 with sidewall surfaces.
Concrete, be placed in described photoresist layer 103 in second plasma environment, use the second grade from
Daughter processes technique and forms described cured layer 104.The gas forming described second plasma includes HBr,
Under the second action of plasma being produced by HBr, photoresist layer 103 surface can form class equadag coating
(graphite-like layer), with the carrying out of the second plasma treatment, described class equadag coating is increasingly
Thickness, thus stop photoresist layer 103 to reflux further so that photoresist layer 103 solidifies, thus prevents
Photoresist layer 103 occurs figure to cave in.
Therefore, described cured layer 104 is class equadag coating.
In described second plasma treatment procedure, for forming the second radio-frequency power of the second plasma
The pattern in source is pulse mode, and the i.e. second radio frequency power source opens and closes for periodic.If cured layer
The thickness of 104 is blocked up, can increase the low frequency line width roughness of photoresist layer 103；When being used for forming described
When second radio frequency power source of two plasmas is pulse mode, i.e. described second radio frequency power source is periodically
Opening and closing when, the thickness of the cured layer 104 of formation can be reduced so that photoresist layer 103
Line width roughness can be reduced greatly, and the particularly low frequency wire of photoresist layer 103 is broad and rough rough
Degree is reduced greatly.
In the present embodiment, the dutycycle of described second radio frequency power source is 10% to 90%, the i.e. second radio frequency
The ratio of the time sum that the time that power source is opened and the second radio frequency power source open and close be 10% to
90%.
In the second plasma treatment procedure, apply the second bias power to described second plasma.
Second plasma can be moved so that second along the direction being perpendicular to 101 surfaces layer to be etched
Photoresist layer 103 is bombarded by plasma along the direction being perpendicular to 101 surfaces layer to be etched,
Under the bombardment effect of the second plasma, photoresist layer 103 can be repaired further so that light
The line width roughness of photoresist layer 103 reduces further, particularly contributes to reducing photoresist layer 103 further
Low frequency line width roughness.
Described second bias power is unsuitable excessive, the otherwise bombardment to photoresist layer 103 for second plasma
Act on too strong, be easily caused photoresist layer 103 and removed by substantial amounts of etching.In the present embodiment, described
Two bias powers are 0 watt to 200 watts；The pattern of described second bias power can be for persistently opening, institute
The pattern stating the second bias power also can be pulse mode, the i.e. second bias power periodically open and
Close.
In the present embodiment, the technological parameter of described second plasma treatment is: the flow of HBr is 50sccm
To 500sccm, O2Flow is 0sccm to 100sccm, and Ar flow is 100sccm to 500sccm,
Chamber pressure is 10 millitorrs to 200 millitorrs, and the power of the second radio frequency power source is 200 watts to 1000 watts,
The frequency of the second radio frequency power source is 0.1KHz to 100KHz, and the second bias power is 0 watt to 200 watts,
The dutycycle of described second radio frequency power source is 10% to 90%.
Use above-mentioned technological parameter to carry out the second plasma treatment, the cured layer 104 of formation can have been made both
Play the effect making photoresist layer 103 solidify, additionally it is possible to make the low frequency line width roughness of photoresist layer 103
Reduce further, it should be noted that the low frequency line width roughness of photoresist layer 103 actually refers to herein
: the lamination of photoresist layer 103 and cured layer 104 composition being positioned at photoresist layer 103 surface is tied
The low frequency line width roughness of structure.
With reference to Fig. 5, direct current repair process is carried out to described cured layer 104 and photoresist layer 103, described
Cured layer 104 surface forms silicon layer 105, and described silicon layer 105 has the less than the second line width roughness
Three line width roughness.
Described 3rd line width roughness includes the 3rd low frequency line width roughness, and described 3rd low frequency wire is broad and rough rough
Degree is less than the second low frequency line width roughness.
The method of described direct current reparation includes: described cured layer 104 and photoresist layer 103 are placed in process
In chamber, and process chamber inner wall material includes silicon atom；It is passed through plasma in described process chamber,
Applying DC offset voltage to described process chamber, described plasma is under the effect of DC offset voltage
Bombardment processing chamber inner wall, makes the silicon atom of process chamber inner wall come off, the described silicon atom attachment coming off
On cured layer 104 surface, thus form described silicon layer 105.
Concrete, can be by plasmarized for Ar formation Ar plasma, at the work of DC offset voltage
Under with, Ar plasma bombardment processes chamber inner wall；Or, can be by N2Plasmarized formation N
Plasma, under the effect of DC offset voltage, N plasma bombardment processes chamber inner wall.
It should be noted that in the present embodiment, mesh that plasma bombards under DC offset voltage effect
It is designated as processing chamber inner wall, it is therefore desirable to according to the positive negativity of plasma-charge, determine direct current biasing electricity
The positive negativity of pressure, so that plasma bombards to processing chamber inner wall, without to cured layer 104
Bombard.
In the present embodiment, using the method that above-mentioned direct current is repaired, the low frequency wire of the silicon layer 105 of formation is broad and rough
Rugosity is less than the low frequency line width roughness of cured layer 104, thus reduces the low of photoresist layer 103 further
Frequently line width roughness；And due to described direct current repair process and aforesaid first plasma treatment, the
Two plasma treatment are carried out in same process chamber, so that the production cycle contracting of semiconductor devices
Short.It should be noted that the low frequency line width roughness of photoresist layer 103 refers to photoresist layer herein
103rd, the low frequency line width roughness of the laminated construction of cured layer 104 and silicon layer 105.
In the present embodiment, the technological parameter forming described silicon layer 105 is: N2Flow be 50sccm extremely
500sccm, Ar flow is 100sccm to 500sccm, chamber pressure be 10 millitorrs to 200 millitorrs,
There is provided source power to be 200 watts to 1000 watts, provide bias power to be 0 watt to 200 watts, the direct current of offer
Bias voltage is-50V to-500V.
Wherein, DC offset voltage is, at described DC offset voltage for the meaning of-50V to-500V
Under effect, N plasma, Ar plasma bombardment are positioned at the process chamber directly over cured layer 104
Wall, under the effect of DC offset voltage, plasma obtains to bombard and is positioned at directly over cured layer 104
Process the kinetic energy of chamber inner wall.
In other embodiments, if the material processing chamber inner wall does not include silicon atom, then silicon layer is formed
Method includes: providing silicon target, using plasma bombards silicon target under the effect of direct current biasing power,
Make silicon atom come off from silicon target and be attached to cured layer surface, form described silicon layer.
With reference to Fig. 6, described cured layer 104 forms repairing sizes layer 106.
In the present embodiment, owing to being formed with silicon layer 105, therefore described repairing sizes on cured layer 104 surface
Layer 106 is positioned at silicon layer 105 surface.
Described photoresist layer 103 has goal-selling size, and described goal-selling size is ideal situation
Under photoetching process is carried out to initial lithographic glued membrane 102 (with reference to Fig. 1) after the size of photoresist layer that formed；
Owing to photoresist layer 103 experienced by aforementioned first plasma-treating technology and the second plasma treatment
Technique, the size of described photoresist layer 103 diminishes, even if being formed with cured layer on photoresist layer 103
104 and silicon layer 105, the chi of photoresist layer the 103rd, the laminated construction of cured layer 104 and silicon layer 105
Very little still and have deviation between goal-selling size.
To this end, the present embodiment forms described repairing sizes layer 106 so that repairing sizes layer the 106th, silicon layer is the 105th,
The size of the laminated construction that cured layer 104 and photoresist layer 103 are constituted and goal-selling consistent size,
Thus prevent from going out between the pattern of the etch layer of subsequent etching 101 formation layer to be etched and target pattern
Existing deviation.
Further, after cured layer 104 forming repairing sizes layer 106, described repairing sizes layer 106
Low frequency line width roughness is less than the low frequency line width roughness of silicon layer 105, thus is conducive to improving further shape
The mask pattern pattern of the etching layer to be etched 101 becoming.
With reference to Fig. 7, with the described photoresist layer 103 with repairing sizes layer 106 as mask, etching is described
101 (with reference to Fig. 6) layer to be etched, form etch layer 110.
In the present embodiment, use dry etch process, etch described layer to be etched 101.Described etching is to be etched
The mask of erosion layer 101 is: photoresist layer the 103rd, cured layer the 104th, silicon layer 105 and repairing sizes layer 106
The laminated construction constituting.The low frequency line width roughness of described laminated construction be obviously limited to photoetching process after light
The low frequency line width roughness of photoresist layer 103, the low frequency wire of the etch layer 110 being formed after therefore etching is broad and rough
Rugosity is low；Further, due to size and the goal-selling consistent size of described laminated construction, after therefore etching
The size of the etch layer 110 being formed also is consistent with goal-selling size.
The present embodiment is improving the low frequency line width roughness of the etch layer 110 being formed, and improves etch layer 110
Pattern while, it is to avoid between the size of the etch layer 110 of formation and goal-selling size, deviation occurs,
Thus the yield of the semiconductor devices of formation is provided, improve the electric property of semiconductor devices.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a semiconductor devices, it is characterised in that include:
There is provided layer to be etched, described surface layer to be etched is formed with initial lithographic glued membrane；
Carry out photoetching process to described initial lithographic glued membrane, form the photoresist with the first line width roughness
Layer；
Carry out sidewall backflow repair process, the photoresist after sidewall backflow repair process to described photoresist layer
Layer has the second line width roughness less than the first line width roughness；
After the backflow repair process of described sidewall, in described photoresist layer top surface and sidewall surfaces shape
Become cured layer；
Described cured layer forms repairing sizes layer.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that by described photoresist
It is placed in the first plasma environment, use the first plasma-treating technology to carry out described sidewall and return
Stream repair process.
3. the forming method of semiconductor devices as claimed in claim 2, it is characterised in that form described first
The gas of plasma includes H2。
4. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that form described first
The gas of plasma also includes N2、He、Ar、CH2F2Or CH3F。
5. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that described first grade from
It in daughter processing procedure, is pulse for producing the pattern of the first radio frequency power source of the first plasma
Pattern；In described first plasma treatment procedure, apply first to described first plasma inclined
Put power.
6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that described first grade from
The technological parameter that daughter is processed is: H2Flow is 10sccm to 500sccm, N2Flow is 0sccm
To 500sccm, chamber pressure is 10 millitorrs to 200 millitorrs, and the power of the first radio frequency power source is 200
Watt to 1000 watts, the frequency of the first radio frequency power source is 0.1KHz to 100KHz, the first biasing work(
Rate is 0 watt to 200 watts, and the dutycycle of the first radio frequency power source is 10% to 90%.
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that described cured layer is
Class equadag coating.
8. the forming method of semiconductor devices as claimed in claim 7, it is characterised in that by described photoresist
It is placed in the second plasma environment, use the second plasma-treating technology to form described cured layer.
9. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that form described second
The gas of plasma includes HBr.
10. the forming method of semiconductor devices as claimed in claim 9, it is characterised in that described second grade from
It in daughter processing procedure, is pulse for forming the pattern of the second radio frequency power source of the second plasma
Pattern；In described second plasma treatment procedure, apply second to described second plasma inclined
Put power.
The forming method of 11. semiconductor devices as claimed in claim 10, it is characterised in that described second grade from
The technological parameter that daughter is processed is: the flow of HBr is 50sccm to 500sccm, O2Flow is 0sccm
To 100sccm, Ar flow is 100sccm to 500sccm, and chamber pressure is that 10 millitorrs are to 200 millis
Torr, the power of the second radio frequency power source is 200 watts to 1000 watts, and the frequency of the second radio frequency power source is
0.1KHz to 100KHz, the second bias power is 0 watt to 200 watts, described second radio frequency power source
Dutycycle be 10% to 90%.
The forming method of 12. semiconductor devices as claimed in claim 1, it is characterised in that use and contain HBr
Gas form described repairing sizes layer on described cured layer surface.
The forming method of 13. semiconductor devices as claimed in claim 12, it is characterised in that form described size
The technological parameter of repair layer is: HBr flow is 50sccm to 500sccm, O2Flow be 0sccm extremely
100sccm, CH2F2Flow is 0sccm to 100sccm, and Ar flow is 100sccm to 500sccm,
Chamber pressure is 10 millitorrs to 200 millitorrs, provide RF source power be 200 watts to 1000 watts, carry
It it is 0 watt to 200 watts for bias power.
The forming method of 14. semiconductor devices as claimed in claim 1, it is characterised in that described first live width
Roughness includes the first low frequency line width roughness；Described second line width roughness includes the second low frequency live width
Roughness.
The forming method of 15. semiconductor devices as claimed in claim 1, it is characterised in that forming cured layer
Afterwards, before forming repairing sizes layer, further comprise the steps of: and described cured layer and photoresist layer are carried out
Direct current repair process, forms silicon layer on described cured layer surface, and described silicon layer has less than the second line
3rd line width roughness of broad and rough rugosity.
The forming method of 16. semiconductor devices as claimed in claim 15, it is characterised in that described silicon layer low
Frequently line width roughness is less than the low frequency line width roughness of cured layer.
The forming method of 17. semiconductor devices as claimed in claim 15, it is characterised in that described direct current reparation
The method processing includes: is placed in described cured layer and photoresist layer in process chamber, and processes chamber
Inner-wall material includes silicon；There is provided plasma, described plasma is under the effect of DC offset voltage
Bombardment processing chamber inner wall, makes the silicon atom of process chamber inner wall come off, and the described silicon atom coming off is attached
On cured layer surface, form described silicon layer.
The forming method of 18. semiconductor devices as claimed in claim 17, it is characterised in that form described silicon layer
Technological parameter be: N2Flow is 50sccm to 500sccm, Ar flow be 100sccm extremely
500sccm, chamber pressure is 10 millitorrs to 200 millitorrs, provide source power be 200 watts to 1000
Watt, provide bias power to be 0 watt to 200 watts, the DC offset voltage of offer is-50V to-500V.
The forming method of 19. semiconductor devices as claimed in claim 1, it is characterised in that described photoresist layer
There is goal-selling size；The size of described repairing sizes layer, the size of silicon layer, cured layer size,
And the size sum of the photoresist layer after sidewall reflow treatment is equal to goal-selling size.
The forming method of 20. semiconductor devices as claimed in claim 1, it is characterised in that further comprise the steps of:
It after forming described repairing sizes layer, with described photoresist layer, cured layer and repairing sizes layer is
Mask, etches described formation etch layer layer to be etched.
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| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
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| CN111769037B (en) * | 2020-05-29 | 2021-10-29 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
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