CN104681417B - The forming method of semiconductor devices and grid - Google Patents
The forming method of semiconductor devices and grid Download PDFInfo
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- CN104681417B CN104681417B CN201310617880.2A CN201310617880A CN104681417B CN 104681417 B CN104681417 B CN 104681417B CN 201310617880 A CN201310617880 A CN 201310617880A CN 104681417 B CN104681417 B CN 104681417B
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Abstract
The present invention provides the forming method of a kind of semiconductor devices and grid, in the forming method of the semiconductor devices, photoresist layer above hard mask layer is patterned, formed after photoetching agent pattern, sofening treatment technique is carried out to photoetching agent pattern, so as to effectively reduce photoetching agent pattern surface roughness, afterwards, elder generation's hard mask layer described in mask etching part using photoetching agent pattern, remove the photoetching glue residua of photoetching agent pattern sidewall bottom, compactification handling process is carried out to the photoetching agent pattern afterwards, solidify photoetching agent pattern simultaneously, decorative layer is formed on photoetching agent pattern surface, improve the flatness of the photoetching agent pattern sidewall surfaces, it is follow-up using after photoetching agent pattern hard mask layer described in mask etching to improve, the quality of the hard mask pattern obtained, and then improve follow-up using after hard mask pattern material layer to be etched described in mask etching, the structure precision of the semiconductor devices of acquisition, so as to optimize the performance of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor preparation field, more particularly, to the forming method of a kind of semiconductor devices and grid.
Background technology
With the development of ic manufacturing technology, the integrated level of integrated circuit is continuously increased, the feature chi of integrated circuit
It is very little also continuous to reduce thus also strict all the more for the quality requirement of each electric elements in integrated circuit.
In integrated circuit fabrication process, photoetching process is considered as the core procedure in large scale integrated circuit manufacture.
Photoetching process is to be transferred to the figure on mask plate in each film layer of Semiconductor substrate by exposure, and each film is etched afterwards
Technique of the layer to form the film layer for carrying specific pattern.
The development of modern photoetching technique mainly refers to around line width, alignment (overlay) precision of etching pattern etc.
Mark expansion.Especially after the semiconductor technology of 28nm and smaller processing procedure is entered, for the etching pattern formed after photoetching
Precise requirements it is strict all the more.
With reference to Fig. 1, so that in MOS transistor formation process, etching is formed exemplified by polysilicon gate.In the shape of polysilicon gate
Into in technique, polysilicon layer 11, hard mask layer 12, and photoresist layer 13 are first sequentially formed over the semiconductor substrate 10；Exposing
After light technique, pattern is formed on the photoresist layer 13, and with the photoresist layer 13 after patterning for the hard mask of mask etching
Layer 11, forms hard mask pattern, and forming polysilicon gate by mask etching polysilicon layer 11 of the hard mask pattern afterwards
Pole.
In the formation process of above-mentioned polysilicon gate, as the mask of the polysilicon gate ultimately formed, after exposure
Photoetching agent pattern has material impact for the structure of the polysilicon gate of final molding.But with continued reference to shown in Fig. 1, exposing
It is poor in the flatness of the side wall of the photoetching agent pattern of formation after light technique, and then influence follow-up hard mask layer 12 and polycrystalline
The etching technics of silicon layer 11, and the structure for the polysilicon gate to be formed finally is influenceed, the grid line width of such as polysilicon gate is coarse
Degree（Line Width Roughness）It is larger, and then reduction ultimately forms polysilicon gate performance.
Thus, the structure of photoetching agent pattern how is improved, the problem of be those skilled in the art's urgent need to resolve.
The content of the invention
The problem of present invention is solved is to provide the forming method of a kind of semiconductor devices and grid, can effectively improve photoresist
The flatness on the photoetching agent pattern surface formed after pattern layers, so as to optimize photoetching agent pattern structure, to improve follow-up each step
The etching effect of etching technics.
To solve the above problems, the present invention provides a kind of method of forming gate, including：
Semiconductor substrate is provided；
Material layer to be etched is formed on the semiconductor substrate, and hard mask layer is formed in the material layer to be etched,
Photoresist layer is formed on hard mask layer；
The photoresist layer is patterned, photoetching agent pattern is formed；
Sofening treatment technique is carried out to the photoetching agent pattern；
The hard mask layer is etched by Mask portion of the photoetching agent pattern；
Compactification handling process is carried out to the photoetching agent pattern, decorative layer is formed on the surface of the photoetching agent pattern；
Using the photoetching agent pattern as the remaining hard mask layer of mask etching, hard mask pattern is formed；
Using the hard mask pattern described in mask etching material layer to be etched.
Alternatively, the sofening treatment technique includes：It it is 40~60 DEG C in temperature, pressure is 70~100mtorr, biasing
Power is 50~300W, under the conditions of bias voltage is 0~100V, be continually fed into grade that flow contains H2 for 100~300sccm from
Sub- 30~60s of gas.
Alternatively, during the sofening treatment technique, bias voltage, the pulsed adjustment are adjusted using pulsed
The frequency of bias voltage is 20~50Hz.
Alternatively, in hard mask layer technique described in partial etching, the thickness of the hard mask layer of removal is
Alternatively, the compactification handling process is：The plasma gas containing HBr is passed through, so that in the photoresist
The surface of pattern forms the decorative layer.
Alternatively, the compactification handling process is：It it is 40~60 DEG C in temperature, pressure is 5~30mtorr, biases work(
Rate is 50~200W, under the conditions of bias voltage is 0~100V, is continually fed into what flow was 100~300sccm containing HBr etc.
30~60s of ionized gas.
Alternatively, after the hard mask layer is formed, at upper formation Darc layers of the hard mask layer, and in the Darc
Barc layers are formed on layer.
Alternatively, after sofening treatment is carried out to the photoetching agent pattern, the institute by mask etching of the photoetching agent pattern
State Darc layers and Barc layers, and when carrying out compactification handling process to the photoetching agent pattern, equally after etching described
Darc layers and Barc layer surfaces formation decorative layer.
Present invention also offers a kind of forming method of grid, including,
Semiconductor substrate is provided；
Gate material layers are formed on the semiconductor substrate, hard mask layer are formed in the gate material layers, hard
Photoresist layer is formed on mask layer；
The photoresist layer is patterned, photoetching agent pattern is formed；
Sofening treatment technique is carried out to the photoetching agent pattern；
The hard mask layer is etched by Mask portion of the photoetching agent pattern；
Compactification handling process is carried out to the photoetching agent pattern, decorative layer is formed on the surface of the photoetching agent pattern；
Using the photoetching agent pattern as the remaining hard mask layer of mask etching, hard mask pattern is formed；
Using hard mask pattern gate material layers described in mask etching, grid is formed.
Alternatively, the gate material layers are polysilicon layer.
Compared with prior art, technical scheme has advantages below：
After photoresist layer above hard mask layer is patterned into photoetching agent pattern, the photoetching agent pattern is carried out
During sofening treatment technique, sofening treatment, the part photoetching agent pattern part is slid in flow-like by photoetching agent pattern side wall,
So as to effectively reduce the photoetching agent pattern surface roughness, the flatness for causing photoetching agent pattern side wall is improved；It
Afterwards, the hard mask layer is etched by Mask portion of the photoetching agent pattern, so as to effectively remove in above-mentioned sofening treatment process
In, the stacking of photoetching agent pattern sidewall bottom is slid and be formed at by photoetching agent pattern side wall in the photoresist of flow-like, is improved
The flatness of photoetching agent pattern side wall；Afterwards, decorative layer is formed on the surface of the photoetching agent pattern, further improves photoresist
The surface smoothness of pattern, optimizes photoetching agent pattern structure, so that it is guaranteed that follow-up using photoetching agent pattern as the hard mask of mask etching
The accuracy of hard mask pattern obtained after layer, and afterwards using hard mask pattern as mask etching material layer to be etched after, obtain
The accuracy of the semiconductor devices obtained.Such as in the forming method of grid, it can effectively improve using hard mask layer as mask etching grid
The accuracy of the structure of the grid obtained after the material layer of pole, and then improve the performance of grid.
Still optionally further, the method for the sofening treatment includes, and under 70~100mtorr pressure, is passed through containing H2's
Plasma gas, so as to realize the softening of photoetching agent pattern.Wherein, institute is carried out under the vacuum condition of 70~100mtorr pressure
Sofening treatment technique is stated, so as to while the photoetching agent pattern softening is realized, apply suitable to the photoetching agent pattern periphery
When pressure, it is to avoid photoetching agent pattern is overbated expansion so that photoetching agent pattern produces gross distortion and influences photoresist figure
The structure of case, and then influence follow-up other etching process such as progress hard mask layer etching by mask of photoetching agent pattern
Progress.
Brief description of the drawings
Fig. 1 is a kind of structural representation of polysilicon gate formation of the prior art；
Fig. 2 to Fig. 7 is a kind of structural representation of method of forming gate provided in an embodiment of the present invention.
Embodiment
As described in background, as integrated circuit integrated level increases, the device size of integrated circuit constantly reduces, right
It is strict all the more in the quality requirement of device.But in existing photoetching technique, the photoetching formed after photoresist exposure, developing process
The flatness of the side wall of glue pattern is poor, and then can influence the etching of such as hard mask layer subsequently by mask of photoetching agent pattern
Precision, and then influence the quality of the IC-components of follow-up each etching technics formation.
Therefore, industry is after photoetching agent pattern is formed, it can be carried out using the gases such as the HBr photoetching agent pattern softer to quality
Curing process（HBr cure）, and polymer-modified layer is formed on the surface of photoetching agent pattern, to improve photoetching agent pattern surface
（Such as side wall）Flatness.
But in actual mechanical process, formed even in photoetching agent pattern surface after modification, photoetching agent pattern side wall
Flatness is not still high, especially the bottom in photoetching agent pattern side wall, and relative to side wall other positions, it stretches out.Point
Analyse its reason, the material layer of the bottom of photoresist directly with being disposed below（Such as hard mask layer）Bonding.Expose, develop for this
After technique, the bottom of photoetching agent pattern side wall, which still has part residual, to be removed.Thus even in the side wall of photoetching agent pattern
Decorative layer is formed, it is larger compared to side wall other positions width in the bottom of the side wall of photoetching agent pattern, destroy photoresist figure
The flatness of case side wall.
Drawbacks described above can be directly affected subsequently using photoetching agent pattern as the hard mask of mask etching in semiconductor preparing process
What is obtained after the accuracy for the hard mask pattern that layer is obtained, and the etching technics of progress by mask of hard mask pattern partly leads
The dimensional accuracy of body device.Especially constantly reduce in the size of contemporary semiconductor device, the precision for semiconductor devices will
Ask strict all the more.Such as in the technique of etching grid material formation grid, the precision defect of photoetching agent pattern is directly affected subsequently
The dimensional accuracy of the grid of formation, and formed grid performance.
For drawbacks described above, the invention provides the forming method of a kind of semiconductor devices and grid.The semiconductor device
The forming method of part includes, after photoetching agent pattern is formed, and sofening treatment is carried out to photoetching agent pattern, so as to reduce photoresist figure
Case surface roughness, afterwards using photoetching agent pattern as mask etching part hard mask layer after, then at the surface shape of photoetching agent pattern
Into decorative layer, so that the overall planarization of photoetching agent pattern side wall is improved, and using photoetching agent pattern as mask etching hard mask layer
The precision of the hard mask pattern obtained, so improve it is follow-up using hard mask pattern as mask etching material layer to be etched after, formation
Semiconductor devices precision.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings, with grid
Exemplified by etching technics in forming method, the specific embodiment of the present invention is described in detail.
Fig. 2 to Fig. 7 is the structural representation of the one embodiment for the method for forming gate that the present invention is provided.
Referring initially to, there is provided Semiconductor substrate 100, being formed according to this from the bottom to top in the Semiconductor substrate 100 shown in Fig. 2
Gate material layers 200, hard mask layer 300, Darc layers（Dielectric Anti-Reflect Coating, dielectric anti reflective
Layer）400th, Barc layers（Bottom Anti-reflective coating, bottom antireflective coating）500 and photoresist layer 600.
The Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or non-crystalline silicon or silicon, germanium, GaAs or silicon
Germanium compound.The Semiconductor substrate 100 can have the structure such as silicon on epitaxial layer or insulating barrier, and existing Semiconductor substrate all may be used
As the Semiconductor substrate of the present invention, it will not enumerate herein.
The hard mask layer 300 can be the materials such as silicon nitride, silicon oxynitride, and existing hard mask material layer all can be
The material of hard mask layer 300 in the present embodiment, will not enumerate herein.
The Barc layers 500 and Darc layers 400 have absorption effects, can prevent what reflected light from forming with the incident interference of light
Standing wave causes photoresist side wall " standing wave effect ", so as to increase lithographic process window, improve the wide control of photoetching bar.
In the present embodiment, the material of the gate material layers 200 can be polysilicon, and the grid being subsequently formed is polysilicon gate
Pole.
In the present embodiment, the gate material layers 200, hard mask layer 300, Darc layers 400, Barc layers 500 and photoresist
The formation process of layer 600 is chosen as CVD（Chemical vapor deposition method）.
It is worth noting that, in the other embodiment in addition to the present embodiment, the Darc layers 400, Barc layers 500 can be selected
Excellent selectively formed, the Darc layers 400, Barc layers 500 can improve the photoetching obtained after the follow-up photoresist layer 600 exposes
The quality of glue pattern, but do not formed and described state Darc layers 400, Barc layers 500 and the object of the invention will not be hindered to realize.
With reference to shown in Fig. 3, the photoresist layer 600 is patterned using exposure, developing process, on the Barc layers 500
Form photoetching agent pattern 610.
With reference to shown in reference to Fig. 4, afterwards, sofening treatment technique is carried out to the photoetching agent pattern 610, so as to reduce photoetching
The roughness of the side wall of glue pattern 610.
In the present embodiment, the sofening treatment technique is：It is passed through into reaction chamber containing H2Plasma gas so that institute
State photoetching agent pattern suitably to soften, to improve the flatness of the side wall of photoetching agent pattern 611.
Specifically include：It is 40~60 DEG C to adjust the temperature in reaction chamber, and pressure is 70~100mtorr vacuum, and
Bias power is 50~300W, and bias voltage is 0~100V conditions, is continually fed into flow and contains H for 100~300sccm2Etc.
30~60s of ionized gas（Second）So that the photoetching agent pattern suitably softens, to improve the smooth of the side wall of photoetching agent pattern 611
Degree.
In above-mentioned sofening treatment technique, after the peripherally located part photoresist of the photoetching agent pattern 610 is softened, by
The side wall of the photoetching agent pattern 610 slides, so as to effectively reduce the roughness of the side wall 611 of the photoetching agent pattern 610
（roughness）, improve the surface smoothness of photoetching agent pattern 610.
Wherein, carried out in above-mentioned sofening treatment technique under the vacuum condition of 70~100mtorr pressure, by photoresist figure
Case is positioned over progress sofening treatment technique under elevated pressures vacuum condition so that the photoetching agent pattern 610 suitably softens simultaneously,
The photoetching agent pattern 610 is surrounded, applies appropriate pressure, so as to avoid photoetching agent pattern overdistension, prevents photoresist figure
Case produces gross distortion, and then influences the follow-up etching technics carried out by mask of photoetching agent pattern to carry out.In the present embodiment, if
Pressure is more than 100mtorr, then photoetching agent pattern sofening treatment technique is not obvious, and excessive pressure is likely to result in photoresist figure
Case compressive deformation, but if pressure is less than 70mtorr photoetching agent pattern may be caused to be pressurized not enough, and cause photoetching agent pattern
610 overdistensions, and cause photoetching agent pattern 610 to produce deformation.
In the present embodiment, by containing H described in control2Plasma gas flow be 100~300sccm, Yi Jichi
The continuous time being passed through（30~60s）, contain H used in softening photoresist to adjust2Plasma gas amount, to cause photoetching
The appropriate softening on glue top layer, it is to avoid excessive contains H2Plasma gas to spend softening photoresist more, and too small amount of contain
There is H2Plasma gas can not cause photoresist surface it is enough softening and do not reach cause photoetching agent pattern top layer planarizing mesh
's.In the present embodiment, by the pressure in reaction chamber and be passed through contain H2Plasma flow and time control photoetching
The softening degree on glue top layer, to reach the purpose of planarizing photoresist simultaneously, it is to avoid photoresist is overbated and causes serious change
Shape.Its concrete numerical value is determined according to actual conditions.
Alternatively, in the present embodiment, during above-mentioned sofening treatment, bias voltage is adjusted using pulsed.As described
Bias voltage value is the first bias voltage（0≤the first bias voltage≤100V）, can be effective by adjusting the numerical value of bias voltage
Adjustment contains H2Plasma gas direction and energy, to improve the bating effect of photoetching agent pattern.
Alternatively, in the present embodiment, during the sofening treatment, first bias voltage is produced indirectly（I.e., partially
Put voltage and changed between the first bias voltage and 0V biasings）.Still optionally further, the pulsed adjusts the frequency of bias voltage
Rate is 20~50Hz.In the above-described state, H can be effectively improved2Plasma gas and photoresist reaction effect.
In the present embodiment, by adjusting temperature（40~60 DEG C）, pressure（70~100mtorr）, coordinate and specifically contain H2
The amount of plasma gas, energy, and direction can suitably soften photoetching agent pattern 610, so as to improve photoetching agent pattern surface
While planarization, it is to avoid excessive deformation occurs in photoetching agent pattern 610, to ensure photoetching agent pattern precision.
With reference to shown in reference to Fig. 3 and Fig. 4, in Fig. 3, the side wall of photoetching agent pattern 610 formed after exposure, developing process
611 concavo-convex phenomenons are more obvious, and flatness is poor；And in Fig. 4, after the sofening treatment technique, the photoetching agent pattern
The side wall planarization of 620 side wall 621 be improved significantly.
It is mask with the photoetching agent pattern 620 after sofening treatment technique with reference to shown in Fig. 5, the etching Darc layers 400,
Barc layers 500, form new Darc layers 410 and new Barc layers 510.
It is mask with reference to shown in Fig. 6, then with the photoetching agent pattern 620, hard mask layer 300 described in etched portions is formed
First hard mask pattern 310.Wherein, it is surrounded on the part of the photoetching agent pattern 620, Darc layers 410 and the periphery of Barc layers 510
Hard mask layer 300 is etched removal, and the hard mask layer 300 positioned at the underface part of Darc layers 410 is retained so that institute's shape
Into the sectional view of the first hard mask pattern 310 be in raised " convex " font structure in middle upper end.
The photoresist layer, Barc layers and Darc layers, and hard mask layer 300 etching technics, including etching agent selection
Deng being the maturation process of this area, will not be repeated here.
In the present embodiment, the thickness h of the removed hard mask layer 300 in the surface of hard mask layer 300 isThis
When, the width of the first hard intermediate raised portion of mask pattern 310 is consistent with the width of the photoetching agent pattern 620.So that
The sidewall bottom of photoetching agent pattern 620 is raised in the described first hard top of mask pattern 310 completely.
With reference to shown in Fig. 7, afterwards, compactification handling process is carried out to the photoetching agent pattern 620, in the photoresist figure
The surface of case 620 forms decorative layer 700, so as to improve the flatness of the side wall of the photoetching agent pattern 620, optimizes the photoetching
The structure of glue pattern 620.
In the present embodiment, the compactification handling process is：The plasma gas containing HBr is passed through into reaction chamber,
The HBr reacts with photoetching agent pattern 620, so as to form decorative layer 700 on the surface of the photoetching agent pattern 620.
In the present embodiment, the decorative layer 700 is formed simultaneously in the side wall of the Darc layers 410 and Barc layers 510.
With reference to shown in reference to Fig. 4 and Fig. 5, in Fig. 4, after the sofening treatment technique, the photoetching agent pattern 620
The flatness of side wall 621 preferably, thus can improve the hard mask pattern formed after hard mask layer 300 described in subsequent etching.But on
State in sofening treatment technique, part photoresist is by the photoetching agent pattern 610（Shown in Fig. 3）Side wall slide to effectively improve
The side wall flatness of photoetching agent pattern 620 formed after softening process simultaneously, the part photoetching slid by the side wall of photoetching agent pattern 620
Glue stacks 622 in the sidewall bottom of photoetching agent pattern 620 formation（footing）；And in Fig. 5, based on the He of Barc layers 400
Hard mask layer 300 is fitted, in the new Darc layers 410 of the etching formation of Darc layers 400, at the side wall bottom of Darc layers 410
Portion can also form Darc layer materials residual（footing）411.
With reference to shown in reference to Fig. 6, the hard mask layer 300 is being etched originally, the sidewall bottom shape of photoetching agent pattern 620
Into stack 622 and Darc layer materials residual 411 can influence after hard mask layer 300 described in subsequent etching, the originally formed
The one hard accuracy of mask pattern 310, includes the side wall flatness of the influence first hard mask pattern 310, and described the
Hard mask material layer residual 412 is formed on the bottom of one hard mask pattern 310.
With continued reference to shown in Fig. 6, in the present embodiment, after the decorative layer 700 formation, the photoetching is further increased
The flatness on the surface of glue pattern 620, although after the hard mask layer 300 is etched, the first hard mask pattern 310 of formation it is convex
Rise and hard mask material layer residual 412 is still formed with below the side wall of part.But HBr is difficult to occur instead with hard mask material layer
Should, thus hard mask material layer residual 412 does not influence to be modified the photoetching agent pattern 620 of the parcel of layer 700, Darc layers 410
With the structure of Barc layers 510.
In the present embodiment, the compactification handling process is specially：The temperature for adjusting reaction chamber is 40~60 DEG C, and pressure is
5~30mtorr, bias power is 50~200W, under the conditions of bias voltage is 0~100V, be continually fed into flow for 100~
300sccm 30~60s of plasma gas containing HBr.So as to realize the compactification of photoetching agent pattern 620, while in photoetching
The top layer of glue pattern 640, Barc layers 510 and Darc layers 410 forms polymer-modified layer 700.
With reference to shown in Fig. 7, in above-mentioned compactification handling process, in previous sofening treatment technique, the photoresist being softened
Pattern 620 is cured and realizes compactification, so that the structure of photoetching agent pattern 620 is optimized, meanwhile, in the photoresist figure
Case 620 is after the decorative layer is formed, the side wall formation decorative layer 700 of photoetching agent pattern 620 so that the photoetching agent pattern
The flatness of 620 side wall each several parts is more consistent, improves the side wall integral smoothness of the photoetching agent pattern 620.
After, the remaining hard mask layer 310 is continued for mask etching with the photoetching agent pattern 620, herein mistake
Cheng Zhong, hard mask material layer residual 412 is completely removed, and forms hard mask pattern in the gate material layers 200.At it
In grid formation process afterwards, using hard mask pattern gate material layers 200 described in mask etching, in semiconductor lining
The top of bottom 100 forms grid.It is based on, the good flatness of the side wall of photoetching agent pattern 620, etches the hard mask pattern obtained
Size is more accurate, thus can effectively improve subsequently using after hard mask pattern gate material layers 200 described in mask etching,
The accuracy of the grid structure of acquisition.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
1. a kind of forming method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided；
Material layer to be etched is formed on the semiconductor substrate, hard mask layer is formed in the material layer to be etched, hard
Photoresist layer is formed on mask layer；
The photoresist layer is patterned, photoetching agent pattern is formed；
Sofening treatment technique is carried out to the photoetching agent pattern；
The hard mask layer is etched by Mask portion of the photoetching agent pattern；
Compactification handling process is carried out to the photoetching agent pattern, decorative layer is formed on the surface of the photoetching agent pattern；
Using the photoetching agent pattern as the remaining hard mask layer of mask etching, hard mask pattern is formed；
Using the hard mask pattern described in mask etching material layer to be etched.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the sofening treatment technique includes：
It it is 40~60 DEG C in temperature, pressure is 70~100mtorr, bias power is 50~300W, and bias voltage is 0~100V conditions
Under, it is continually fed into flow and contains H for 100~300sccm230~60s of plasma gas.
3. the forming method of semiconductor devices as claimed in claim 2, it is characterised in that the process of the sofening treatment technique
In, bias voltage is adjusted using pulsed, the frequency of the pulsed adjustment bias voltage is 20~50Hz.
4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that hard mask layer work described in partial etching
In skill, the thickness of the hard mask layer of removal is
5. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the compactification handling process is：
The plasma gas containing HBr is passed through, so as to form the decorative layer on the surface of the photoetching agent pattern.
6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that the compactification handling process is：
Temperature be 40~60 DEG C, pressure be 5~30mtorr, bias power be 50~200W, bias voltage be 0~100V under the conditions of,
It is continually fed into 30~60s of plasma gas containing HBr that flow is 100~300sccm.
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that after the hard mask layer is formed,
At upper formation Darc layers of the hard mask layer, and Barc layers of the formation on the Darc layers.
8. the forming method of semiconductor devices as claimed in claim 7, it is characterised in that carried out to the photoetching agent pattern
After sofening treatment, using the photoetching agent pattern Darc layers and Barc layers described in mask etching, and to the photoetching agent pattern
When carrying out compactification handling process, the Darc layers equally after etching and Barc layer surfaces formation decorative layer.
9. a kind of forming method of grid, it is characterised in that
Semiconductor substrate is provided；
Gate material layers are formed on the semiconductor substrate, and hard mask layer is formed in the gate material layers；
Photoresist layer is formed on hard mask layer；
The photoresist layer is patterned, photoetching agent pattern is formed；
Sofening treatment technique is carried out to the photoetching agent pattern；
The hard mask layer is etched by Mask portion of the photoetching agent pattern；
Compactification handling process is carried out to the photoetching agent pattern, decorative layer is formed on the surface of the photoetching agent pattern；
Using the photoetching agent pattern as the remaining hard mask layer of mask etching, hard mask pattern is formed；
Using hard mask pattern gate material layers described in mask etching, grid is formed.
10. method of forming gate as claimed in claim 9, it is characterised in that the gate material layers are polysilicon layer.
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| CN107527797B (en) * | 2017-08-16 | 2022-04-05 | 江苏鲁汶仪器有限公司 | Method for improving photoresist line edge roughness |
| CN117135994B (en) * | 2023-10-25 | 2023-12-29 | 致真存储(北京)科技有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN117936376A (en) * | 2024-03-25 | 2024-04-26 | 上海谙邦半导体设备有限公司 | Etching method of silicon carbide groove and silicon carbide semiconductor device |
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| CN101071273A (en) * | 2006-05-09 | 2007-11-14 | 虹创科技股份有限公司 | Method for manufacturing thin film pattern layer |
| CN101458463B (en) * | 2007-12-13 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Ashing method |
| CN101777493A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Hard mask layer etching method |
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2013
- 2013-11-27 CN CN201310617880.2A patent/CN104681417B/en active Active
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