JP3125869B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a field-effect semiconductor device having a T-type gate electrode.

[0002]

2. Description of the Related Art In general, a field effect transistor (hereinafter, referred to as a field effect transistor)
Called FET. In (2), the gate electrode is formed of a so-called mushroom (or T-type) gate electrode in order to prevent an increase in gate resistance due to a reduction in gate length.

In this gate electrode, the channel and the contact portion, which are the gate length, are made thinner, and the upper part of the gate electrode is made thicker to reduce the gate resistance.

[0004] Here, F using a conventional T-type gate electrode is used.
ET is introduced in, for example, Japanese Patent Application Laid-Open No. 6-120253. An FET using a T-type gate electrode according to this publication will be described with reference to FIG.

In the FET disclosed in the above publication, an insulating film 12 is laminated on a compound semiconductor 11, and a T-type gate electrode 14 which is in contact with the surface of the compound semiconductor 11 through an opening 13 formed in the insulating film 12 is formed. It has been configured.

In the FET having such a configuration, the T-shaped gate electrode 14 that is unstable in shape upright can be supported by the insulating film 12, so that characteristics and manufacturing can be stabilized.

However, the lower portion of the upper portion of the T-type gate electrode 14 is filled with the insulating film 12. For this reason, the problem is that the high-frequency characteristics, particularly the gain, of the FET are reduced as compared to the case where the parasitic film is generated and the insulating film 12 is not present.

As a countermeasure against the above problem, a semiconductor device having a configuration as shown in FIG. 8 has been developed. Two insulating film layers, a lower insulating film 16 and an upper insulating film 17, are provided on the compound semiconductor 11, and an opening 18 of the lower insulating film 16 is formed wider than an opening 19 of the upper insulating film 17. A cavity is formed on both sides of the leg of the T-type gate electrode 14 by combining sputtering and a lift-off method from the openings 19 and 18.

The FET is molded using a resin or the like in order to reduce the cost of the package. If a gate is covered with only a thin protective film (passivation film) and molding is performed on the exposed FET, the gate electrode may be damaged when the molding resin is dropped. Further, when the resin is solidified, the gate electrode may be in a state where a high stress is applied.

[0010]

However, in the semiconductor device developed as a countermeasure for the above-mentioned prior art, the parasitic capacitance between the source electrode or the drain electrode and the gate electrode can be reduced. The legs of the mold gate electrode 14 are only limited by the openings 19 in the upper insulating film 17. Therefore, when forming the gate electrode, the width of the portion of the leg portion of the T-type gate electrode 14 that is in contact with the surface of the compound semiconductor 11 is increased, and the reduction of the gate length may be incomplete.

The exposed surface of the cavity 11 formed by widening the opening 18 of the lower insulating film 16 is easily affected by the atmosphere of the cavity and impurities at the time of forming the cavity.
In some cases, the electrical characteristics were adversely affected.

(Object of the present invention) In the present invention, while protecting the gate electrode 3 against the mold, the insulating film under the eaves of the gate electrode 3 is removed so that the gap between the source or drain electrode and the gate electrode can be reduced. It is an object of the present invention to reduce the parasitic capacitance of the semiconductor device and improve the RF characteristics.

[0013]

Means for Solving the Problems In order to solve the above problems,
A method for manufacturing a semiconductor device according to the present invention includes a T-shaped gate electrode having a T-shaped cross section provided on a semiconductor substrate and having eaves protruding on both upper sides thereof, and on both sides of the T-shaped gate electrode,
A source electrode and a drain electrode provided on the semiconductor substrate; a SiO ₂ film formed so as to cover an upper portion of the T-type gate electrode; and a mold protection film further formed on a surface of the SiO ₂ film. Of manufacturing semiconductor device provided with semiconductor device
A is, the gate electrode by planarizing the SiO ₂ film
Exposing the SiO ₂ film and the T-type gate electrode.
Forming a mold protection film on the top, opening an opening for injecting an etching solution into the mold protection film, injecting the etching solution from the opening , and forming an eaves of the T-type gate electrode. By etching the underlying SiO ₂ film , a space is formed under the eaves of the T-type gate electrode.

Further, a method of manufacturing a semiconductor device according to the present invention
A T-shaped gate electrode provided on the semiconductor substrate and having an eaves protruding on both upper sides thereof and having a T-shaped cross section ; and a source provided on both sides of the T-shaped gate electrode and provided on the semiconductor substrate. In a semiconductor device comprising: an electrode and a drain electrode; an insulating film formed so as to cover the T-type gate electrode; and a mold protection film further formed on a surface of the insulation film, a pinhole is formed as the mold protection film. S with
The insulating film under the eaves of the T-type gate electrode is etched through the pinhole by exposing etching vapor from above the mold protection film using iN. Furthermore, the semiconductor device of the present invention
Eaves provided on the semiconductor substrate and protruding on both upper sides
A T-shaped gate electrode having a T-shaped cross section,
On both sides of the gate electrode and on the semiconductor substrate.
A source electrode and a drain electrode;
An SiO ₂ film formed so as to cover an upper portion, and the SiO ₂ film
And a mold protective film further formed on the surface of the
It is characterized in that a space is formed under the eaves of the T-type gate electrode.
Sign.

(Function) In the present invention, for example, the insulating film under the eaves of the gate electrode 3 is removed by using the selectivity for etching a solution such as BHF (buffered hydrofluoric acid) or a vapor gas.

[0016]

(Embodiment 1) Embodiment 1 according to the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an FET in which the surface of a semiconductor 1 and a gate electrode 3 are passivated with a SiN film 2.

On the gate electrode 3, an SiN film as a first mold protection film 6 (a protection film for the mold) connects the drain electrode 5, the gate electrode 3 and the source electrode 4, and fixes them. Is formed. First
A normal pressure CVD (Chem)
Ial Vapor Deposition An abbreviation for chemical vapor deposition. SiO ₂ film 7 is formed by). Further, a second mold protection film 8 is formed on the upper layer of the SiO ₂ film 7 by normal pressure CVD.

Further, the passivation SiN film 2 and the first
Protection film 6, drain electrode 5 and gate electrode 3
A gap 9 exists between the passivation SiN film 2 and the first mold protection film 6 and between the gate electrode 3 and the source electrode 4. Furthermore, the SiO ₂ film, which is a thick insulating film near the gate electrode 3 under the eaves, has been removed, and the structure does not exist.

Next, the manufacturing process of the FET according to the first embodiment shown in FIG. 1 will be described.

The first process will be described with reference to FIG. As a first process, first, a first
Is applied to form a first resist film. The first resist film forms a first resist pattern by opening a first opening by, for example, electron beam exposure and performing development and baking. Next, a second resist having a different developing property from the first resist is applied on the first resist pattern,
A second resist film is formed. The second resist film also forms a resist pattern by, for example, opening the second opening by electron beam exposure or the like and performing a phenomenon, baking, or the like. Subsequently, for example, a gate metal is deposited by an evaporation method. Then, by the lift-off method,
The first and second resists are removed. Through the steps so far, the gate electrode 3 is formed on the semiconductor 1. Then, the surfaces of the semiconductor 1 and the gate electrode 3 are covered with the passivation film 2 (SiN).

It should be noted that the passivation film 2 is not limited to a single layer of SiN, but after passivation with SiO ₂ ,
It is also possible to use a multilayer film having SiN as an upper layer such as growing iN. Next, the second process shown in FIG. 2B will be described. On the surface of the passivation film 2 (SiN) formed in the first process, SiO ₂ is grown by about 15000 ° using plasma CVD or the like. Then, in order to flatten the SiO ₂ , a photoresist (PR) is applied to the entire surface. The above planarization etches back the photoresist (PR) and SiO ₂ by dry etching. At this time, FIG.
As shown in (1), the gate is caught, that is, the etch back is performed until the head of the gate is exposed. The photoresist (PR) is removed by the etch back. Next, as a third process, FIG.
As shown in FIG. 5, a source electrode 4 and a drain electrode 5 are formed. Photo-resist (PR) on planarized SiO ₂
Is applied, and portions of the source electrode 4 and the drain electrode 5 are exposed and developed to form openings. Photoresist (P
By injecting a hydrofluoric acid solution through the opening of R), the planarized SiO ₂ at the positions where the source electrode 4 and the drain electrode 5 are formed is removed. Thereafter, a metal for an electrode is deposited by, for example, an evaporation method. After that, the resist pattern is removed by a lift-off method or the like.
And a drain electrode 5 are formed. Since the method of forming the source electrode 4 and the drain electrode 5 is not directly related to the present invention, further description is omitted.

Next, the fourth process will be described with reference to FIG.
This will be described with reference to FIG. In the third process, the source electrode 4 and the drain electrode 5 were formed. Next, for example, plasma SiN or the like is deposited to cover the entire surface of the source electrode 4, the gate electrode 3, and the drain electrode 5, and a first mold protection film 6 is formed. The steps up to this point are the same as the steps of forming an ordinary mold-compatible FET except that the gate is located at the time of etch back.

Further, as a fifth process, the planarized SiO ₂ deposited near the gate electrode 3 under the eaves and deposited in the second process is removed. The fifth process will be described with reference to FIG.

First, in order to remove SiO ₂ under the eaves of the gate electrode 3, a hole is opened in a non-operating region at the tip of the finger. Then, buffered hydrofluoric acid (B
HF) or the like. The opening has a diameter of about 2 μm. The opening hole is masked using a photoresist (PR), and the first mold protection film 6 is opened by dry etching or the like.

After the photoresist (PR) is removed, SiO ₂ is etched from the opening using a BHF solution or BHF vapor. After removing the SiO ₂ , the substrate is washed with water and dried by baking or the like.

Here, in a BHF solution or the like, SiO ₂ is instantaneously etched, but SiN is etched only in a small amount. Therefore, the resist pattern on the gate electrode 3 remains without being removed. This is for BHF solution etc.
SiO ₂ is easy to etch it, SiN is because there is a selectivity that it is difficult to etch. That is, S
Utilizing the difference between the etching rates of iN and SiO ₂ ,
The insulating film is removed.

The vicinity of the gate electrode 3 is entirely covered with SiN. The first mold protection film 6 is also made of SiN. Therefore, these are removed only by SiO ₂ near the gate electrode 3 under the eaves without being etched by BHF.

Next, the sixth process will be described with reference to FIG. FIG. 4 is a sectional view corresponding to the opening AA ′.

This process is a step for filling the opening hole. In order to fill the opening hole, first, SiO ₂ is deposited thickly using normal pressure CVD with low coverage. S
iO ₂ does not penetrate deep into the gap 9 due to normal pressure CVD having low coverage. Actually, holes are buried when piled up more than 5000 mm. And then,
The second mold protection film 8 covers the SiO ₂ deposited at normal pressure CVO.

Therefore, by performing the above-described first to sixth processes, the SiO ₂ under the eaves of the gate electrode 3 can be removed while protecting the gate electrode 3. That is, the capacitance of the gate electrode 3 can be reduced, and the RF characteristics can be improved.

(Embodiment 2) In Embodiment 2 of the present invention,
The removal of SiO ₂ near the lower part of the eave of the gate electrode 3 is realized without forming the opening hole for injecting BHF used in the first embodiment. The manufacturing process will be described below with reference to FIG. Note that the processes in the present embodiment are the same up to the third process shown in FIG. 2D of the first embodiment, so the description up to the third process is omitted, and the fourth process is repeated. explain.

The fourth process will be described with reference to FIG. As a fourth process, for example, plasma SiN or the like is deposited on the surfaces of the source electrode 4, the gate electrode 3, the drain electrode 5, and the photoresist (PR). Then, plasma SiN of the first mold protection film 6 is formed on the surface of the gate electrode 3 and the like. At that time, the plasma S
The growth condition of iN is changed so that a pinhole is easily formed in the first mold protection film 6.

Here, in order to easily form a pinhole in the first mold protection film 6, the nitrogen (N) of SiN is insufficient. Normally, plasma SiN is obtained by mixing silane gas SiH ₄ and ammonia NH ₃ at a ratio of 1: 1 and reacting with plasma to grow SiN.

Therefore, in order to easily generate pinholes, the mixture ratio of SiH ₄ : NH ₃ is increased to 2: 1 or more to increase the amount of SiH ₄ , thereby deficient nitrogen (N) in the plasma SiN. As a result, pinholes are easily generated in the grown SiN.

In the present embodiment, the SiN of the first mold protection film 6 shown in FIG. 6A is made of SiN in which a pinhole is easily formed only when the first mold protection film 6 is grown.
N was used. Specifically, SiN was grown at a mixing ratio of SiH ₄ : NH ₃ = 3: 1.

Next, a fifth process will be described with reference to FIG. The surface of the first mold protection film 6 is exposed to BHF vapor or the like. BHF vapor penetrates and etches the underlying SiO ₂ through SiN pinholes. Here, as in the first embodiment,
Since BHF vapor has selectivity for etching of SiO ₂ and SiN, it does not affect the gate or semiconductor surface covered with SiN. Therefore, the gate electrode 3
The SiO ₂ can be removed near the bottom of the eaves.

Thereafter, by the above-described etching, Si
After removing O ₂ , water washing is performed. Then, for example, baking is performed at a temperature of 110 ° C. for 24 hours in order to evaporate water remaining in the void 9 from which SiO ₂ has been removed.

The sixth process will be described with reference to FIG. As a sixth process, after the above-described baking, the second mold protection film 8 is grown under the condition that no pinhole is generated. That is, a material having a mixture ratio of SiH ₄ : NH ₃ of 1: 1 is used.

When the first to sixth processes as described above are performed, the SiO ₂ under the eaves of the gate electrode 3 can be removed while protecting the gate electrode 3 as in the first embodiment. Therefore, the RF characteristics can be improved.

In this embodiment, the number of PR steps, the number of opening steps, and the number of atmospheric pressure CVD steps can be eliminated as compared with the first embodiment, so that the PR step and the like can be simplified. .

FIG. 5 shows the results of comparison between the FET according to the prior art and the FET according to the present invention in terms of high frequency characteristics. FIG. 5 shows a conventional FET which does not remove SiO ₂ near the eaves below the gate electrode and a FET according to the present invention.
2 shows the frequency characteristics of MSG / MAG by the small signal S-parameter analysis of FIG. These FETs are
Both have a finger length of 240 μm and a gate width of 2.88 mm.
It is.

According to the figure, the FET according to the present invention has improved gain. Further, the frequency at which MSG and MAG are switched (K> 1) is also longer in the present invention, and the cutoff frequency ft is increased.

Therefore, although the FET according to the present invention is mold-compatible, the generation of parasitic capacitance can be suppressed, and the FET can be used at a higher frequency than before.

According to the equivalent circuit analysis, the FET according to the present invention has a Cgd, C
gs are both reduced by about 15%. That is, since the parasitic capacitance between the source or drain electrode and the gate electrode can be reduced, the gain can be improved.

[0045]

As described above, according to the present invention,
While protecting the gate electrode 3 of the FET, the SiO ₂ under the eaves of the gate electrode 3 is removed, and a portion surrounded by the gate electrode 3, the drain electrode 5, the first mold protection film 6, and the passivation film 2 is a gap. 9 can be set. Therefore, the RF characteristics of the FET can be improved.

In a manufacturing process in which a pinhole is easily formed in the first mold protection film 6 and the first mold protection film 6 is exposed to BHF vapor, a PR process is used. Since the number, the number of opening steps, and the number of atmospheric pressure CVD steps can be reduced, the PR step and the like can be simplified.

Further, the FET according to the present invention can improve the gain as compared with the conventional FET. Therefore, although the FET according to the present invention is mold-compatible, generation of parasitic capacitance can be suppressed, and the FET can be used at a higher frequency than in the related art.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view of an FET according to Embodiments 1 and 2 of the present invention.

FIG. 2 is a manufacturing process diagram of a gate electrode according to Embodiments 1 and 2 of the present invention.

FIG. 3 is a sectional view of the FET showing an opening hole for BHF injection according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an opening hole for BHF injection according to the first embodiment of the present invention from above.

FIG. 5 shows an FET according to the present invention and an FET shown in the prior art.
FIG. 5 is a diagram comparing the RF characteristics of FIG.

FIG. 6 is a manufacturing process diagram of the gate electrode according to the second embodiment of the present invention.

FIG. 7 is a configuration sectional view of a conventional FET.

FIG. 8 is a configuration sectional view of a conventional FET.

[Explanation of symbols]

1 semiconductor substrate 2 passivation film 3 gate electrode 4 a source electrode 5 drain electrode 6 first mold protective film 7 SiO ₂ film 8 by atmospheric pressure CVD second mold protective film 9 voids 11 compound semiconductor 12 insulating film 13 opening 14 T -Shaped gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 29/778 H01L 29/80-29/812

Claims (5)

(57) [Claims] 1. A T-shaped gate electrode having a T-shaped cross section and provided on a semiconductor substrate and having eaves protruding on both upper sides, and provided on both sides of the T-shaped gate electrode and on the semiconductor substrate. A source electrode and a drain electrode;
And SiO ₂ film formed so as to cover the upper portion of the mold gate electrode, a manufacturing method of the SiO ₂ film semiconductor device having further formed a mold protective film on the surface of a flat the SiO ₂ film To expose the head of the gate electrode, form a mold protection film on the SiO ₂ film and the T-type gate electrode, open an opening for injecting an etchant into the mold protection film, The etching liquid is injected from a hole to etch the SiO ₂ film under the eaves of the T-type gate electrode, so that a space is formed under the eaves of the T-type gate electrode. Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, after the etching, the SiO ₂ film is deposited using CVD to close the opening. 3. A T-shaped gate electrode having a T-shaped cross section provided on a semiconductor substrate and having eaves protruding on both upper sides, and provided on both sides of the T-shaped gate electrode and on the semiconductor substrate. A source electrode and a drain electrode;
A semiconductor device comprising: an insulating film formed so as to cover a mold gate electrode; and a mold protection film further formed on a surface of the insulating film, wherein the mold protection film is formed of SiN having a pinhole, A method of manufacturing a semiconductor device, comprising: exposing an etching vapor from above a mold protective film to etch the insulating film under the eaves of the T-type gate electrode through the pinhole. 4. The method for manufacturing a semiconductor device according to claim 3, wherein after the etching, the mold protection film is formed so as to cover a mold protection film having no pinhole from above the mold protection film. 5. An Si film using SiO ₂ as the insulating film, a SiN film as the mold protection film, and a buffered hydrofluoric acid vapor as the etching vapor.
5. The method for manufacturing a semiconductor device according to claim 3, wherein the insulating film is removed by utilizing a difference between etching rates of O ₂ and SiN.