JP3019446B2 - High frequency semiconductor device - Google Patents

High frequency semiconductor device

Info

Publication number
JP3019446B2
JP3019446B2 JP3063360A JP6336091A JP3019446B2 JP 3019446 B2 JP3019446 B2 JP 3019446B2 JP 3063360 A JP3063360 A JP 3063360A JP 6336091 A JP6336091 A JP 6336091A JP 3019446 B2 JP3019446 B2 JP 3019446B2
Authority
JP
Japan
Prior art keywords
semiconductor device
space
electrode
frequency semiconductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3063360A
Other languages
Japanese (ja)
Other versions
JPH04298047A (en
Inventor
光啓 比嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3063360A priority Critical patent/JP3019446B2/en
Publication of JPH04298047A publication Critical patent/JPH04298047A/en
Application granted granted Critical
Publication of JP3019446B2 publication Critical patent/JP3019446B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、高周波用半導体装
置、特に電極間の寄生容量を減少せしめたFET等の高
周波用半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor device, and more particularly to a high-frequency semiconductor device such as an FET having a reduced parasitic capacitance between electrodes.

【0002】[0002]

【従来の技術】高周波用半導体装置、例えばバイポーラ
トランジスタの製造過程において、コレクタ、ベース、
エミッタ(電界効果トランジスタ:FETの場合はソー
ス、ゲート、ドレイン)の各電極を半導体基板上に形成
した後、通常トランジスタの動作領域部が絶縁膜で被覆
され、上記各電極間が埋没してしまう。
2. Description of the Related Art In the process of manufacturing a high-frequency semiconductor device, for example, a bipolar transistor, a collector, a base,
After each electrode of an emitter (field effect transistor: source, gate, drain in the case of FET) is formed on a semiconductor substrate, the operation region of the transistor is usually covered with an insulating film, and the space between the electrodes is buried. .

【0003】このようなトランジスタの製造工程で用い
られる絶縁膜としては、特に金属配線層を形成する過程
における層間絶縁膜やオーバーコート用の絶縁膜等があ
げられる。
As an insulating film used in the process of manufacturing such a transistor, an interlayer insulating film in the process of forming a metal wiring layer, an insulating film for overcoating, and the like can be given.

【0004】[0004]

【発明が解決しようとする課題】これらの絶縁膜が電極
間を全て埋めることにより、ベース電極〜エミッタ電極
(FETの場合ゲート電極〜ソース電極)及びベース電
極〜コレクタ電極(FETの場合ゲート電極〜ドレイン
電極)のそれぞれの電極間で寄生容量が増大して高周波
特性が劣化する。
These insulating films completely fill the gaps between the electrodes, so that the base electrode to the emitter electrode (gate electrode to source electrode in the case of FET) and the base electrode to collector electrode (gate electrode to gate electrode in the case of FET). The parasitic capacitance increases between the respective electrodes (drain electrode), and the high-frequency characteristics deteriorate.

【0005】特に、ベース電極〜コレクタ電極(FET
の場合ゲート電極〜ドレイン電極)間の寄生容量が増大
すると帰還容量が増大し、ゲインの低下を招いた。
In particular, a base electrode to a collector electrode (FET)
In the case (2), when the parasitic capacitance between the gate electrode and the drain electrode) increases, the feedback capacitance increases, resulting in a decrease in gain.

【0006】本発明は、高周波特性を劣化させる寄生容
量を低減した高周波用半導体装置を提供することを目的
とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency semiconductor device in which a parasitic capacitance that deteriorates high-frequency characteristics is reduced.

【0007】[0007]

【課題を解決するための手段】上記課題は本発明によれ
ば、半導体基板表面に形成された電極同士の対向間隙内
に寄生容量防止用空間と、前記電極上方に形成された対
向する層間絶縁膜同士間及び該層間絶縁膜上に形成され
た対向する被覆絶縁膜同士間に前記空間と連通する空間
とを有することを特徴とする高周波用半導体装置によっ
て解決される。
According to the present invention, a space for preventing parasitic capacitance is provided in an opposing gap between electrodes formed on the surface of a semiconductor substrate, and an opposing interlayer insulation formed above the electrodes. The problem is solved by a high-frequency semiconductor device having a space communicating with the space between the films and between the opposing covering insulating films formed on the interlayer insulating film.

【0008】[0008]

【作用】本発明によれば、電極間同士の対向間隙を空間
(空気を介在)としているため、従来絶縁膜で被覆され
ていた場合よりも寄生容量を低下させることができる。
また、電極上方にも上記空間と連通する空間があるた
め、トランジスタの動作部上が絶縁膜で埋没されず、上
記作用をより助長することができる。
According to the present invention, since the opposing gap between the electrodes is a space (air is interposed), the parasitic capacitance can be reduced as compared with the conventional case where the electrode is covered with an insulating film.
In addition, since there is a space above the electrode that communicates with the space, the operation portion of the transistor is not buried in the insulating film, and the above operation can be further promoted.

【0009】本発明で用いられる高周波用半導体装置と
しては、バイポーラトランジスタ、FET等があげられ
る。
The high-frequency semiconductor device used in the present invention includes a bipolar transistor, an FET and the like.

【0010】[0010]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図1は本発明に係る高周波用半導体装置の
一実施例を示す断面図である。
FIG. 1 is a sectional view showing an embodiment of a high-frequency semiconductor device according to the present invention.

【0012】図1において、1は例えばGaAsからな
る半導体基板、2はソース電極、3はゲート電極、4は
ドレイン電極、5は例えば窒化珪素SiNからなる保護
膜、7a,7bは例えばSiOあるいはSiNからなる
層間絶縁膜、8aは例えばTi/Auからなる上層配
線、9a,9bは例えばSiNあるいはSiO等からな
る被覆絶縁膜である。図1において半導体基板1表面に
形成されたソース電極2とゲート電極3の対向間隙に空
間A及びゲート電極3とドレイン電極4の対向間隙に空
間Bを有し、しかも各電極上方に形成された対向する層
間絶縁膜7a,7b間及び対向する被覆絶縁膜9a,9
b間の空間Cが上記空間A,Bと連続した空間を構成し
ている。
In FIG. 1, 1 is a semiconductor substrate made of, for example, GaAs, 2 is a source electrode, 3 is a gate electrode, 4 is a drain electrode, 5 is a protective film made of, for example, silicon nitride SiN, and 7a and 7b are, for example, SiO or SiN. Is an upper layer wiring made of, for example, Ti / Au, and 9a and 9b are coating insulating films made of, for example, SiN or SiO. In FIG. 1, a space A is formed in the gap between the source electrode 2 and the gate electrode 3 formed on the surface of the semiconductor substrate 1, and a space B is formed in the gap between the gate electrode 3 and the drain electrode 4 formed above the electrodes. Between the opposing interlayer insulating films 7a and 7b and the opposing covering insulating films 9a and 9
The space C between the points b and b forms a space continuous with the above-mentioned spaces A and B.

【0013】図2、図3及び図4は図1に示した本発明
に係る高周波用半導体装置を得るための製造方法の一実
施例を説明するための一連の工程図であり、図1と同一
符号は同一部分を示す。
FIG. 2, FIG. 3, and FIG. 4 are a series of process charts for explaining one embodiment of a manufacturing method for obtaining the high-frequency semiconductor device according to the present invention shown in FIG. The same reference numerals indicate the same parts.

【0014】まず、図2(a)に示すように、GaAs
からなる半導体基板1上に通常通り例えばAlからなる
厚さ3000オングストロームのソース電極2、厚さ5
000オングストロームのゲート電極3、厚さ3000
オングストロームのドレイン電極4を形成し、次に、図
2(b)に示すように露出面全面に厚さ500オングス
トロームの薄い窒化珪素(SiN)からなる保護膜5を
CVD(化学的気相成長)法により形成する。
First, as shown in FIG.
A 3000 .ANG. Thick source electrode 2 of, for example, Al on a semiconductor substrate 1 of
3,000 angstroms gate electrode 3, thickness 3000
An Å drain electrode 4 is formed, and then a protective film 5 made of thin silicon nitride (SiN) having a thickness of 500 Å is formed on the entire exposed surface as shown in FIG. 2B by CVD (chemical vapor deposition). It is formed by a method.

【0015】次に、図2(c)の如く、スピンコート法
によりレジスト6を全面に塗布し、図2(d)に示した
所定の領域を残して動作部保護膜を構成するレジストパ
ターン6aを形成する。図2(c)において、レジスト
6の代わりにSiOあるいはポリイミド等でも可能であ
る。
Next, as shown in FIG. 2C, a resist 6 is applied to the entire surface by a spin coating method, and a resist pattern 6a constituting an operating portion protective film except for a predetermined region shown in FIG. 2D. To form In FIG. 2C, instead of the resist 6, SiO or polyimide may be used.

【0016】レジストパターン6aを形成した後、図3
(a)に示すように厚さ約2000オングストロームの
SiOからなる層間絶縁膜7をCVD法により全面に形
成し、次に図3(b)に示すように、ソース電極2及び
ドレイン電極4上の保護膜5及び層間絶縁膜7の端部を
エッチング除去する。
After forming the resist pattern 6a, FIG.
As shown in FIG. 3A, an interlayer insulating film 7 made of SiO having a thickness of about 2,000 Å is formed on the entire surface by the CVD method, and then, as shown in FIG. The ends of the protective film 5 and the interlayer insulating film 7 are removed by etching.

【0017】次に、図3(c)に示すように、スパッタ
法により厚さ1.5μmのTi/Au(厚さ500オン
グストローム/1μm)からなる配線層8を形成し、次
に図3(d)に示すように配線層8の中央部をドライエ
ッチングにより除去して、上層配線8aを形成する。
Next, as shown in FIG. 3C, a wiring layer 8 made of Ti / Au (thickness: 500 Å / 1 μm) having a thickness of 1.5 μm is formed by a sputtering method. As shown in (d), the central part of the wiring layer 8 is removed by dry etching to form the upper wiring 8a.

【0018】次に、図4(a)に示すようにCVD法に
より厚さ約2000オングストロームのSiNからなる
被覆絶縁膜9を全面に被着する。
Next, as shown in FIG. 4A, a coating insulating film 9 made of SiN having a thickness of about 2000 Å is deposited on the entire surface by the CVD method.

【0019】次に、図4(b)及び図4(c)に順に示
すように、まず被覆絶縁膜9にリソグラフィ技術で溝1
0を形成して対向する被覆絶縁膜9a,9bを形成し、
続いて被覆絶縁膜9a,9bをマスクとして中央の層間
絶縁膜7を除去して層間絶縁膜7a,7bを形成し、更
にレジストパターン6aも除去し、図1に示した高周波
用半導体装置を得る。この半導体装置は、ソース電極2
とゲート電極3の間及びゲート電極3とドレイン電極4
の間には薄い保護膜5が形成されているのみで、その他
は全て除去され空間を形成し寄生容量も従来より減少さ
れる。この保護膜5はレジストあるいはその他ポリイミ
ドSiO等で作られる動作部保護膜6aを除去する際の
エッチングストッパとして作用し、半導体基板1を保護
する。
Next, as shown in FIG. 4 (b) and FIG. 4 (c), first, the groove 1 is formed in the coating insulating film 9 by lithography.
0 to form opposed covering insulating films 9a and 9b,
Subsequently, the interlayer insulating film 7 at the center is removed using the coating insulating films 9a and 9b as masks to form interlayer insulating films 7a and 7b, and the resist pattern 6a is further removed, thereby obtaining the high-frequency semiconductor device shown in FIG. . This semiconductor device has a source electrode 2
Between the gate electrode 3 and between the gate electrode 3 and the drain electrode 4
Between them, only a thin protective film 5 is formed, and all the others are removed to form a space, and the parasitic capacitance is reduced as compared with the conventional case. The protective film 5 functions as an etching stopper when removing the resist or the operating portion protective film 6a made of polyimide SiO or the like, and protects the semiconductor substrate 1.

【0020】[0020]

【発明の効果】以上説明したように、本発明によれば、
各電極間の寄生容量が減少するため、例えばゲイン(G
ain)等の高周波特性の劣化を防止できる。
As described above, according to the present invention,
Since the parasitic capacitance between the electrodes is reduced, for example, the gain (G
ain) can be prevented from deteriorating.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る高周波用半導体装置の一実施例を
示す断面図である。
FIG. 1 is a sectional view showing an embodiment of a high-frequency semiconductor device according to the present invention.

【図2】本発明に係る半導体装置の製造方法を説明する
ための前半の工程断面図である。
FIG. 2 is a first-half process cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

【図3】図2に示した工程に続く中間工程断面図であ
る。
FIG. 3 is an intermediate step sectional view following the step shown in FIG. 2;

【図4】図3に示した工程に続く後半工程断面図であ
る。
4 is a sectional view of the latter half of the step that follows the step of FIG.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 ソース電極 3 ゲート電極 4 ドレイン電極 5 保護膜 6 レジスト 6a レジストパターン 7,7a,7b 層間絶縁膜 8 配線層 8a 上層配線 9,9a,9b 被覆絶縁膜 10 溝 Reference Signs List 1 semiconductor substrate 2 source electrode 3 gate electrode 4 drain electrode 5 protective film 6 resist 6a resist pattern 7, 7a, 7b interlayer insulating film 8 wiring layer 8a upper wiring 9, 9a, 9b covering insulating film 10 groove

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/338 H01L 21/331 H01L 29/73 H01L 29/812 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/338 H01L 21/331 H01L 29/73 H01L 29/812

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板表面に形成された電極同士の
対向間隙内に寄生容量防止用空間と、前記電極上方に形
成された対向する層間絶縁膜同士間及び該層間絶縁膜上
に形成された対向する被覆絶縁膜同士間に前記空間と連
通する空間とを有することを特徴とする高周波用半導体
装置。
1. A parasitic capacitance preventing space in an opposing gap between electrodes formed on a surface of a semiconductor substrate, and a space formed between opposing interlayer insulating films formed above the electrodes and on the interlayer insulating film. A high-frequency semiconductor device comprising: a space communicating with the space between opposing covering insulating films.
JP3063360A 1991-03-27 1991-03-27 High frequency semiconductor device Expired - Fee Related JP3019446B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3063360A JP3019446B2 (en) 1991-03-27 1991-03-27 High frequency semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3063360A JP3019446B2 (en) 1991-03-27 1991-03-27 High frequency semiconductor device

Publications (2)

Publication Number Publication Date
JPH04298047A JPH04298047A (en) 1992-10-21
JP3019446B2 true JP3019446B2 (en) 2000-03-13

Family

ID=13227019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3063360A Expired - Fee Related JP3019446B2 (en) 1991-03-27 1991-03-27 High frequency semiconductor device

Country Status (1)

Country Link
JP (1) JP3019446B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3093487B2 (en) * 1992-10-28 2000-10-03 松下電子工業株式会社 Semiconductor device and manufacturing method thereof
JP5365062B2 (en) * 2008-05-07 2013-12-11 富士通株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH04298047A (en) 1992-10-21

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