JPH02268445A - Manufacture of field effect transistor - Google Patents

Manufacture of field effect transistor

Info

Publication number
JPH02268445A
JPH02268445A JP9000589A JP9000589A JPH02268445A JP H02268445 A JPH02268445 A JP H02268445A JP 9000589 A JP9000589 A JP 9000589A JP 9000589 A JP9000589 A JP 9000589A JP H02268445 A JPH02268445 A JP H02268445A
Authority
JP
Japan
Prior art keywords
recess
film
insulating film
window
temporary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9000589A
Other languages
Japanese (ja)
Inventor
Yukiko Yamaguchi
由紀子 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9000589A priority Critical patent/JPH02268445A/en
Publication of JPH02268445A publication Critical patent/JPH02268445A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce the series resistance by forming a shallow temporary recess, an insulating film, and ohmic electrodes, performing side etching, and etching a semiconductor base substance with the insulating film used as a mask to form a recess. CONSTITUTION:A photoresist film 3 is formed on a GaAs substrate 1, on which an active layer 2 is formed, and a window 3a is made. A shallower temporary recess 4 than a purposed recess is formed by wet etching through the window 3a. An oxide film 5 is formed, windows are made in ohmic electrode parts, and source and drain ohmic electrodes 6 are formed. A photoresist film 7 is applied, a window 7a is made, and then the film 5 is etched with the film 7 used as a mask. The substrate 1 is etched with the films 7 and 5 used as masks to form a recess 8. Gate metal 9 is adhered and the film 7 is removed to complete an FET. Thereby widening of the upper end of the recess is suppressed and the series resistance decreases.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明はリセス構造のME’S型電界効果トランジスタ
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a ME'S field effect transistor having a recessed structure.

〔従来の技術〕[Conventional technology]

従来、この種の電界効果トランジスタの製造方法は、第
3図に工程一部を示すように、活性層2を形成したGa
As基板1に絶縁膜5を選択形成し、この絶縁膜5を利
用してソース、ドレインの各オーミック電極6を形成す
る。また、前記絶縁膜5をゲート位置で開口するととも
に、この上に選択形成したフォトレジスト膜7をマスク
にGaAs1板1をエツチングしてリセス(凹部)8A
を形成し、かつこのフォトレジスト膜7を利用したリフ
トオフ法によ′リソセス8Aの底面上にゲート電極9を
形成している。
Conventionally, as shown in FIG. 3, a method for manufacturing a field effect transistor of this type has been carried out using a Ga film with an active layer 2 formed thereon.
An insulating film 5 is selectively formed on an As substrate 1, and each of the source and drain ohmic electrodes 6 is formed using this insulating film 5. Further, the insulating film 5 is opened at the gate position, and the GaAs 1 plate 1 is etched using the photoresist film 7 selectively formed thereon as a mask to form a recess (concave portion) 8A.
A gate electrode 9 is formed on the bottom surface of the recess 8A by a lift-off method using this photoresist film 7.

〔発明が解決しようとする課題] 上述した従来の製造方法では、リセスを形成する際の絶
縁膜5の開口時に、耐圧が小さくなる等の問題を防ぐた
めに、ある程度絶縁膜5をサイドエツチングすることが
行われている。このため、リセスが深くなってくると、
リセスの上端で幅が広がってしまう。
[Problems to be Solved by the Invention] In the conventional manufacturing method described above, when opening the insulating film 5 when forming a recess, it is necessary to side-etch the insulating film 5 to some extent in order to prevent problems such as a decrease in breakdown voltage. is being carried out. For this reason, when the recess becomes deep,
The width increases at the top of the recess.

したがって、MESFETにおけるシリーズ抵抗を低減
するためにソース側のオーミンク電極6とゲート電極9
との距離を小さく設計した場合には、リセス8Aがソー
ス側のオーミック電極6と干渉してしまうことがある。
Therefore, in order to reduce the series resistance in MESFET, the ohmink electrode 6 and gate electrode 9 on the source side are
If the distance between the recess 8A and the ohmic electrode 6 is designed to be small, the recess 8A may interfere with the ohmic electrode 6 on the source side.

このため、従来ではオーミック電極とゲート電極の距離
をある程度前して設計する必要があり、MESFETの
低抵抗化の障害になっている。
For this reason, conventionally it is necessary to design the distance between the ohmic electrode and the gate electrode to some extent, which is an obstacle to lowering the resistance of the MESFET.

本発明はシリーズ抵抗を低減し、かつ充分な耐圧を得る
ことができるMESFETの製造方法を提供することを
目的とする。
An object of the present invention is to provide a method for manufacturing a MESFET that can reduce series resistance and obtain sufficient breakdown voltage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のMESFETの製造方法は、先に半導体基板に
本来のリセスよりも浅い仮リセスを選択的に形成してお
き、その後絶縁膜を形成し、オーミック電極を形成した
後、この絶縁膜を仮リセス上でサイドエツチングし、か
つこの絶縁膜をマスクにして半導体基板を所定の深さに
までエツチングして本来のリセスを形成する工程を含ん
でいる。
In the MESFET manufacturing method of the present invention, a temporary recess shallower than the original recess is first selectively formed in the semiconductor substrate, an insulating film is formed, an ohmic electrode is formed, and this insulating film is temporarily recessed. This process includes the steps of performing side etching on the recess, and using this insulating film as a mask, etching the semiconductor substrate to a predetermined depth to form the original recess.

〔作用〕[Effect]

この製造方法では、仮リセスから本来のリセスを形成す
る際のサイドエツチング量を極めて少な(でき、リセス
の上端が横に広がることを抑制し、ゲート電極とオーミ
ック電極との距離を小さくしてシリーズ抵抗を低減させ
る。同時にゲートとリセス端の距離を仮リセスの位置に
よって決めることができ、ゲート耐圧を任意に制御する
ことが可能となる。
With this manufacturing method, the amount of side etching when forming the original recess from the temporary recess is extremely small. The resistance is reduced.At the same time, the distance between the gate and the recess edge can be determined by the position of the temporary recess, making it possible to arbitrarily control the gate breakdown voltage.

(実施例〕 次に、本発明を図面を参照して説明する。(Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明方法により製造したMESFETの断面
図であり、その製造方法を第2図(a)乃至(C’)に
工程順に示している。
FIG. 1 is a sectional view of a MESFET manufactured by the method of the present invention, and the manufacturing method is shown in the order of steps in FIGS. 2(a) to (C').

先ず、第2図(a)のように、活性層2を形成したG 
a A s基板1上にフォトレジスト膜3を形成し、か
つこれをパターン形成して窓3aを開設する。そして、
この窓3aを通して前記GaAs基板1をウェットエツ
チングして仮リセス4を形成する。このとき、仮リセス
4は本来のリセス深さ(2000人)よりも浅(、例え
ば1500人の深さに形成している。
First, as shown in FIG. 2(a), G
A photoresist film 3 is formed on the aAs substrate 1 and patterned to form a window 3a. and,
A temporary recess 4 is formed by wet etching the GaAs substrate 1 through this window 3a. At this time, the temporary recess 4 is formed to be shallower (for example, 1500 depths) than the original recess depth (2000 depths).

次いで、第2図(b)のように、全面にCVD法等によ
り酸化膜5を形成し、オーミック電極部位に窓を開設す
る。そして、この酸化膜5上にオーミック金属を蒸着し
、かつ選択的に除去することでソース、ドレインの各オ
ーミック電極6を形成する。続いて、全面にフォトレジ
スト膜7を塗布し、かつ前記仮リセス4の上においてゲ
ート電極形成箇所に窓7aを開設する。そして、このフ
ォトレジスト膜7をマスクにして、例えばバッフアート
弗酸により前記酸化膜5をエツチングする。
Next, as shown in FIG. 2(b), an oxide film 5 is formed on the entire surface by CVD or the like, and a window is formed at the ohmic electrode portion. Then, ohmic metal is deposited on this oxide film 5 and selectively removed to form source and drain ohmic electrodes 6. Subsequently, a photoresist film 7 is applied to the entire surface, and a window 7a is opened above the temporary recess 4 at the location where the gate electrode is to be formed. Then, using this photoresist film 7 as a mask, the oxide film 5 is etched using, for example, buffered hydrofluoric acid.

このとき、酸化膜5はフォトレジスト膜7の窓7aの外
側に向けてサイドエツチングされる。
At this time, the oxide film 5 is side-etched toward the outside of the window 7a of the photoresist film 7.

次に、第2図(C)のように、前記フォトレジスト膜7
及び酸化膜5をマスクにしてGaAs基板1をエツチン
グし、本来の深さのリセス8を形成する。このとき、リ
セス8のエツチング量は僅かであるため、酸化膜5の下
側のサイドエツチング量は極めて僅かとなる。
Next, as shown in FIG. 2(C), the photoresist film 7
Then, using the oxide film 5 as a mask, the GaAs substrate 1 is etched to form a recess 8 of the original depth. At this time, since the amount of etching of the recess 8 is small, the amount of side etching on the lower side of the oxide film 5 is extremely small.

そして、全面にゲート金属9を被着し、その後フォトレ
ジスト膜7を除去することで、第1図に示したように、
所謂リフトオフ法によりリセス8の底面にゲート電極9
を形成し、MESFETが完成される。
Then, by depositing the gate metal 9 on the entire surface and then removing the photoresist film 7, as shown in FIG.
A gate electrode 9 is formed on the bottom surface of the recess 8 by a so-called lift-off method.
is formed to complete the MESFET.

したがって、この製造方法では、最初に仮リセス4を形
成した後に、この仮リセス4の外側にオーミック電極6
を形成し、かつその後にサイドエツチングが極めて僅か
なエツチングにより本来のリセス8を形成しているため
、リセス8とオーミック電極6との距離を小さくした場
合でも、リセス8とオーミック電極6が干渉しないME
SFETが形成できる。これにより、オーミック電極6
とリセス8との距離を小さくした設計が可能となり、ソ
ース側のシリーズ抵抗を低減させたMESFETが構成
できる。
Therefore, in this manufacturing method, after first forming the temporary recess 4, the ohmic electrode 6 is placed outside the temporary recess 4.
, and then the original recess 8 is formed by very slight side etching, so even if the distance between the recess 8 and the ohmic electrode 6 is reduced, the recess 8 and the ohmic electrode 6 do not interfere with each other. M.E.
SFET can be formed. As a result, the ohmic electrode 6
It becomes possible to design the distance between the recess 8 and the recess 8, and a MESFET with reduced series resistance on the source side can be constructed.

また、仮リセス4の状態から本来のリセス8を形成する
際のサイドエツチングが極めて少ないことから、リセス
ゲート端を仮リセス4の底面位置で決定でき、ゲート耐
圧を任意に制御することも可能となる。したがって、ゲ
ート耐圧を容易に増大することが可能である。
Furthermore, since there is extremely little side etching when forming the original recess 8 from the state of the temporary recess 4, the recess gate end can be determined by the bottom surface position of the temporary recess 4, and the gate withstand voltage can be controlled arbitrarily. . Therefore, it is possible to easily increase the gate breakdown voltage.

〔発明の効果] 以上説明したように本発明は、先に浅い仮リセスを選択
的に形成しておき、その後オーミック電極を形成した上
で、仮リセス上に形成した絶縁膜をマスクにして本来の
リセスをエツチング形成しているので、仮リセスから本
来のリセスを形成する際のサイドエツチング量を小さく
してリセスの上端が横に広がることを抑制し、ゲート電
極とオーミック電極との距離を小さくした設計を可能に
してシリーズ抵抗を低減したMESFETを製造できる
[Effects of the Invention] As explained above, the present invention first selectively forms a shallow temporary recess, then forms an ohmic electrode, and then uses the insulating film formed on the temporary recess as a mask to perform the original process. Since the recess is formed by etching, the amount of side etching is reduced when forming the actual recess from the temporary recess, suppressing the upper end of the recess from spreading laterally, and reducing the distance between the gate electrode and the ohmic electrode. MESFETs with reduced series resistance can be manufactured.

また、前記サイドエンチングを抑制することにより、本
来のリセスの端を仮リセスの端に略一致させ、これによ
りゲートとリセス端の距離を仮リセスの位置によって決
めることができ、ゲート耐圧を任意に制御したMESF
ETを製造することができる効果もある。
In addition, by suppressing the side etching, the end of the original recess can be made to approximately coincide with the end of the temporary recess, which allows the distance between the gate and the recess end to be determined by the position of the temporary recess, and the gate withstand voltage can be adjusted arbitrarily. MESF controlled by
There is also the effect that ET can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法で製造したMESFETの断面図、
第2図(a)乃至(C)は第1図のMESFETの製造
方法を工程順に示す断面図、第3図は従来の製造方法の
工程一部を示す断面図である。 1・・・GaAs基板、2・・・活性層、3・・・フォ
トレジスト膜、4・・・仮リセス、5・・・酸化膜、6
・・・オーミック電極、7・・・フォトレジスト膜、8
,8A・・・リセス、9・・・ゲート電極。 弔 図 第2 図 第3 図
FIG. 1 is a cross-sectional view of a MESFET manufactured by the method of the present invention,
2(a) to 2(C) are cross-sectional views showing the manufacturing method of the MESFET shown in FIG. 1 in the order of steps, and FIG. 3 is a cross-sectional view showing a part of the steps of the conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... GaAs substrate, 2... Active layer, 3... Photoresist film, 4... Temporary recess, 5... Oxide film, 6
... Ohmic electrode, 7... Photoresist film, 8
, 8A... Recess, 9... Gate electrode. Funeral map Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、活性層を形成した半導体基板に本来のリセスよりも
浅い仮リセスを選択的に形成する工程と、全面に絶縁膜
を形成しかつこの絶縁膜を利用して前記仮リセスの外側
にオーミック電極を形成する工程と、前記絶縁膜上にフ
ォトレジスト膜を形成しかつこのフォトレジスト膜のゲ
ート電極形成箇所に窓を開設する工程と、該フォトレジ
スト膜の窓を通して前記絶縁膜をサイドエッチングする
工程と、この絶縁膜をマスクに前記半導体基板を所定の
深さにまでエッチングして本来のリセスを形成する工程
と、全面にゲート電極を被着しかつ前記フォトレジスト
膜を用いたリフトオフ法により前記リセス底面にゲート
電極を選択形成する工程とを含むことを特徴とする電界
効果トランジスタの製造方法。
1. A step of selectively forming a temporary recess shallower than the original recess in the semiconductor substrate on which the active layer has been formed, and forming an insulating film on the entire surface and using this insulating film to form an ohmic electrode on the outside of the temporary recess. a step of forming a photoresist film on the insulating film and opening a window in the photoresist film at a location where the gate electrode is to be formed; and a step of side etching the insulating film through the window of the photoresist film. Then, using this insulating film as a mask, the semiconductor substrate is etched to a predetermined depth to form the original recess, and a gate electrode is deposited on the entire surface, and a lift-off method using the photoresist film is used to etch the semiconductor substrate to a predetermined depth. A method for manufacturing a field effect transistor, comprising the step of selectively forming a gate electrode on the bottom of the recess.
JP9000589A 1989-04-10 1989-04-10 Manufacture of field effect transistor Pending JPH02268445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9000589A JPH02268445A (en) 1989-04-10 1989-04-10 Manufacture of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9000589A JPH02268445A (en) 1989-04-10 1989-04-10 Manufacture of field effect transistor

Publications (1)

Publication Number Publication Date
JPH02268445A true JPH02268445A (en) 1990-11-02

Family

ID=13986503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9000589A Pending JPH02268445A (en) 1989-04-10 1989-04-10 Manufacture of field effect transistor

Country Status (1)

Country Link
JP (1) JPH02268445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19952304C2 (en) * 1998-10-29 2002-04-04 Murata Manufacturing Co oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19952304C2 (en) * 1998-10-29 2002-04-04 Murata Manufacturing Co oscillator

Similar Documents

Publication Publication Date Title
JP2778600B2 (en) Method for manufacturing semiconductor device
US4222164A (en) Method of fabrication of self-aligned metal-semiconductor field effect transistors
US4700455A (en) Method of fabricating Schottky gate-type GaAs field effect transistor
JPH0260216B2 (en)
JPH03248439A (en) Manufacture of compound semiconductor device
JPH118256A (en) Manufacture of field-effect transistor
JPH02268445A (en) Manufacture of field effect transistor
JP2518402B2 (en) Method for manufacturing semiconductor device
JP2853940B2 (en) Method for manufacturing semiconductor device
JPH0323643A (en) Semiconductor device and manufacture thereof
JP3035994B2 (en) Method for manufacturing semiconductor device
JP2893776B2 (en) Method for manufacturing semiconductor device
JPS6112079A (en) Manufacture of semiconductor element
JPH04186640A (en) Manufacture of semiconductor device
JPS62115782A (en) Manufacture of semiconductor device
JPH03145738A (en) Formation of gate electrode
JPS6276780A (en) Manufacture of semiconductor device
JPH01199473A (en) Manufacture of field-effect transistor
JPH0831844A (en) Fabrication of semiconductor device
JPH04162635A (en) Manufacture of semiconductor device
JP3032458B2 (en) Method for manufacturing field effect transistor
JPH02262342A (en) Manufacture of semiconductor device
JPS6151979A (en) Manufacture of semiconductor device
JPH02180032A (en) Manufacture of gaas mesfet
JPH05275455A (en) Semiconductor device and its manufacture