JPH10256532A - Compound semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dissipation power by narrowing a width of a channel layer without influence of a lithography limit and eliminating a parallel conduction. SOLUTION: An ohmic electrode 5 and dummy electrode 6 provided on a second one conductivity type semiconductor layer 4 are selfaligned with a laminated structure having at least first one conductivity type semiconductor layer 2, a non-doped semiconductor layer 3 and a second one conductivity type semiconductor layer 4, and two stripe-like grooves 7 formed of crystal plane of the same crystal orientation at its sidewall are provided. At least a gate electrode 10 is provided via a gate barrier layer 9 provided on a surface of the groove 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly to a HEMT.
(1) Field of the Invention The present invention relates to a vertical compound semiconductor device having operating characteristics of a (high electron mobility transistor) and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, compound semiconductor devices for high-speed operation, mainly GaAs-based compound semiconductors, have been used for high-frequency communication at microwaves or higher. In particular, two-dimensional carrier gas caused by heterojunction, especially A HEMT utilizing a two-dimensional electron gas is typical.

In recent years, there has been a demand for such high-speed operation compound semiconductor devices to have lower power consumption and higher operation speed. To meet such demands, the channel length of the element, That is, it is very effective to shorten the gate length.

However, in a conventional fine gate FET (field effect transistor) device, the limit of shortening the gate length is determined by the extent to which a gate electrode having a short gate length can be formed by lithography. It was difficult to shorten the channel length.

Therefore, a vertical field-effect transistor has been proposed to solve such a problem of the limitation of lithography. This vertical field-effect transistor will be described with reference to FIG.

Referring to FIG. 10, this conventional vertical field effect transistor uses a semi-insulating Ga.
An n ⁺ -type GaAs serving as a source-side semiconductor layer is formed on an As substrate 61 by MOVPE (metal organic chemical vapor deposition).
A layer 62, an i-type GaAs layer 63 serving as a channel layer, and
An n ⁺ -type GaAs layer 64 serving as a drain-side semiconductor layer is sequentially epitaxially grown.

Then, n ⁺ -type GaAs is etched by etching.
After the step portion is formed by exposing the s layer 62, an i-type AlGaAs layer 65 serving as a gate barrier layer is grown on the entire surface, a gate electrode 66 is formed on the step portion, and n ⁺
A drain electrode 67 and a source electrode 68 are formed on the n-type GaAs layer 64 and the n ⁺ -type GaAs layer 62, respectively.

In this case, the channel length is almost i-type GaAs.
Since the thickness is determined by the thickness of the s layer 63, the thickness is determined by the crystal growth accuracy without depending on the lithography limit, and a channel length on the order of several tens of nm is possible.

In this case, a two-dimensional electron gas (2DEG) 69 is formed at the interface due to a difference in electron affinity between the i-type AlGaAs layer 65 and the i-type GaAs layer 63. High-speed operation using the gas 69 is performed.

[0010]

However, in such a vertical field-effect transistor, a current flowing independently of the gate voltage, that is, a parallel current, rather than a current caused by the two-dimensional electron gas 69 modulated by the gate voltage. Since the conduction 70 increases, there is a problem that current does not disappear between the source and the drain even when a negative voltage is applied to the gate electrode 66, that is, when the gate electrode 66 is in an off state, and power consumption increases.

In order to solve such a problem of the parallel conductor 70, oxygen or the like is ion-implanted so as to leave a region where the two-dimensional electron gas 69 is formed, thereby insulating a portion where the parallel conductor 70 occurs. However, there is a limit in the accuracy of lithography alignment with respect to a small region for ion implantation, and it is very difficult to insulate with good reproducibility for each wafer.

Accordingly, an object of the present invention is to eliminate the parallel conduction without being affected by the lithography limit, to obtain the operating characteristics as designed, and to reduce the power consumption.

[0013]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1. (1) The present invention relates to a compound semiconductor device having a stacked structure including at least a first one-conductivity-type semiconductor layer 2, a non-doped semiconductor layer 3, and a second one-conductivity-type semiconductor layer 4. Two stripe-shaped grooves 7 which are self-aligned with the ohmic electrode 5 and the dummy electrode 6 provided on the second one-conductivity-type semiconductor layer 4 and whose side walls are formed of crystal planes having the same crystal orientation. In addition, a gate electrode 10 is provided via a gate barrier layer 9 provided at least on the surface of the groove 7 to generate a two-dimensional carrier gas 11 at an end of the non-doped semiconductor layer 3.

As described above, the width x of the channel layer 8 of the vertical field effect transistor can be reduced by using the two stripe-shaped grooves 7 whose side walls are formed of the same crystal plane having the same crystal orientation. , The width of the drain electrode or the source electrode, and the width of the drain electrode or the source electrode is set to such a length that the channel layer 8 is depleted from both sides when a negative bias is applied to the gate electrode 10. As a result, parallel conduction can be eliminated, and lower power consumption can be achieved in an element having the same channel length as in the related art.

(2) The present invention relates to a compound semiconductor device having a laminated structure comprising at least a first one conductivity type semiconductor layer 2, a non-doped semiconductor layer 3, and a second one conductivity type semiconductor layer 4. Two stripe-shaped grooves 7 whose side walls are formed of crystal planes having the same crystal orientation are provided at least at the surface of the grooves 7 in order to generate a two-dimensional carrier gas 11 at the end of the non-doped semiconductor layer 3. The gate electrode 10 is provided via the provided gate barrier layer 9, and extends over the insulating film provided on the surface of the gate electrode 10, and
An ohmic electrode 5 in contact with the one conductivity type semiconductor layer 4 is provided.

In this case, similar to the above (1), the parallel conduction can be eliminated, the power consumption can be reduced in a device having the same channel length as the conventional one, and the gate electrode 10 Providing an insulating film, extending over the insulating film, and forming a second one-conductivity-type semiconductor layer 4;
Since the ohmic electrode 5 is provided so as to be in contact with the ohmic electrode 5, the parasitic resistance on the ohmic electrode 5 side, that is, the series resistance can be reduced.

(3) According to the present invention, in the above (1) or (2), the groove 7 has a V-shaped cross section, and the tip of the groove 7 after the gate barrier layer 9 is provided. The position coincides with the interface between the first one conductivity type semiconductor layer 2 and the non-doped semiconductor layer 3.

With such a configuration, the parasitic capacitance caused by the gate electrode 10 can be reduced even when the gate electrode 10 is buried normally.

(4) In the present invention, in the above (1) or (2), the groove 7 has a V-shaped cross section, and the first one conductivity type semiconductor layer 2 and the non-doped semiconductor A non-doped semiconductor buried layer is provided at a height near an interface with the layer 3, and a gate electrode 10 is provided thereon.

With this configuration, the parasitic capacitance caused by the gate electrode 10 can be reduced irrespective of the positional relationship between the depth of the groove 7 and the non-doped semiconductor layer 3, and the gate electrode Since the cross-sectional area of 10 can be increased, the gate resistance can be reduced.

(5) According to the present invention, in the above (1), the cross-sectional shape of the groove 7 is an inverted mesa shape and the first one conductivity type semiconductor layer 2 and the non-doped semiconductor layer 3 It is characterized by having an etching stop layer of one conductivity type at the interface.

As described above, when the cross-sectional shape of the groove 7 is an inverted mesa shape, the narrow ohmic electrode 5 can form the narrow channel layer 8, so that the cutoff characteristic of the drain current can be reduced. Can be good, and
When the same width x of the channel layer 8 is formed, the parasitic resistance on the ohmic electrode 5 side can be reduced, and the width of the ohmic electrode 5 is controlled by the thickness of the second one conductivity type semiconductor layer 4. Can be.

(6) The present invention also provides a method of manufacturing a compound semiconductor device, comprising the steps of: providing a semi-insulating semiconductor substrate 1 with at least a first one conductivity type semiconductor layer 2; a non-doped semiconductor layer 3; A step of providing a laminated structure composed of two one-conductivity-type semiconductor layers 4; a stripe-shaped ohmic electrode 5 on the second one-conductivity-type semiconductor layer 4;
Forming a dummy electrode 6 in the form of a stripe facing the substrate, etching the laminated structure using the ohmic electrode 5 and the dummy electrode 6 as a mask, so as to be self-aligned with the ohmic electrode 5 and the dummy electrode 6, Forming a groove 7 composed of crystal planes having the same crystal orientation, providing a gate barrier layer 9 for generating a two-dimensional carrier gas 11 at least at the end of the non-doped semiconductor layer 3 on the surface of the groove 7, and And a step of burying the gate electrode 10 in the trench 7 to a height exceeding the interface between the non-doped semiconductor layer 3 and the second one conductivity type semiconductor layer 4.

As described above, by using the etching with the ohmic electrode 5 and the dummy electrode 6 as a mask,
Regardless of the lithography limit, the channel layer 8 having a narrow width x without parallel conduction can be formed in a self-aligned manner.

(7) According to the present invention, in the above (6), the groove 7 has a V-shaped cross section, and the position of the tip of the groove 7 after the gate barrier layer 9 is provided is the first position. The distance y between the ohmic electrode 5 and the dummy electrode 6 is adjusted so as to coincide with the interface between the one conductivity type semiconductor layer 2 and the non-doped semiconductor layer 3.
Is determined.

As described above, the ohmic electrode 5 and the dummy electrode 6
Is determined, the parasitic capacitance caused by the gate electrode 10 can be reduced even when the gate electrode 10 is buried normally.

(8) Further, according to the present invention, in the method for manufacturing a compound semiconductor device, at least the first one conductivity type semiconductor layer 2, the non-doped semiconductor layer 3, and the Providing a stacked structure composed of two one-conductivity-type semiconductor layers 4, forming a pattern in which stripe-shaped lines and stripe-shaped spaces are alternately arranged on the second one-conductivity-type semiconductor layer 4, and masking the pattern. Forming a groove 7 which is self-aligned to a stripe-shaped line and whose side wall is formed of a crystal plane having the same crystal orientation by etching the laminated structure, wherein at least the surface of the groove 7 has a non-doped semiconductor A step of providing a gate barrier layer 9 for generating a two-dimensional carrier gas 11 at an end of the layer 3, and a step of providing a non-doped semiconductor layer 3 and a second one conductivity type semiconductor layer 4 in a groove 7. Burying the gate electrode 10 to a height exceeding the interface of the gate electrode 10, providing an insulating film on the surface of the gate electrode 10, and removing the gate barrier layer 9 exposed on the surface of the multilayer structure surrounded by the groove 7 And providing an ohmic electrode 5 so as to cover at least the removed portion.

As described above, by using etching using a pattern in which stripe-shaped lines and stripe-shaped spaces are alternately arranged as a mask, regardless of the lithography limit, a narrow width x without parallel conduction can be obtained.
The channel layer 8 can be formed in a self-aligned manner, and the ohmic electrode 5 of an arbitrary size can be formed, so that the parasitic resistance can be reduced.

(9) According to the present invention, in the above (8), the cross-sectional shape of the groove 7 is V-shaped, and the position of the tip of the groove 7 after the gate barrier layer 9 is provided is the first position. The distance y between the stripe-shaped line and the stripe-shaped space is determined so as to coincide with the interface between the one conductivity type semiconductor layer 2 and the non-doped semiconductor layer 3.

With such a configuration, the parasitic capacitance caused by the gate electrode 10 can be reduced even when the gate electrode 10 is normally buried.

(10) In the present invention, in the above (6) or (8), the groove 7 has a V-shaped cross section, and after the gate barrier layer 9 is provided, the gate electrode 10 is embedded. Prior to the step, a non-doped semiconductor buried layer is selectively grown to near the interface between the first one-conductivity-type semiconductor layer 2 and the non-doped semiconductor layer 3.

With such a structure, the parasitic capacitance caused by the gate electrode 10 can be reduced irrespective of the positional relationship between the depth of the groove 7 and the non-doped semiconductor layer 3, and the gate electrode 10 Since the cross-sectional area of 10 can be increased, the gate resistance can be reduced.

(11) According to the present invention, in the above (6), the cross-sectional shape of the groove 7 is an inverted mesa shape and the first one conductivity type semiconductor layer 2 and the non-doped semiconductor layer 3 It is characterized by having an etching stop layer of one conductivity type at the interface.

In the case where the cross-sectional shape of the groove 7 is an inverted mesa, the narrow channel layer 8 can be formed by the wide ohmic electrode 5, so that the cutoff characteristic of the drain current is reduced. And when the same width x of the channel layer 8 is formed, the parasitic resistance on the ohmic electrode 5 side can be reduced, and the width of the ohmic electrode 5 is the second one conductivity type. The thickness can be controlled by the thickness of the semiconductor layer 4, and the position of the bottom surface of the groove 7 can be accurately controlled because the etching stop layer is provided, and the offset of the gate electrode 10 can be prevented.

(12) In the present invention, according to (11), after the gate barrier layer 9 is grown, ions are implanted into the bottom of the groove 7 to form a part of the first one-conductivity type semiconductor layer 2. Is insulated.

As described above, by partially insulating the first one-conductivity-type semiconductor layer 2, the parasitic capacitance between the gate electrode 10 and the first one-conductivity-type semiconductor layer 2 is greatly reduced. be able to.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a first embodiment of the present invention will be described.
The state will be described with reference to FIGS. Referring to FIG. 2A, first, a semi-insulating GaAs substrate having a (100) plane as a main surface.
MOVPE (metal organic chemical vapor deposition)
And the impurity concentration is 1 × 10¹⁸~ 1 × 10¹⁹cm ^-3,example
5 × 10¹⁸cm^-3With a thickness of 10 to 1000 nm,
For example, n of 100 nm⁺Type GaAs layer 22, thickness 10
To become a channel layer of about 100 nm, for example, 20 nm.
Undoped i-type GaAs layer 23 and impurity concentration
1 × 10 ¹⁸~ 1 × 10¹⁹cm^-3, For example, 5 × 10¹⁸c
m^-3And a thickness of 10 to 1000 nm, for example, 100 n
m for n⁺Type GaAs layers 24 are sequentially deposited.

Next, mesa etching is performed using a hydrofluoric acid-based etchant, thereby isolating the element and forming a source electrode contact region.

Next, as shown in FIG. 2 (b), the Au.Ge layer is
0 nm and an Au layer are deposited at 100 to 1000 nm, for example, 500 nm, and the distance d is 20 to 1000 n.
m, for example, 300 nm, and the width w of the drain electrode 25 is patterned so as to be 10 to 500 nm, for example, 50 nm, thereby forming a striped drain electrode 25 and a dummy electrode 26 made of an Au.Ge/Au layer. .

Next, using the drain electrode 25 and the dummy electrode 26 as a mask, etching is performed using an etching solution having a smaller etching rate on the (111) plane than the (100) plane, for example, bromomethanol, to obtain (0).
1-1) A V-shaped groove 27 having a stripe shape having a (111) side surface in a cross section is formed in the drain electrode 25 and the dummy electrode 26 in a self-aligned manner. In the present specification, a plane orientation usually represented by “1 bar” or the like is represented by “−1” for convenience of preparing the specification.

In this case, when the V-groove 27 is formed,
That is, the etching is automatically stopped when the top of the V groove 27 is formed, and the i-type GaAs layer 2 sandwiched between the V grooves 27 is formed.
3 becomes the channel layer 28.

Next, as shown in FIG. 2C, a non-doped i-type AlGaAs layer 29 (Al composition ratio 0.5) having a thickness of 5 to 100 nm, for example, 20 nm, serving as a gate barrier layer, is formed into n ⁺ by MOVPE.
Selective growth on the exposed surfaces of the n-type GaAs layer 22, the i-type GaAs layer 23, and the n ⁺ -type GaAs layer 24.

In this case, the electron affinity of AlGaAs is G
Since it is smaller than the electron affinity of aAs, when a positive bias is applied to the gate electrode, the i-type AlGaAs layer 29
The two-dimensional electron gas 30 is generated on the i-type GaAs layer 23 side of the interface between the semiconductor device and the i-type GaAs layer 23.

Next, as shown in FIG. 3D, after the resist mask 31 is provided, an Al film is deposited by a vacuum evaporation method, so that the top is made i
The gate electrode 32 is buried in the V-groove 27 so as to be above the interface between the n-type GaAs layer 23 and the n ⁺ -type GaAs layer 24.

Next, by removing the resist mask 31, as shown in FIG.
After removing the Al film deposited on the unnecessary portion by the lift-off method, the i-type A in the region where the source electrode 33 is formed is formed.
The lGaAs layer 29 is selectively removed using a hydrofluoric acid-based etchant, and a source electrode 33 made of Au.Ge/Au is formed at the removed portion.

As described above, in the first embodiment of the present invention, the channel length is determined by the thickness of the channel layer 28 as in the case of the conventional vertical field effect transistor, and thus exceeds the lithography limit. Shorter channels are possible.

Further, since the width of the channel layer 28 is automatically determined by the width of the drain electrode 25, the channel width can be reduced by applying a negative voltage to the gate electrode 32 by reducing the width of the drain electrode 25. Since the entire layer 28 can be depleted, a current that does not depend on the gate voltage, that is, parallel conduction can be eliminated, and power consumption can be reduced.

Next, two modifications of the first embodiment of the present invention will be described with reference to FIG. Referring to FIG. 4A, in the case of the first modification, the i-type A
When the lGaAs layer 29 is provided, the top of the groove is n ⁺ -type Ga.
The distance d between the drain electrode 25 and the dummy electrode 26 is set so as to coincide with the interface between the As layer 22 and the i-type GaAs layer 23.

In this case, the interface and the top do not need to exactly coincide with each other.
When the i-type AlGaAs layer 29 is provided on the surface of the groove 27, the top of the groove is formed by the n ⁺ -type GaAs layer 22 and the i-type GaAs layer 23.
It is desired that the depth be slightly deeper than the interface with.

With this configuration, the parasitic capacitance between the gate electrode 32 and the n ⁺ -type GaAs layer 22 on the source side can be reduced, and the operation delay caused by the parasitic capacitance can be reduced. Can be.

Referring to FIG. 4B, in the case of the second modification, the i-type AlGaAs layer 29 is formed.
Is grown, and the conditions of the MOVPE method are controlled so that the non-doped i-type GaAs layer 34 grows only on the top of the V-groove 27, so that the n ⁺ -type GaAs layers 22 and i
The i-type GaAs layer 34 is buried to the vicinity of the interface of the type GaAs layer 23, and then a gate electrode is provided.

In such selective growth on only the top of the V-groove 27, for example, the growth rate on the (111) plane is (10).
The growth temperature can be controlled by controlling the growth temperature such that the average diffusion distance of the grown atoms becomes longer than the length of the (111) plane of the V-groove 27 so as to be lower than the growth rate for the 0) plane.

In the case of the second modification, i-type GaAs
By controlling the growth rate of the selective growth of the s layer 34, the position of the top can be precisely controlled, so that the gate electrode 32 and the n ⁺ -type GaAs layer 22 on the source side can be precisely controlled.
And the cross-sectional area of the gate electrode 32 can be increased, so that the gate resistance can be reduced.

Next, a second embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 5A, first, as in the first embodiment, the MOVPE (metal organic chemical vapor deposition) method is used on a semi-insulating GaAs substrate 21 having a (100) plane as a main surface. 1 × 1 impurity concentration
0 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁸ cm
^-3 , the thickness is 10 to 1000 nm, for example, 100 nm
N ⁺ -type GaAs layer 22, a non-doped i-type G layer serving as a channel layer having a thickness of 10 to 100 nm, for example, 20 nm
aAs layer 23 and an impurity concentration of 1 × 10 ¹⁸ to 1 × 1
0 ¹⁹ cm ^-3 , for example, 5 × 10 ¹⁸ cm ^-3 and a thickness of 10
N ⁺ -type GaAs of about 1000 nm, for example, 100 nm
By sequentially depositing the layer 24 and then performing mesa etching using a hydrofluoric acid-based etchant, isolation of the element and formation of a source electrode contact region are performed.

Referring to FIG. 5B, after the resist is applied, the distance d is set to 20 to 10.
00 nm, for example, 300 nm, and the width w is 10 to 500.
pattern 35 having a stripe-shaped opening.
Is formed, and using this resist pattern 35 as a mask,
By etching with an etching solution having a smaller etching rate on the (111) plane than the (100) plane, for example, bromomethanol, a V-shaped groove having a (111) plane on the (01-1) cross section is obtained. 27
Is formed on the end of the resist pattern 35 in a self-aligned manner.

Also in this case, the etching is automatically stopped when the V-groove 27 is formed, and the i-type GaAs layer 23 sandwiched between the V-grooves 27 becomes the channel layer 28.

Referring to FIG. 5C, the resist pattern 35 is removed.
By PE method, a thickness of 5 to 100 to be a gate barrier layer
nm, for example, 20 nm non-doped i-type AlGa
An As layer (Al composition ratio 0.5) 29 is grown on the entire surface.

Also in this case, since the electron affinity of AlGaAs is smaller than the electron affinity of GaAs, i-type AlGaAs
i-type GaAs at the interface between the s-layer 29 and the i-type GaAs layer 23
Two-dimensional electron gas 30 is generated on the layer 23 side.

Next, as shown in FIG. 6D, a gate electrode 32 made of Al is formed by CVD using a source gas made of TMAl (trimethylaluminum) to form an i-type GaAs layer 23 and an n ⁺ -type G
It is selectively grown and buried inside the V-groove 27 so as to be above the interface with the aAs layer 24.

Next, by heat-treating the gate electrode 32 made of Al in an oxidizing atmosphere, an insulating film 36, that is, aluminum oxide is formed on the exposed surface of the gate electrode 32, as shown in FIG.

Next, as shown in FIG. 6F, the i-type A in the region where the source electrode 33 is formed is formed.
i-type AlG surrounded by an lGaAs layer 29 and an insulating film 36
After the aAs layer 29 and the self-oxidized film formed on the surface thereof are selectively removed using a hydrofluoric acid-based etchant, the drain electrode 25 made of an Au.Ge/Au film extending on the insulating film 36 and the source are formed. The electrode 33 is formed by a lift-off method.

As described above, also in the second embodiment of the present invention, the channel length is determined by the thickness of the channel layer 28, similarly to the conventional vertical field effect transistor, and thus exceeds the lithography limit. Shorter channels are possible.

The width of the channel layer 28 is determined by the width w of the resist pattern, and the width w of the resist pattern can be reduced irrespective of the series resistance of the drain electrode 25, that is, regardless of the parasitic resistance. 28
Can be arbitrarily narrowed, the drain electrode 25 can be increased to an arbitrary size, and the contact area with the drain region, that is, the n ⁺ -type GaAs layer 34 can be increased. Therefore, the parasitic resistance of the drain can be sufficiently reduced.

Next, two modifications of the second embodiment of the present invention will be described with reference to FIG. 7A. This first modification corresponds to the modification of FIG. 4A, and in this case, the i-type AlG
When the aAs layer 29 is provided, the top of the groove is made of n ⁺ -type GaAs.
In order to match the interface between the layer 22 and the i-type GaAs layer 23,
An interval d between the resist patterns 35 is set.

Also in this case, the interface and the top do not need to exactly coincide with each other, but in order to prevent the occurrence of the offset region,
When the i-type AlGaAs layer 29 is provided on the surface of the V-shaped groove 27, the top of the groove is formed by the n ⁺ -type GaAs layer 22 and the i-type GaAs layer 2
It is desired to be slightly deeper than the interface with No.3.

With such a configuration, the parasitic capacitance between the gate electrode 32 and the n ⁺ -type GaAs layer 22 on the source side can be reduced, and the operation delay caused by the parasitic capacitance can be reduced. Can be.

FIG. 7 (b) This second modification corresponds to the modification of FIG. 4 (b). After the i-type AlGaAs layer 29 has been grown, M
By controlling the conditions of the OVPE method so that the non-doped i-type GaAs layer 34 grows only at the top of the V-groove 27, the i-type GaAs is brought to the vicinity of the interface between the n ⁺ -type GaAs layer 22 and the i-type GaAs layer 23. It is embedded with a layer 34, and then a gate electrode 32 is provided.

In the case of the second modification, the parasitic capacitance between the gate electrode 32 and the n ⁺ -type GaAs layer 22 on the source side can be reduced, and the sectional area of the gate electrode 32 is increased. Therefore, the gate resistance can be reduced.

In the second embodiment and its modification, the insulating film provided on the surface of the gate electrode 32 is formed by thermal oxidation. However, the present invention is not limited to the thermal oxide film. May be deposited.

Next, referring to FIG. 8 and FIG.
A third embodiment will be described. Referring to FIG. 8A, first, a semi-insulating GaAs substrate having a (100) plane as a main surface.
41, using MOVPE (metal organic chemical vapor deposition)
And the impurity concentration is 1 × 10¹⁸~ 1 × 10¹⁹cm ^-3,example
5 × 10¹⁸cm^-3With a thickness of 10 to 1000 nm,
For example, n of 100 nm⁺Type GaAs layer 42, impurity concentration
Degree 1 × 10¹⁸~ 1 × 10¹⁹cm^-3, For example, 5 × 10
¹⁸cm^-3And has a thickness of 1 to 50 nm, for example, 10 nm.
N-type AlGaAs layer (Al
Composition ratio 0.5) 43, thickness 10 to 100 nm, for example,
Non-doped i-type GaAs serving as a 20 nm channel layer
s layer 44 and an impurity concentration of 1 × 10¹⁸~ 1 × 10¹⁹
cm^-3, For example, 5 × 10 ¹⁸cm^-3And the thickness is 10-1
000 nm, for example 100 nm n⁺Type GaAs layer 4
5 are sequentially deposited.

Next, by performing mesa etching using a hydrofluoric acid-based etching solution, isolation of the element and formation of a source electrode contact region are performed.

Next, as shown in FIG. 8 (b), the Au.Ge layer is
0 nm and an Au layer are deposited at 100 to 1000 nm, for example, 500 nm, and the distance d is 20 to 1000 n.
m, for example, 300 nm, and the width w of the drain electrode 46 is patterned so as to be 10 to 500 nm, for example, 50 nm, thereby forming a striped drain electrode 46 and a dummy electrode 47 made of an Au.Ge/Au layer. .

Next, using the drain electrode 46 and the dummy electrode 47 as a mask, etching is performed using an etching solution having a higher etching rate on the (100) plane than on the (111) plane, for example, bromomethanol, thereby forming (0).
11) In the cross section, a side surface is formed in a stripe shape having a (111) plane, and an inverted mesa-shaped groove 48 is formed in a self-aligned manner with the drain electrode 46 and the dummy electrode 47.

In this case, when the inverted mesa-shaped groove 48 reaches the n-type AlGaAs layer 43 serving as an etching stop layer, the etching is automatically stopped, and the i-type GaAs layer 44 sandwiched between the inverted mesa-shaped groove 48 is formed. Becomes the channel layer 49.

Next, as shown in FIG. 8 (c), for example, n
The n-type AlGaAs layer 43 is removed, but also in this case, the etching automatically stops when the n ⁺ -type GaAs layer 42 is exposed.

Next, after removing the dummy electrode 47, an undesired region is covered with a SiO ₂ mask 50, and then the MOVP is removed.
The thickness of the gate barrier layer is 5 to 100 n by the method E.
m, for example, 20 nm non-doped i-type AlGaAs
An n ⁺ -type GaAs layer 42, an n-type AlGaAs layer 43 exposing an s layer (Al composition ratio 0.5)
Selective growth is performed on the surfaces of the i-type GaAs layer 44 and the n ⁺ -type GaAs layer 45.

Also in this case, since the electron affinity of AlGaAs is smaller than the electron affinity of GaAs, i-type AlGaAs
i-type GaAs at the interface between the s-layer 51 and the i-type GaAs layer 44
A two-dimensional electron gas 52 is generated on the layer 44 side.

Next, after a resist mask 53 is provided, the Al film is
By depositing by the D method, the gate electrode 54 is buried in the reverse mesa-shaped groove 48 so that the top is above the interface between the i-type GaAs layer 44 and the n ⁺ -type GaAs layer 45.

Next, as shown in FIG. 9F, the resist film 53 and the SiO ₂ mask 50 are removed to remove the Al film deposited on the unnecessary portion by a lift-off method, and thereafter, is made of Au.Ge/Au by a lift-off method. The source electrode 55 is formed.

As described above, also in the third embodiment of the present invention, the channel length is determined by the thickness of the channel layer 49, similarly to the conventional vertical field effect transistor, and therefore exceeds the lithography limit. Shorter channels are possible.

The width of the channel layer 49 is automatically determined by the width of the drain electrode 46. However, unlike the first embodiment, the width of the drain electrode 46 is sufficiently small even if the width of the drain electrode 46 is increased. Can be formed, the cut-off characteristic of the drain current can be improved in a simple manufacturing process, with the drain-side parasitic resistance sufficiently reduced, and the parallel conduction can be reduced. Since it can be eliminated, power consumption can be reduced.

In the state shown in FIG. 9F, the overlapping area between the gate electrode 53 and the n ⁺ -type GaAs layer 42 on the source side increases, and the parasitic capacitance caused by the gate electrode 53 increases. Prior to the formation of the electrode 53, oxygen ions or protons, ie, hydrogen ions, are ion-implanted into the bottom of the reverse mesa-shaped groove 48 to insulate the portion of the n ⁺ -type GaAs layer 42 facing the gate electrode 53. It is desirable.

Although the embodiments of the present invention have been described above, the present invention is not limited to the GaAs / AlGaAs system, but includes the InGaAs / GaAs system.
Any combination of semiconductors used in a normal horizontal HEMT may be used.

In the above description, an n-type element, that is, an element using a two-dimensional electron gas, is described for the purpose of high-speed operation. However, a p-type element, that is, an element formed on the valence band side is used. A device using a two-dimensional hole gas may be used. In particular, this is necessary when a complementary device is to be constructed. In this case, the gate barrier layer has a forbidden band width E _gB and an electron affinity χ _B. The sum, ie, E _gB + χ _B is the sum of the forbidden bandwidth and the electron affinity of the semiconductor constituting the channel layer, ie, E _gC + χ _C
It must be chosen to be larger.

In the above description, the electrode formed on the convex portion is the drain electrode. However, the drain electrode may be used as the source electrode. In that case, the n ⁺ on the semi-insulating substrate side may be used. A drain electrode may be formed on the mold layer.

In the above description, one element structure has been described. However, in the present invention, such an element structure may be used as a discrete device, or as a compound semiconductor integrated circuit device in which these are integrated. It may be used.

[0087]

According to the present invention, the width of the channel layer of the vertical field effect transistor is determined in a self-aligned manner by the width of the stripe pattern such as the drain electrode. The width can be reduced irrespective of the alignment accuracy, and parallel power can be eliminated to reduce power consumption.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a modified example of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 5;

FIG. 7 is an explanatory diagram of a modified example of the second embodiment of the present invention.

FIG. 8 is an explanatory diagram of a manufacturing process partway through a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of a manufacturing process of the third embodiment of the present invention after FIG. 8;

FIG. 10 is a sectional view of a main part of a conventional vertical field effect transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semi-insulating substrate 2 first conductivity type semiconductor layer 3 undoped semiconductor layer 4 first conductivity type semiconductor layer 5 ohmic electrode 6 dummy electrode 7 groove 8 channel layer 9 gate barrier layer 10 gate electrode 11 two-dimensional carrier gas 12 ohmic Electrode 21 semi-insulating GaAs substrate 22 n ⁺ -type GaAs layer 23 i-type GaAs layer 24 n ⁺ -type GaAs layer 25 drain electrode 26 dummy electrode 27 V-groove 28 channel layer 29 i-type AlGaAs layer 30 two-dimensional electron gas 31 resist mask 32 Gate electrode 33 source electrode 34 i-type GaAs layer 35 resist pattern 36 insulating film 41 semi-insulating GaAs substrate 42 n ⁺ -type GaAs layer 43 n-type AlGaAs layer 44 i-type GaAs layer 45 n ⁺ -type GaAs layer 46 drain electrode 47 dummy electrode 48 Inverted mesa groove 49 Channel layer Reference Signs List 50 SiO ₂ mask 51 i-type AlGaAs layer 52 two-dimensional electron gas 53 resist mask 54 gate electrode 55 source electrode 61 semi-insulating GaAs substrate 62 n ⁺ -type GaAs layer 63 i-type GaAs layer 64 n ⁺ -type GaAs layer 65 i-type AlGaAs Layer 66 Gate electrode 67 Drain electrode 68 Source electrode 69 Two-dimensional electron gas 70 Parallel conduction

Claims (12)

[Claims] 1. A laminated structure comprising at least a first one-conductivity-type semiconductor layer, a non-doped semiconductor layer, and a second one-conductivity-type semiconductor layer, provided on the second one-conductivity-type semiconductor layer. Self-aligned with the ohmic and dummy electrodes, and
A gate provided with two stripe-shaped grooves whose side walls are formed of the same crystal plane having the same crystal orientation, and provided at least on the surface of the groove to generate a two-dimensional carrier gas at an end of the non-doped semiconductor layer. A compound semiconductor device comprising a gate electrode provided via a barrier layer. 2. A stacked structure comprising at least a first one conductivity type semiconductor layer, a non-doped semiconductor layer, and a second one conductivity type semiconductor layer, wherein a side wall is formed of a crystal plane having the same crystal orientation. Two stripe-shaped grooves are provided, and a gate electrode is provided via at least a gate barrier layer provided on a surface of the groove to generate a two-dimensional carrier gas at an end of the non-doped semiconductor layer. Extending on an insulating film provided on the surface of the gate electrode;
A compound semiconductor device provided with an ohmic electrode in contact with the one conductivity type semiconductor layer. 3. The semiconductor device according to claim 2, wherein the groove has a V-shaped cross section, and the tip of the groove after the gate barrier layer is provided is located between the first one conductivity type semiconductor layer and the non-doped semiconductor. The compound semiconductor device according to claim 1, wherein the compound semiconductor device coincides with an interface with the layer. 4. A non-doped semiconductor buried at a height near an interface between the first one conductivity type semiconductor layer and the non-doped semiconductor layer, wherein the groove has a V-shaped cross section. The compound semiconductor device according to claim 1, wherein a layer is provided, and the gate electrode is provided on the non-doped semiconductor buried layer. 5. The semiconductor device according to claim 5, wherein the cross-sectional shape of the groove is an inverted mesa shape, and an etching stop layer of one conductivity type is provided at an interface between the first one conductivity type semiconductor layer and the non-doped semiconductor layer. The compound semiconductor device according to claim 1, wherein: 6. A semi-insulating semiconductor substrate comprising at least a first one conductivity type semiconductor layer, a non-doped semiconductor layer, and
A step of providing a laminated structure made of a second one-conductivity-type semiconductor layer; and a step of forming a stripe-shaped ohmic electrode on the second one-conductivity-type semiconductor layer and a stripe-shaped dummy electrode facing the ohmic electrode. By etching the laminated structure using the ohmic electrode and the dummy electrode as a mask, a groove is formed which is self-aligned with the ohmic electrode and the dummy electrode and whose side wall is formed of a crystal plane having the same crystal orientation. Providing a gate barrier layer for generating a two-dimensional carrier gas at an end of the non-doped semiconductor layer on at least the surface of the groove,
And the non-doped semiconductor layer and the second
A step of burying the gate electrode to a height exceeding an interface with the one conductivity type semiconductor layer. 7. The semiconductor device according to claim 7, wherein the groove has a V-shaped cross section, and the tip of the groove after the gate barrier layer is provided is located between the first one conductivity type semiconductor layer and the non-doped semiconductor. 7. The method according to claim 6, wherein a distance between the ohmic electrode and the dummy electrode is determined so as to coincide with an interface with the layer. 8. On a semi-insulating semiconductor substrate, at least a first one conductivity type semiconductor layer, a non-doped semiconductor layer, and
Providing a stacked structure composed of a second one-conductivity-type semiconductor layer, forming a pattern in which stripe-like lines and stripe-like spaces are alternately arranged on the second one-conductivity-type semiconductor layer; Forming a groove which is self-aligned with the stripe-shaped line by etching the laminated structure as a mask, and whose side wall is formed of a crystal plane having the same crystallographic orientation; Providing a gate barrier layer for generating a two-dimensional carrier gas at an end of the doped semiconductor layer;
And the non-doped semiconductor layer and the second
Embedding the gate electrode to a height exceeding the interface with the one conductivity type semiconductor layer, providing an insulating film on the surface of the gate electrode, and then exposing the surface of the stacked structure surrounded by the groove. Removing the gate barrier layer; and
A method for manufacturing a compound semiconductor device, comprising a step of providing an ohmic electrode so as to cover at least the removed portion. 9. The semiconductor device according to claim 9, wherein the groove has a V-shaped cross section, and the tip of the groove after the gate barrier layer is provided is located between the first one conductivity type semiconductor layer and the non-doped semiconductor. 9. The method of manufacturing a compound semiconductor device according to claim 8, wherein an interval between the stripe-shaped line and the stripe-shaped space is determined so as to coincide with an interface with the layer. 10. The semiconductor device according to claim 1, wherein the groove has a V-shaped cross section, and after the gate barrier layer is provided, before the step of embedding the gate electrode, the first one-conductivity-type semiconductor layer and the non-conductive semiconductor layer are formed.・ Non-up to the vicinity of the interface with the doped semiconductor layer
9. The method according to claim 6, wherein the doped semiconductor buried layer is selectively grown. 11. A cross-sectional shape of the groove is an inverted mesa shape,
7. The method of manufacturing a compound semiconductor device according to claim 6, further comprising a one-conductivity-type etching stop layer at an interface between the first one-conductivity-type semiconductor layer and the non-doped semiconductor layer. 12. The method according to claim 11, wherein, after growing the gate barrier layer, ions are implanted into the bottom of the trench to partially insulate the first one conductivity type semiconductor layer. The manufacturing method of the compound semiconductor device of the above.