JP4413472B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device and a method for manufacturing the same. For example, a resonant tunneling diode (RTD) having a negative differential resistance and a high electron mobility transistor (which are expected to be applied to a device for high-speed optical communication) The present invention relates to a compound semiconductor device characterized by the structure of a self-aligned electrode in a compound semiconductor device in which HEMTs are integrated, and a method for manufacturing the same.
[0002]
[Prior art]
With the recent increase in speed and capacity of optical communications, in the field of communications infrastructure, there is an urgent need to develop various optical devices such as wavelength multiplexing lasers and optical modulators. In order to drive at high speed, a high-speed switching semiconductor device or the like is required.
[0003]
As such a high-speed switching semiconductor device for optical communication, a compound semiconductor device in which an RTD having a negative differential resistance and a HEMT are integrated is known. Here, referring to FIG. The HEMT will be described.
[0004]
See FIG.
FIG. 12 is a schematic cross-sectional view of a conventional RTD integrated HEMT. In order to integrate an RTD, an n-type cap layer 53 is formed on a HEMT constituent layer 52 provided on a semi-insulating InP substrate 51. An RTD component layer is formed through the patterning, and the RTD component layer 54 is patterned to form the RTD element portion 54.
[0005]
In this case, it is important to minimize the step between the RTD and the HEMT from the problem of the gate electrode formation process using electron beam lithography.
That is, the T-type gate electrode 61 provided in the gate recess region 60 is formed using a lift-off pattern obtained by patterning a three-layer resist by electron beam lithography. Therefore, it is necessary to reduce the step between the RTD and the HEMT.
[0006]
Therefore, the HEMT n-type cap layer 53 is used as it is for the lateral extraction of the lower electrode 56, and the film thickness of the RTD element portion 54 is as small as possible, for example, about 140 nm.
Reference numerals 55, 58, and 59 in the figure denote an upper electrode, a source electrode, and a drain electrode, respectively.
[0007]
[Problems to be solved by the invention]
However, the parasitic resistance 57 due to the n-type cap layer 53 of the HEMT has a problem that the high-speed operation of the RTD is hindered.
In order to solve such a problem, the lower electrode 56 may be as close as possible to the RTD element portion 54. However, there is a lift-off problem in the process using the conventional photolithography technique, and this distance may be reduced. Can not.
[0008]
On the other hand, by using the self-alignment process, it is possible to reduce the parasitic resistance due to the n-type cap layer 53 of the HEMT by bringing the RTD element portion 54 and the lower electrode 56 close to the limit.
[0009]
However, since the lower electrode 56 needs to have a certain thickness, for example, about 300 nm, in order to reduce damage in the subsequent wiring process, when the thickness of the RTD element portion 54 is smaller than the lower electrode 56 as described above, self-alignment is required. If the process is applied as it is, it causes a serious problem that the upper electrode 55 and the lower electrode 57 are short-circuited.
[0010]
Therefore, an object of the present invention is to reduce the parasitic resistance by forming an electrode by a self-alignment process while keeping the step small, and to enable high-speed operation.
[0011]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Here, means for solving the problems in the present invention will be described with reference to FIG.
Reference numeral 1 in the figure denotes a substrate such as a semi-insulating InP substrate.
See Figure 1
In order to achieve the above object, the present invention provides a first compound semiconductor layer 2 on the first compound semiconductor layer 2. A diode is formed, or a diode is formed by using a joint surface with the first compound semiconductor layer 2. A second compound semiconductor layer 3 is formed and formed on the first compound semiconductor layer 2 One electrode of the diode While providing the 1st electrode 5, on the said 2nd compound semiconductor layer 3 The other electrode of the diode In the compound semiconductor device provided with the second electrode 4, the first electrode 5 is at least close to the second compound semiconductor layer 3. And thinner than the second compound semiconductor layer 3 A distance from the first region 6 to the second compound semiconductor layer 3 is longer than the first region 6 and in contact with the first region 6, and is thicker than the first region 6. It is configured.
[0012]
Thus, even if the electrode is formed by a self-alignment process, the first region 6 is formed by a two-stage structure including the first region 5 which is the lower electrode and the second region which is sufficiently thick. Then, since the film thickness is small, the first electrode 5 and the second electrode 4 are not short-circuited.
In addition, since the film thickness of the second region 7 of the first electrode 5 can be sufficiently increased, the wiring process is not damaged.
[0013]
In addition, the thickness of the first region 6 of the first electrode 5 is thinner than that of the second compound semiconductor multilayer structure, and the boundary between the first region 6 and the second compound semiconductor layer 3 By providing the electrode 4 in a self-aligned manner, the parasitic resistance on the surface of the first compound semiconductor layer 2 is reduced, and high-speed operation is possible.
[0014]
This self-alignment process may be formed by forming an eaves-like overhanging portion on the second electrode 4 or may be performed by making the cross section of the second compound semiconductor layer 3 reversely tapered. May be.
[0015]
In addition, by providing a sidewall made of an insulating material at the boundary between the first region 6 and the second compound semiconductor layer 3, the distance between the sidewalls may be increased.
[0016]
Further, a diode structure, for example, a resonant tunnel diode, a pn junction diode, or a pin diode, is provided on either the second compound semiconductor layer 3 or the junction surface between the first compound semiconductor layer 2 and the second compound semiconductor layer 3. Alternatively, it is desirable to form either a Schottky barrier diode.
In this case, when a Schottky barrier diode is formed, a portion of the second electrode 4 provided in the second compound semiconductor layer 3 that is in contact with the second compound semiconductor layer 3 is made of a Schottky barrier forming metal. good.
[0017]
Further, by forming at least one of a bipolar transistor or a field effect transistor in the first compound semiconductor layer 2, a high-speed switching semiconductor device for optical communication can be configured.
[0018]
Further, when manufacturing the above-described compound semiconductor device, a conductive material constituting the first electrode 5 is formed after forming an eaves-like protruding portion on the second electrode 4 provided on the second compound semiconductor layer 3. Is deposited from above, and the boundary between the second compound semiconductor layer 3 and the first electrode 5 may be formed in a self-aligned manner with respect to the second electrode 4.
[0019]
Alternatively, after providing a sidewall made of an insulating material on the sidewall of the second compound semiconductor layer 3, the conductive material constituting the first electrode 5 is deposited from above, and then obliquely with respect to the deposition direction. The first electrode 5 in the vicinity of the second compound semiconductor layer 3 can be formed by selectively removing the conductive material on the sidewall by performing ion milling.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Here, the manufacturing process of the compound semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 5. Here, as the compound semiconductor device, a resonant tunnel diode (RTD) and a high-voltage semiconductor device are used. An example in which an electron mobility transistor (HEMT) is integrated is shown.
[0021]
See Fig. 2 (a)
First, an MOCVD method (metal organic chemical vapor deposition method) is used on a semi-insulating InP substrate 11 to form an i-type InAlAs buffer layer 13 having a thickness of, for example, 200 nm, and an i-type InGaAs having a thickness of, for example, 25 nm. Channel layer 14, i-type InAlAs spacer layer 15 with a thickness of 3 nm, for example, thickness of 7 nm with an impurity concentration of 5 × 10 5 ¹⁸ cm ^-3 N-type InAlAs electron supply layer 16, i-type InAlAs barrier layer 17 having a thickness of, for example, 7 nm, i-type InP etching stop layer 18 having a thickness of, for example, 6 nm, and thickness of, for example, 50 nm Impurity concentration is 1 × 10 ¹⁹ cm ^-3 The n-type InGaAs cap layer 19 is sequentially grown.
This is the HEMT constituent layer. Here, for convenience of the following description, the i-type InGaAs buffer layer 12 to the i-type InP etching stop layer 18 are referred to as the HEMT constituent layer 12 and separated from the n-type InGaAs cap layer 19. Separately illustrated.
[0022]
Subsequently, the i-type InP etching stop layer 21 having a thickness of, for example, 6 nm, the thickness of, for example, 50 nm, and the impurity concentration of 1 × 10 5 ¹⁹ cm ^-3 N-type InGaAs spacer layer 22, for example, an i-type InGaAs spacer layer 23 having a thickness of, for example, 30 nm, an i-type InAlAs barrier layer 24 having a thickness of, for example, 3 nm, and an i-type InGaAs well having a thickness of, for example, 4 nm Layer 25, i-type InAlAs barrier layer 26 with a thickness of, for example, 3 nm, i-type InGaAs spacer layer 27 with a thickness of, for example, 30 nm, and thickness of, for example, 50 nm and an impurity concentration of 1 × 10 ¹⁹ cm ^-3 The n-type InGaAs spacer layer 28 is sequentially deposited to form the RTD constituent layer 20.
[0023]
Refer to FIG.
Next, a TiW layer having a thickness of, for example, 100 nm is deposited on the entire surface by sputtering, and then dry etching is performed using a resist pattern (not shown) as a mask to form the TiW upper electrode 29.
[0024]
Refer to FIG.
Next, after removing the resist pattern, the RTD component layer 20 is etched by RTD using the TiW upper electrode 29 as a mask and wet etching using an etchant made of a mixed solution of phosphoric acid, hydrogen peroxide, and water. The element part 30 is formed.
In this case, when a (001) -oriented substrate is used as the substrate, the side wall of the RTD component layer 20 is formed by the (111) A plane, and when viewed from one side, takes a forward mesa shape and is orthogonal thereto. When viewed from the direction, it has a reverse mesa shape.
[0025]
In this case, the RTD constituent layer 20 is excessively etched to form an eave-like overhanging portion in the TiW upper electrode 29, but the etching stops at the lowermost i-type InP etching stop layer 21 of the RTD constituent layer 20.
Next, the i-type InP etching stop layer 21 is removed by etching using a mixed solution of hydrochloric acid and phosphoric acid, thereby exposing the n-type InGaAs cap layer 19.
[0026]
Refer to FIG.
Next, using the new resist pattern (not shown) as a mask, the n-type InGaAs cap layer 18 is first removed by wet etching using an etchant composed of a mixture of phosphoric acid, hydrogen peroxide, and water. The i-type InP etching stop layer 18 on the surface of the HEMT component layer 12 is etched using a mixed solution of hydrochloric acid and phosphoric acid, and then again using an etchant made of a mixed solution of phosphoric acid, hydrogen peroxide, and water. By performing wet etching, the i-type InAlAs barrier layer 17 to the i-type InAlAs buffer layer 13 are removed, and the isolation groove 31 is formed.
In this case, the i-type InAlAs buffer layer 13 is etched to a depth of 70 nm, for example.
[0027]
See Fig. 4 (e)
Next, after removing the resist pattern, a new lift-off resist pattern (not shown) is provided, and the thickness is, for example, a 5 nm Ti film, the thickness is, for example, 10 nm, and the thickness is, for example, After sequentially depositing a 35 nm Au film, the Ti / Mo / Au layer 32 is formed by removing the lift-off resist pattern.
In this case, the Ti / Mo / Au layer 32 formed on the n-type InGaAs cap layer 18 is the first stage of the annular lower electrode and is formed in a self-aligned manner with respect to the TiW upper electrode 29.
[0028]
Refer to FIG.
Next, a new lift-off resist pattern (not shown) is provided, and a 10 nm Ti film having a thickness of, for example, a Pt film having a thickness of, for example, 30 nm, and an Au film having a thickness of, for example, 250 nm are sequentially formed. After the vapor deposition, the Ti / Pt / Au layer 33 is formed by removing the lift-off resist pattern.
[0029]
In this case, on the n-type InGaAs cap layer 18, the lower electrode 34 is formed by the Ti / Mo / Au layer 32 and the Ti / Pt / Au layer 33. For example, the Ti / Pt / Au layer 33 is formed at a distance of 1.5 μm from the end face of the RTD element portion 30.
Further, the Ti / Pt / Au layer 33 formed simultaneously in the other mesa region serves as a source / drain electrode of the HEMT.
[0030]
Refer to FIG.
Next, the n-type InGaAs cap layer 19 is etched using an etchant made of a mixture of citric acid, hydrogen peroxide, and water using a new resist pattern (not shown) as a mask in the other mesa region, thereby forming a gate recess region 35. Form.
At this time, the etching stops at the i-type InP etching stop layer 18.
[0031]
Next, after removing the resist pattern, a resist pattern for lift-off having a new three-layer structure is provided, and the thickness is, for example, a 10 nm Ti film, the thickness is, for example, 30 nm, and the thickness is, for example, After sequentially depositing a 600 nm Au film, the lift-off resist pattern is removed to form the T-type gate electrode 36, thereby obtaining the basic structure of the compound semiconductor device of the first embodiment of the present invention. It is done.
[0032]
Thus, in the first embodiment of the present invention, the lower electrode 34 is formed by the first stage made of the thin Ti / Mo / Au layer 32 and the second stage made of the thick Ti / Pt / Au layer 33. Since it is formed, the lower electrode 34 can be formed in a self-aligned process with respect to the TiW upper electrode 29, thereby reducing the parasitic resistance.
[0033]
Further, since the second stage made of the thick Ti / Pt / Au layer 33 is provided on the lower electrode 34, the lower electrode 34 is not damaged in the wiring process, and a highly reliable compound semiconductor device is configured. be able to.
[0034]
Next, with reference to FIGS. 6 to 8, a manufacturing process of the compound semiconductor device according to the second embodiment of the present invention will be described.
See Fig. 6 (a)
First, in exactly the same manner as in the first embodiment, the HEMT constituent layer 12, the n-type InGaAs cap layer 19, and the RTD constituent layer 20 are sequentially deposited on the semi-insulating InP substrate 11 using the MOCVD method. .
[0035]
Next, using the resist pattern (not shown) as a mask, wet etching is performed using an etchant made of a mixture of phosphoric acid, hydrogen peroxide, and water, thereby forming the separation groove 31.
The i-type InP etching stop layers 18 and 21 existing in the middle are removed with a mixed solution of hydrochloric acid and phosphoric acid, and the i-type InGaAs buffer layer 13 is etched to a depth of 70 nm, for example. .
[0036]
See Fig. 6 (b)
Next, after removing the resist pattern, the new resist pattern (not shown) is used as a mask, and etching is performed using an etchant made of a mixture of phosphoric acid, hydrogen peroxide, and water, so that the RTD has an inversely tapered cross section. The element part 37 is formed, and the RTD constituent layer 20 in the other mesa region is removed.
In this case, since the etching stops at the i-type InP etching stop layer 21, the i-type InP etching stop layer 21 is further removed with a mixed solution of hydrochloric acid and phosphoric acid.
In this case, when a (001) -oriented substrate is used as the substrate, the side wall of the RTD component layer 20 is formed by the (111) A plane, and when viewed from one side, takes a forward mesa shape and is orthogonal thereto. When viewed from the direction, it has a reverse mesa shape.
[0037]
See Fig. 7 (c)
Next, after removing the resist pattern, a new lift-off resist pattern (not shown) is provided, and the thickness is, for example, a 5 nm Ti film, the thickness is, for example, 10 nm, and the thickness is, for example, After sequentially depositing a 35 nm Au film, the Ti / Mo / Au layer 32 is formed by removing the lift-off resist pattern.
In this case, the Ti / Mo / Au layer 32 formed on the n-type InGaAs cap layer 18 is the first stage of the annular lower electrode, and the Ti / Mo / Au layer formed on the RTD element portion 37. 32 is the first stage of the upper electrode and is formed in a self-aligned manner.
Here, since the Ti / Mo / Au layer 32 is deposited only in the reverse mesa shape, that is, the reverse taper direction in the RTD element portion 37 by devising the lift-off resist pattern, the Ti / Mo / Au layer 32 is deposited. The Mo / Au layer 32 is separated by disconnection.
[0038]
Refer to FIG.
Next, a new lift-off resist pattern (not shown) is provided, and a 10 nm Ti film having a thickness of, for example, a Pt film having a thickness of, for example, 30 nm, and an Au film having a thickness of, for example, 250 nm are sequentially formed. After the vapor deposition, the Ti / Pt / Au layer 33 is formed by removing the lift-off resist pattern.
[0039]
In this case, on the n-type InGaAs cap layer 18, the lower electrode 34 is formed by the Ti / Mo / Au layer 32 and the Ti / Pt / Au layer 33. For example, the Ti / Pt / Au layer 33 is formed at a distance of 1.5 μm from the end face of the RTD element portion 37.
[0040]
On the other hand, the upper electrode 38 is formed by the Ti / Mo / Au layer 32 and the Ti / Pt / Au layer 33 formed on the RTD element portion 37.
Further, the Ti / Pt / Au layer 33 formed simultaneously in the other mesa region serves as a source / drain electrode of the HEMT.
[0041]
Refer to FIG.
Thereafter, in exactly the same manner as in the first embodiment, an etchant made of a mixed solution of citric acid, hydrogen peroxide, and water is used as a mask for a new resist pattern (not shown) in the other mesa region. The gate recess region 35 is formed by etching the n-type InGaAs cap layer 19.
At this time, the etching stops at the i-type InP etching stop layer 18.
[0042]
Next, after removing the resist pattern, a resist pattern for lift-off having a new three-layer structure is provided, and the thickness is, for example, a 10 nm Ti film, the thickness is, for example, 30 nm, and the thickness is, for example, After sequentially depositing a 600 nm Au film, the resist pattern for lift-off is removed to form the T-type gate electrode 36, thereby obtaining the basic structure of the compound semiconductor device of the second embodiment of the present invention. It is done.
[0043]
As described above, in the second embodiment of the present invention, the reverse tapered RTD element portion 37 is used for the self-alignment process, and this reverse tapered shape is formed by a crystal plane of a specific orientation. Therefore, the gap between the RTD element portion 37 and the first stage Ti / Mo / Au layer 32 of the lower electrode 34 is defined by the thickness of the RTD constituent layer 20 and does not depend on the excessive etching time. 37 and the lower electrode 34 can be brought close to each other with good reproducibility.
[0044]
Next, with reference to FIGS. 9 to 11, a manufacturing process of the compound semiconductor device according to the third embodiment of the invention will be described.
See Fig. 9 (a)
First, in exactly the same manner as in the first embodiment, the HEMT constituent layer 12, the n-type InGaAs cap layer 19, and the RTD constituent layer 20 are sequentially deposited on the semi-insulating InP substrate 11 using the MOCVD method. .
[0045]
Next, the RTD element unit 39 is formed by etching using an etchant made of a mixed solution of phosphoric acid, hydrogen peroxide, and water using a resist pattern (not shown) as a mask.
At this time, since the etching stops at the i-type InP etching stop layer 21, the i-type InP etching stop layer 21 is further removed with a mixed solution of hydrochloric acid and phosphoric acid.
[0046]
Refer to FIG. 9B.
Next, after removing the resist pattern, an SiON film having a thickness of, for example, 100 to 200 nm is formed on the entire surface by plasma CVD, and then the sidewall 40 is formed by performing anisotropic dry etching. .
[0047]
Refer to FIG.
Next, using the resist pattern (not shown) as a mask, wet etching is performed using an etchant made of a mixture of phosphoric acid, hydrogen peroxide, and water, thereby forming the separation groove 31.
The i-type InP etching stop layers 18 and 21 existing in the middle are removed with a mixed solution of hydrochloric acid and phosphoric acid, and the i-type InGaAs buffer layer 13 is etched to a depth of 70 nm, for example. .
[0048]
Refer to FIG.
Next, after removing the resist pattern, a new lift-off resist pattern (not shown) is provided, and the thickness is, for example, a 5 nm Ti film, the thickness is, for example, 10 nm, and the thickness is, for example, Then, a 35 nm Au film is sequentially deposited to form a Ti / Mo / Au layer 32 covering the RTD element portion 39 and its vicinity.
[0049]
Refer to FIG.
Next, by performing Ar ion milling from an obliquely upward direction, the Ti / Mo / Au layer 32 deposited above the sidewall 40 is removed, and the Ti / Mo / Au layer 32 is separated vertically.
In this case, the Ti / Mo / Au layer 32 formed on the n-type InGaAs cap layer 18 is the first stage of the annular lower electrode, and the Ti / Mo / Au layer formed on the RTD element portion 39. 32 is the first stage of the upper electrode.
[0050]
Refer to FIG.
Thereafter, as in the first embodiment, a new lift-off resist pattern (not shown) is provided, and the thickness is, for example, a 10 nm Ti film, the thickness is, for example, a 30 nm Pt film, and Then, after sequentially depositing an Au film having a thickness of, for example, 250 nm, the Ti / Pt / Au layer 33 is formed by removing the lift-off resist pattern.
[0051]
In this case, on the n-type InGaAs cap layer 18, the lower electrode 34 is formed by the Ti / Mo / Au layer 32 and the Ti / Pt / Au layer 33. For example, the Ti / Pt / Au layer 33 is formed at a distance of 1.5 μm from the end face of the RTD element portion 39.
[0052]
On the other hand, the upper electrode 38 is formed by the Ti / Mo / Au layer 32 and the Ti / Pt / Au layer 33 formed on the RTD element portion 39.
Further, the Ti / Pt / Au layer 33 formed simultaneously in the other mesa region serves as a source / drain electrode of the HEMT.
[0053]
Next, the n-type InGaAs cap layer 19 is etched using an etchant made of a mixture of citric acid, hydrogen peroxide, and water using a new resist pattern (not shown) as a mask in the other mesa region, thereby forming a gate recess region 35. Form.
At this time, the etching stops at the i-type InP etching stop layer 18.
[0054]
Next, after removing the resist pattern, a resist pattern for lift-off having a new three-layer structure is provided, and the thickness is, for example, a 10 nm Ti film, the thickness is, for example, 30 nm, and the thickness is, for example, After sequentially depositing a 600 nm Au film, the lift-off resist pattern is removed to form the T-type gate electrode 36, thereby obtaining the basic structure of the compound semiconductor device of the third embodiment of the present invention. It is done.
[0055]
As described above, in the third embodiment of the present invention, the gap between the RTD element portion 39 and the first stage Ti / Mo / Au layer 32 of the lower electrode 34 is defined by the thickness of the sidewall 40. Since it does not depend on the excessive etching time, the RTD element part 39 and the lower electrode 34 can be brought close to each other with good reproducibility.
[0056]
Further, since the upper and lower electrodes are separated using the side wall 40 and using Ar ion milling, the raw material is deposited when the Ti / Mo / Au layer 32 is deposited as in the first or second embodiment. There is no possibility that the gas will wrap around and a short circuit will occur through the side wall of the RTD element.
[0057]
As mentioned above, although each embodiment of the present invention has been described, the present invention is not limited to the configuration described in each embodiment, and various modifications can be made.
For example, in each of the above embodiments, the steps are configured in a specific order, but some of the steps may be interchanged.
[0058]
For example, in the first embodiment, the separation groove forming step, the lower electrode first step forming step, and the lower electrode second cross-section forming step may be interchanged, Further, the separation groove may be formed before the formation of the RTD element portion as in the second embodiment.
[0059]
Also in the second embodiment, the step of forming the separation groove, the first step of forming the lower electrode, and the step of forming the second cross section of the lower electrode may be interchanged. Further, the separation groove may be formed after the formation of the RTD element portion as in the first embodiment.
[0060]
In the third embodiment, the separation groove is formed immediately after deposition of the Ti / Mo / Au layer, immediately after separation of the Ti / Mo / Au layer, or immediately after deposition of the Ti / Pt / Au layer. Is also good.
[0061]
In the first embodiment, since the TiW upper electrode is formed on the RTD element portion in advance, in principle, the Ti / Mo / Au layer and the TiW are formed on the TiW upper electrode. The / Pt / Au layer is not necessarily formed.
However, since a self-alignment process is provided, a Ti / Mo / Au layer is formed.
[0062]
In each of the above embodiments, the lower electrode has a two-stage structure of a Ti / Mo / Au layer and a Ti / Pt / Au layer. However, the lower electrode is not necessarily limited to a two-stage structure. A multi-layer structure having more than one stage may be used.
[0063]
In each of the above embodiments, the source / drain electrodes of the HEMT are constituted by the second stage Ti / Pt / Au layer, but are formed by the first stage Ti / Mo / Au layer. Alternatively, a two-stage structure of a Ti / Mo / Au layer and a Ti / Pt / Au layer may be used.
[0064]
Further, in each of the above embodiments, the lower electrode is formed in a ring shape, but it is not always necessary to have a ring shape, and it may be provided in the vicinity of at least one end of the RTD element portion.
[0065]
Further, in each of the above embodiments, the diode is configured by the RTD, but is not necessarily limited to the RTD, and may be a pn junction diode, a pin diode, or a Schottky barrier diode. In the case of a key barrier diode, the upper electrode may be formed of a Schottky barrier electrode.
[0066]
In the case of forming a pn junction diode, a p-type InGaAs layer may be formed on the n-type InGaAs cap layer 19. In the case of a pn junction diode, a pin diode, or a Schottky barrier diode, an RTD is used. A constituent layer is not necessary.
[0067]
In each of the above embodiments, the HEMT is used as the main element. However, the HEMT is not necessarily required, and a normal MESFET that does not perform the HEMT operation may be used.
[0068]
Further, the main element is not limited to the field effect type compound semiconductor element, but may be a bipolar transistor such as a heterojunction bipolar transistor (HBT), or may be used in combination with a field effect type compound semiconductor element. is there.
[0069]
In each of the above embodiments, the element isolation is performed by the isolation groove. However, the isolation is not necessarily limited to the isolation groove, and the element isolation may be performed by a region in which oxygen ions are implanted and insulated. Is.
[0070]
In each of the above-described embodiments, the InP substrate is used and the InGaAs / InAlAs system is described. However, the present invention is not limited to these materials, and other materials such as a GaAs substrate, a GaAs / AlGaAs system, and the like are used. This material system may be used.
[0071]
Here, the detailed features of the present invention will be described again with reference to FIG.
See Figure 1
(Supplementary Note 1) On the first compound semiconductor layer 2 A diode is formed, or a diode is formed by using a joint surface with the first compound semiconductor layer 2. A second compound semiconductor layer 3 is formed and formed on the first compound semiconductor layer 2 One electrode of the diode While providing the 1st electrode 5, on the said 2nd compound semiconductor layer 3 The other electrode of the diode In the compound semiconductor device provided with the second electrode 4, the first electrode 5 is at least close to the second compound semiconductor layer 3. And thinner than the second compound semiconductor layer 3 A second region 7 having a distance from the first region 6 and the second compound semiconductor layer 3 farther than the first region 6 and in contact with the first region 6 and thicker than the first region 6. A compound semiconductor device comprising:
(Appendix 2) The first area 6 And the boundary between the second compound semiconductor layer 3 and Said Supplementary note 1 characterized by being provided in a self-aligned manner with respect to the second electrode 4 In The compound semiconductor device described.
(Appendix 3) Said The thickness of the first region 6 of the first electrode 5 is Said The second compound semiconductor layer 3 is thinner than the second compound semiconductor layer 3 and the cross section of the second compound semiconductor layer 3 is inversely tapered, and the boundary between the first region 6 and the second compound semiconductor layer 3 is Supplementary note 1 characterized by being provided in a self-aligned manner with respect to the top surface of the second compound semiconductor layer 3 In The compound semiconductor device described.
(Appendix 4) Said The thickness of the first region 6 of the first electrode 5 is Said Note that a sidewall made of an insulating material is provided at the boundary between the first region 6 and the second compound semiconductor layer 3, which is thinner than the second compound semiconductor layer 3. 1 In The compound semiconductor device described.
(Appendix 5 ) Said Note that the diode structure is a resonant tunnel diode, a pn junction diode, a pin diode, or a Schottky barrier diode. 1 to any one of appendix 4 The compound semiconductor device described.
(Appendix 6 ) Said The first compound semiconductor layer 2 is formed with at least one of a bipolar transistor and a field effect transistor. 5 The compound semiconductor device according to any one of the above.
(Appendix 7 Note 1 or Appendix 2. The compound semiconductor device according to 2 A manufacturing method for manufacturing , Said After forming an eaves-like overhanging portion on the second electrode 4 provided on the second compound semiconductor layer 3, Said By depositing the conductive material constituting the first electrode 5 from above, the boundary between the second compound semiconductor layer 3 and the first electrode 5 is self-aligned with the second electrode 4. Forming a compound semiconductor device.
(Appendix 8 ) Compound semiconductor device according to appendix 4 A manufacturing method for manufacturing , Said After providing a sidewall made of an insulating material on the sidewall of the second compound semiconductor layer 3, Said The conductive material on the side wall is selectively removed by depositing the conductive material constituting the first electrode 5 from above and then performing ion milling from an oblique direction with respect to the deposition direction. A method of manufacturing a compound semiconductor device.
[0072]
【The invention's effect】
According to the present invention, since the lower electrode has at least a two-stage structure, it is possible to provide the lower electrode with respect to the semiconductor active layer having a thickness smaller than that of the electrode metal in a self-aligned manner, thereby reducing the parasitic resistance. Therefore, it greatly contributes to the realization of an excellent compound semiconductor device capable of high-speed operation.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process until halfway through the compound semiconductor device according to the first embodiment of this invention;
FIG. 3 is an explanatory diagram of the manufacturing process of the compound semiconductor device according to the first embodiment of this invention up to the middle of FIG. 2 and subsequent steps.
FIG. 4 is an explanatory diagram of a manufacturing process up to the middle of FIG. 3 and subsequent drawings of the compound semiconductor device according to the first embodiment of the invention;
5 is an explanatory diagram of a manufacturing process of the compound semiconductor device according to the first embodiment of the present invention after FIG. 4;
FIG. 6 is an explanatory diagram of a manufacturing process until halfway through the compound semiconductor device according to the second embodiment of the invention.
FIG. 7 is an explanatory diagram of the manufacturing process of the compound semiconductor device according to the second embodiment of the present invention until the middle of FIG. 6 and subsequent steps.
FIG. 8 is an explanatory diagram of the manufacturing process after FIG. 7 for the compound semiconductor device according to the second embodiment of the present invention;
FIG. 9 is an explanatory diagram of a manufacturing process until halfway through the compound semiconductor device according to the third embodiment of the invention;
FIG. 10 is an explanatory diagram of the manufacturing process of the compound semiconductor device according to the third embodiment of the present invention until halfway through FIG. 9;
FIG. 11 is an explanatory diagram of the manufacturing process after FIG. 10 for the compound semiconductor device according to the third embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of a conventional RTD integrated HEMT.
[Explanation of symbols]
1 Substrate
2 First compound semiconductor layer
3 Second compound semiconductor layer
4 Second electrode
5 First electrode
6 First area
7 Second area
11 Semi-insulating InP substrate
12 HEMT component layer
13 i-type InAlAs buffer layer
14 i-type InGaAs channel layer
15 i-type InAlAs spacer layer
16 n-type InAlAs electron supply layer
17 i-type InAlAs barrier layer
18 i-type InP etching stop layer
19 n-type InGaAs cap layer
20 RTD component layers
21 n-type InP etching stop layer
22 n-type InGaAs spacer layer
23 i-type InGaAs spacer layer
24 i-type InAlAs barrier layer
25 i-type InGaAs well layer
26 i-type InAlAs barrier layer
27 i-type InGaAs spacer layer
28 n-type InGaAs spacer layer
29 TiW upper electrode
30 RTD element
31 Separation groove
32 Ti / Mo / Au layer
33 Ti / Pt / Au layer
34 Lower electrode
35 Gate recess area
36 T-type gate electrode
37 RTD element
38 Upper electrode
39 RTD element
40 sidewall
51 Semi-insulating InP substrate
52 HEMT component layer
53 n-type cap layer
54 RTD element
55 Upper electrode
56 Lower electrode
57 Parasitic resistance
58 Source electrode
59 Drain electrode
60 Gate recess area
61 T-type gate electrode

Claims (4)

A first compound semiconductor layer is formed on the first compound semiconductor layer, and a second compound semiconductor layer constituting the diode is formed using a junction surface with the first compound semiconductor layer. provided with a first electrode serving as one electrode of the diode above, in the compound semiconductor device having a second electrode serving as the other electrode of the diode to the second compound semiconductor layer, the first The first electrode is adjacent to at least the second compound semiconductor layer and is thinner than the second compound semiconductor layer, and the distance from the second compound semiconductor layer is farther than the first region. A compound semiconductor device comprising: a second region that is in contact with the first region and is thicker than the first region. Wherein the first region boundary between the second compound semiconductor layer, a compound semiconductor device according to claim 1, characterized in that provided in a self-aligned manner with respect to the second electrode. Wherein the first compound semiconductor layer, a compound semiconductor device according to claim 1 or claim 2, wherein at least one of bipolar transistors or field effect transistor are formed. 4. A manufacturing method for manufacturing the compound semiconductor device according to claim 1 , wherein an eaves-like projecting portion is formed on a second electrode provided on the second compound semiconductor layer. 5. later, by depositing a conductive material constituting the first electrode from above, the boundary between the said second compound semiconductor layer and the first electrode, a self-aligned manner with respect to the second electrode A method of manufacturing a compound semiconductor device, comprising:

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