JPH09102600A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field effect transistor adapted to make it possible to perform the high frequency, high gain and high efficiency operation and to a high output operation and a method for manufacturing the transistor. SOLUTION: A channel layer 100 is formed of an i-type InGaAs channel upper layer 6 provided at a gate electrode side and an n-type GaAs channel lower layer 55 provided at a GaAs substrate 1 side. Thus, since the layer 55 serves as a main current route at the gate electrode 11 at the time of applying a high drain voltage, a collision ionization at the layer is suppressed, and the breakdown voltage of the channel can be increased. Further, since both the layer 6 and the layer 55 serve as main current routes between the source and the gate, low source resistance is obtained to make it possible to perform the high frequency, high gain and high efficiency operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a high output field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing an example of a conventional high output field effect transistor. This field effect transistor is called a HEMT (High Electron Mobility Transistor). This field effect transistor has an i-GaAs buffer layer 2 and an i-AlGa grown on a semi-insulating GaAs substrate 1.
As buffer layer 3, n-type AlGaAs lower electron supply layer 4, i-InGaAs channel layer 65, n-type AlGaA
s upper electron supply layer 7 and n-type GaAs contact layer 8
And a source electrode 9 and a drain electrode 10 which are in ohmic contact with this layer provided on the contact layer, and a contact layer 8 between the source electrode and the drain electrode are formed in a recess groove 13 formed by etching. Gate electrode 11 in Schottky contact with the upper electron supply layer 7
It is composed of

In this field effect transistor, a lower electron supply layer made of n-type AlGaAs having a relatively high concentration of n-type impurities and a small electron affinity, which is arranged above and below the low-impurity concentration i-InGaAs channel layer 65. 4, and electrons supplied from the upper electron supply layer 7 are Al
It is accumulated in a channel layer 65 made of InGaAs having a higher electron affinity than GaAs, and this layer operates as a channel. The electron concentration in the channel layer 65 can be changed by changing the bias voltage applied to the gate electrode 11. Accordingly, the current flowing between the source and the drain can be controlled by the gate voltage, and the transistor operation can be performed.

Since the electron mobility and electron velocity in the InGaAs layer are higher than the electron mobility and electron velocity in the GaAs layer, the above field effect transistor using the InGaAs layer as the channel layer is It has a low source resistance and is suitable for high frequency, high gain and high efficiency operation.

[0005]

As described above, in the channel layer 65 of the field effect transistor, especially HEMT, In
By using the GaAs layer, a field effect transistor suitable for high frequency, high gain and high efficiency operation can be obtained. However, in the InGaAs layer, GaA
Compared with the s layer, impact ionization is more likely to occur in a low electric field, and therefore, in the field effect transistor using the InGaAs layer for the channel layer, there is a problem that the breakdown voltage of the channel is lowered. In order to operate the field effect transistor at high output, it is necessary to apply a high drain voltage, but this decrease in breakdown voltage is an obstacle to operating the field effect transistor having the above InGaAs channel layer at high output. It was.

The present invention has been made in view of the above problems, and provides a field effect transistor capable of high frequency, high gain and high efficiency operation and suitable for high output operation, and a method for manufacturing the same. It is intended.

[0007]

A field effect transistor according to the present invention (claim 1) is a semiconductor layer including a channel layer provided on a semiconductor substrate and a gate electrode provided on the surface of the semiconductor layer. And a field-effect transistor including a source electrode and a drain electrode provided on the surface of the semiconductor layer so as to sandwich the gate electrode,
The channel layer, a channel lower layer made of GaAs,
A channel upper layer made of InGaAs provided above the channel lower layer is included.

Further, a field effect transistor according to the present invention (claim 2) is the field effect transistor according to claim 1, wherein the semiconductor layer is provided above the channel layer and in contact with the channel upper layer. The upper layer made of a semiconductor having an electron affinity smaller than that of InGaAs forming the upper layer of the channel is included.

A field effect transistor according to the present invention (claim 3) is the same as the field effect transistor (claim 2), wherein the upper layer is an upper layer lower layer containing a high concentration of n-type impurities. The n-type impurity concentration contained in the upper-layer lower layer is lower than the n-type impurity concentration of the upper-layer lower layer.

Further, the field effect transistor according to the present invention (claim 4) is the same as the field effect transistor (claim 2 or 3), wherein the upper layer is in contact with the channel upper layer and is an undoped spacer. It is intended to include layers.

A field effect transistor according to the present invention (Claim 5) is the field effect transistor according to any one of Claims 2 to 4, wherein the upper layer is G
It is made of aAs, AlGaAs, or InGaP.

Further, a field effect transistor according to the present invention (claim 6) is characterized in that, in the field effect transistor (any one of claims 2 to 5), the semiconductor layer is
A lower layer made of a semiconductor having an electron affinity lower than that of GaAs is provided below the channel layer.

Further, a field effect transistor according to the present invention (claim 7) is the field effect transistor (claim 6), wherein the lower layer includes an undoped spacer layer in contact with the channel lower layer. It is a thing.

A field effect transistor according to the present invention (claim 8) is the field effect transistor according to claim 6 or 7, wherein the lower layer is AlGaA.
s, or InGaP.

A field effect transistor according to the present invention (claim 9) is provided between the semiconductor substrate and the semiconductor layer in the field effect transistor (claim 1). It is provided with a buffer layer made of a high resistance semiconductor.

A field effect transistor according to the present invention (claim 10) is the field effect transistor according to any one of claims 1 to 9, wherein the semiconductor substrate is a semi-insulating GaAs substrate. is there.

A field effect transistor according to the present invention (claim 11) is the field effect transistor according to any one of claims 1 to 10, wherein the gate electrode is formed on the surface of the upper layer. The semiconductor layer includes a contact layer made of a semiconductor containing a high concentration of n-type impurities, which is provided in regions on both sides of the gate electrode on the surface of the upper layer, and the source electrode, and The drain electrode is formed on the surface of the contact layer.

A field effect transistor according to the present invention (claim 12) is a semiconductor layer including a channel layer provided on a semiconductor substrate, a gate electrode provided on the surface of the semiconductor layer, and the gate. In a field effect transistor provided with a source electrode and a drain electrode provided on the surface of the semiconductor layer so as to sandwich the electrode, the channel layer has an In composition directed from the semiconductor substrate side to the semiconductor layer surface side. The composition transition channel layer made of InGaAs is increased.

A field effect transistor according to the present invention (claim 13) is the field effect transistor (claim 12), wherein the semiconductor layer is in contact with the composition transition channel layer above the channel layer. Which constitutes the uppermost layer of the composition transition channel layer
It includes an upper layer made of a semiconductor having an electron affinity smaller than that of GaAs.

A field effect transistor according to the present invention (claim 14) is the same as the field effect transistor (claim 13), wherein the upper layer is an upper layer lower layer containing a high concentration of n-type impurities. The upper layer lower layer, which is provided on the upper layer lower layer, contains an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer.

A field effect transistor according to the present invention (claim 15) is the field effect transistor according to claim 13 or 14, wherein the upper layer is provided in contact with the composition transition channel layer. The spacer layer is included.

Further, a field effect transistor according to the present invention (claim 16) is the above field effect transistor (any one of claims 13 to 15), wherein the upper layer is made of GaAs, AlGaAs or InGaP. It is what

A field effect transistor according to the present invention (claim 17) is the field effect transistor according to any one of claims 13 to 16, wherein the semiconductor layer is provided below the channel layer. , A lower layer made of a semiconductor having a smaller electron affinity than GaAs.

The field effect transistor according to the present invention (claim 18) is the field effect transistor according to claim 17 wherein the lower layer is provided in contact with the composition transition channel layer. It is intended to include layers.

A field effect transistor according to the present invention (claim 19) is the above field effect transistor (claim 17 or 18), wherein the lower layer is AlG.
It is made of aAs or InGaP.

A field effect transistor according to the present invention (claim 20) is provided between the semiconductor substrate and the semiconductor layer in the field effect transistor (any one of claims 12 to 19). It is provided with a buffer layer made of a high resistance semiconductor.

A field effect transistor according to the present invention (claim 21) is the field effect transistor according to any one of claims 12 to 20, wherein the semiconductor substrate is a semi-insulating GaAs substrate. is there.

A field effect transistor according to the present invention (claim 22) is the field effect transistor according to any one of claims 12 to 21, wherein the gate electrode is formed on the surface of the upper layer. The semiconductor layer includes a contact layer made of a semiconductor containing a high concentration of n-type impurities, which is provided in regions on both sides of the gate electrode on the surface of the upper layer, the source electrode, and The drain electrode is formed on the surface of the contact layer.

Further, in the method of manufacturing a field effect transistor according to the present invention (claim 23), a step of forming a buffer layer made of a high-resistance semiconductor on a semi-insulating GaAs substrate, and a GaAs layer on the buffer layer are provided. A semiconductor layer formed by sequentially laminating a channel lower layer formed of InGaAs, an upper channel layer formed of InGaAs, an upper layer formed of a semiconductor having an electron affinity lower than that of InGaAs forming the upper channel, and a contact layer formed of a semiconductor containing a high concentration of n-type impurities. A step of forming a layer, a step of forming, on the contact layer, a source electrode and a drain electrode whose contact with the contact layer becomes ohmic contact, and a gate described later between the source electrode and the drain electrode. A process for forming a recess groove by etching away the contact layer in the region where the electrode is to be formed. When, is intended to include a step of forming a gate electrode in contact with the upper layer in the recess groove is Schottky contact.

A method of manufacturing a field effect transistor according to the present invention (claim 24) is the same as the method of manufacturing a field effect transistor (claim 23), wherein the upper layer contains a high concentration n-type impurity. And an upper layer upper layer having an n-type impurity concentration which is formed on the upper layer lower layer and is lower than the n-type impurity concentration of the upper layer lower layer. It is supposed to be formed in contact with the upper layer surface.

A method for manufacturing a field effect transistor according to the present invention (claim 25) is the same as the method for manufacturing a field effect transistor (claim 23 or 24) described above.
The upper layer includes an undoped spacer layer formed in contact with the surface of the channel upper layer.

Further, in the method for manufacturing a field effect transistor according to the present invention (claim 26), a step of forming a buffer layer made of a high-resistance semiconductor on a semi-insulating GaAs substrate, and GaAs on the buffer layer are provided. A lower layer made of a semiconductor having a smaller electron affinity, a lower layer of a channel made of GaAs, an upper layer of a channel made of InGaAs, an upper layer made of a semiconductor having a smaller electron affinity than InGaAs constituting this upper layer, and a high concentration of n-type impurities. A step of forming a semiconductor layer formed by sequentially stacking contact layers made of a semiconductor, and a source electrode whose contact with the contact layer is an ohmic contact on the contact layer,
And a step of forming a drain electrode, the source electrode,
And a step of forming a recess groove by etching away the contact layer in a region where a gate electrode described later is to be formed between the drain electrodes, and a contact with the upper layer in the recess groove is a Schottky contact. Forming a gate electrode.

A method of manufacturing a field effect transistor according to the present invention (claim 27) is the same as the method of manufacturing a field effect transistor (claim 26), wherein the upper layer contains a high concentration n-type impurity. And an upper layer upper layer formed on the upper layer lower layer and having an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer. The layer is formed in contact with the surface of the upper layer.

A method for manufacturing a field effect transistor according to the present invention (claim 28) is the same as the method for manufacturing a field effect transistor described above (claim 26 or 27).
The upper layer includes an undoped spacer layer formed in contact with the surface of the channel upper layer.

A method for manufacturing a field effect transistor according to the present invention (claim 29) is the above method for manufacturing a field effect transistor (claim 26).
In the above, the lower layer includes an undoped spacer layer as the uppermost layer.

Further, in the method for manufacturing a field effect transistor according to the present invention (claim 30), a step of forming a buffer layer made of a semiconductor having a high resistance on a semi-insulating GaAs substrate, and GaAs on the buffer layer. A lower layer made of a semiconductor having a smaller electron affinity, and its In composition is the GaA
A composition transition channel layer made of InGaAs increasing upward from the s substrate side, an upper layer made of a semiconductor having a smaller electron affinity than InGaAs constituting the surface portion of the composition transition channel layer, and a high concentration of n-type impurities. A step of forming a semiconductor layer formed by sequentially stacking contact layers made of a semiconductor, and a source electrode whose contact with the contact layer is an ohmic contact on the contact layer,
And a step of forming a drain electrode, the source electrode,
And a step of forming a recess groove by etching away the contact layer in a region where a gate electrode described later is to be formed between the drain electrodes, and a contact with the upper layer in the recess groove is a Schottky contact. Forming a gate electrode.

A method of manufacturing a field-effect transistor according to the present invention (claim 31) is the same as the method of manufacturing a field-effect transistor (claim 30), wherein the upper layer contains a high-concentration n-type impurity. And an upper layer upper layer formed on the upper layer lower layer and having an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer. It is formed on the upper layer.

A method of manufacturing a field-effect transistor according to the present invention (claim 32) is the same as the method of manufacturing a field-effect transistor (claim 30 or 31).
The upper layer includes an undoped spacer layer formed in contact with the surface of the composition transition channel layer.

A method of manufacturing a field effect transistor according to the present invention (claim 33) is the above method of manufacturing a field effect transistor (claim 30).
In the above, the lower layer includes an undoped spacer layer as the uppermost layer.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Configuration 1. As shown in FIG. 1, a field effect transistor (Claim 1) according to the first embodiment of the present invention includes a semiconductor layer 101 provided on a semiconductor substrate 1 including a channel layer 100, and a surface of the semiconductor layer 101. In the field effect transistor including the gate electrode 11 provided on the surface of the semiconductor layer 101 and the source electrode 9 and the drain electrode 10 provided on the surface of the semiconductor layer 101 so as to sandwich the gate electrode 11, the channel layer 100 is The channel lower layer 55 made of GaAs and the channel upper layer 6 made of InGaAs provided above the channel lower layer 55 are included. As a result, in the channel layer 100 below the gate electrode 11 when a high drain voltage is applied, the InGaAs channel upper layer 6 located on the gate electrode side becomes a charge depletion layer, and the GaAs channel lower layer 55 becomes the channel layer 1.
Since it becomes the main path of the current flowing through 00, this current flows through InGa like the conventional field effect transistor described above.
It does not flow through the As layer. Therefore, the channel layer 10
The impact ionization at 0 can be suppressed, the breakdown voltage of the channel can be increased, and this field effect transistor can be made suitable for high output operation.
InG between the source electrode 9 and the gate electrode 11
Since both the aAs channel upper layer 6 and the GaAs channel lower layer 55 serve as current paths, a low source resistance equivalent to that of the field effect transistor using the above-mentioned conventional InGaAs layer as the channel layer can be obtained. Therefore, high frequency, high gain, Highly efficient operation becomes possible.

Configuration 2. As shown in FIG. 1, the field effect transistor according to the first embodiment of the present invention (claim 2) is the same as the field effect transistor having the above-described configuration 1, except that the semiconductor layer 101 is provided above the channel layer 100.
An upper layer 7 made of a semiconductor having an electron affinity lower than that of InGaAs forming the channel upper layer 6 is provided in contact with the channel upper layer 6.
As a result, electrons serving as carriers can be supplied to the channel upper layer 6 by using the upper layer 7 as an electron supply layer. By making the channel upper layer 6 an undoped layer, the electrons serving as carriers are scattered by the donor. The upper layer 6 of the channel can be traveled without receiving. For this reason,
It is possible to obtain a field effect transistor having a low source resistance and capable of high frequency, high gain, and high efficiency operation.

Configuration 3. As shown in FIG. 1 (b), the field effect transistor according to the first embodiment of the present invention is the same as the field effect transistor of the above-mentioned configuration 2, except that the upper layer 7 is formed with a high-concentration n-type impurity. And an upper layer upper layer 73 which is provided on the upper layer lower layer 72 and has an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer 72. Is. Thereby, from the upper layer lower layer 72,
Electrons can be supplied to the channel layer 100, and n of the upper layer upper layer 73 in contact with the gate electrode 11 is n.
Since the type impurity concentration is low, the leak current at the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Structure 4. As shown in FIG. 1B, the field effect transistor according to the first embodiment of the present invention (claim 4) is the same as the field effect transistor having the configuration 2 or 3, and the upper layer 7 and the channel upper layer 6 are And an undoped spacer layer 71 that is provided in contact with. As a result, electrons traveling in the vicinity of the interface of the channel layer 100 with the upper layer 7 are not generated in the upper layer 7.
It is possible to prevent scattering by an n-type impurity, which is a donor contained in, and further improve high frequency, high gain, and high efficiency operation characteristics.

Structure 5. As shown in FIG. 1, the field effect transistor according to the first embodiment of the present invention (claim 5) is the field effect transistor according to any one of the above constitutions 2 to 4, wherein the upper layer 7 is formed of GaAs, AlGa.
It is made of As or InGaP. As a result, the electron affinity of the upper layer 7 can be made smaller than the electron affinity of InGaAs forming the channel upper layer 6, and the upper layer 7 can be used as an electron supply layer. It is possible to obtain a field effect transistor capable of high gain and high efficiency operation.

Configuration 6. As shown in FIG. 1, the field effect transistor according to the first embodiment of the present invention (claim 9) is the same as the field effect transistor according to any one of the configurations 1 to 5, except that the semiconductor substrate 1 and the semiconductor layer 10 are
1 is provided with a buffer layer 2 made of a high resistance semiconductor. As a result, the semiconductor layer 101 formed on the buffer layer 2 has few crystal defects,
The layer can be made of a good semiconductor crystal, and the electric characteristics of the field effect transistor can be made excellent.

Structure 7. As shown in FIG. 1, the field effect transistor according to the first embodiment of the present invention is the field effect transistor according to any one of the configurations 1 to 6, in which the semiconductor substrate 1 is made of semi-insulating Ga.
This is an As substrate. Thereby, the semiconductor substrate 1
When a plurality of elements are formed on top of each other, electrical isolation between the elements is facilitated, and the operating layer of the field effect transistor and the parasitic capacitance between the electrode and the semiconductor substrate are reduced, resulting in high frequency operation characteristics. An excellent field effect transistor can be obtained.

Structure 8. As shown in FIG. 1, the field effect transistor according to the first embodiment of the present invention (claim 11) is the field effect transistor according to any one of the above configurations 1 to 7, in which the gate electrode 11 is replaced by the upper layer 7 It is assumed that the semiconductor layer 101 is formed on the surface.
Includes a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities provided in regions on both sides of the gate electrode 11 on the surface of the upper layer 7, the source electrode 9 and the drain electrode. 10 is formed on the surface of the contact layer 8. This makes it possible to reduce the contact resistance between the source electrode 9 and the drain electrode 10 and the semiconductor layer 101, and
The gate electrode 11 is not on the contact layer 8 but
Since the impurity concentration is lower than the impurity concentration of the contact layer 8, it is formed on the surface of the upper layer 7, so that the leakage current in the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced and the gate breakdown voltage can be improved. You can

Structure 9. As shown in FIG. 2, a method of manufacturing a field effect transistor according to the first embodiment of the present invention comprises a step of forming a buffer layer 2 made of a high-resistance semiconductor on a semi-insulating GaAs substrate 1, as shown in FIG. , A channel lower layer 55 made of GaAs on the buffer layer 2,
A semiconductor layer is formed by sequentially stacking an upper channel layer 6 made of InGaAs, an upper layer 7 made of a semiconductor having an electron affinity lower than that of InGaAs forming the upper channel layer, and a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities. Between the step of forming and the step of forming the source electrode 9 and the drain electrode 10 on the contact layer 8 whose contact with the contact layer 8 is ohmic contact, and between the source electrode 9 and the drain electrode 10. And a step of forming the recess groove 13 by etching away the contact layer 8 in a region where a gate electrode to be described later is formed, and the contact with the upper layer 7 in the recess groove 13 is a Schottky contact. And the step of forming 11. In the field effect transistor thus manufactured, the i-InGaAs channel upper layer 6 becomes a charge depletion layer in the channel layer 100 under the gate electrode 11 when a high drain voltage is applied.
5 serves as the main path of the current flowing through the channel layer 100, and unlike the conventional field effect transistor described above, the current does not flow through the InGaAs layer, so that collision ionization in the channel layer is suppressed and the breakdown of the channel is suppressed. The voltage can be increased. Therefore, this field effect transistor is suitable for high output operation. InGa between the source electrode 9 and the gate electrode 11
Since both the As channel upper layer 6 and the GaAs channel lower layer 55 serve as current paths, a low source resistance equivalent to that of the field effect transistor using the conventional InGaAs layer as the channel layer can be obtained, which results in high frequency, high gain, and Highly efficient operation becomes possible.

Structure 10. A method of manufacturing a field effect transistor according to the first embodiment of the present invention (claim 24) is
As shown in FIG. 1 (b), in the method of manufacturing a field effect transistor having the above-described configuration 9, the upper layer 7 is composed of an upper layer lower layer 72 containing a high concentration of n-type impurities, and an upper layer lower layer 72. And an upper layer upper layer 73 whose n-type impurity concentration contained therein is lower than the n-type impurity concentration of the upper layer lower layer 72. The gate electrode 11 is formed in contact with the surface of the upper layer upper layer 73. It is supposed to be. As a result, electrons can be supplied from the upper layer lower layer 72 to the channel layer 100, and the n-type impurity concentration of the upper layer upper layer 73 in contact with the gate electrode 11 is low, so that the gate electrode 11 and Upper layer 7
It is possible to reduce the leak current in the Schottky contact with and to improve the gate breakdown voltage.

Structure 11. A method of manufacturing a field effect transistor according to the first embodiment of the present invention (claim 25) is
As shown in FIG. 1 (b), in the method of manufacturing a field effect transistor having the above structure 9 or 10, the upper layer 7
Includes an undoped spacer layer 71 formed in contact with the surface of the channel upper layer 6. As a result, electrons traveling in the vicinity of the interface of the channel layer 100 with the upper layer 7 can be prevented from being scattered by the n-type impurity that is a donor included in the upper layer 7, and high frequency and high gain can be obtained. ， High efficiency operation characteristics can be further improved.

Embodiment 1 A field effect transistor according to an example of the first embodiment of the present invention and a method for manufacturing the same will be described. FIG. 1A shows a sectional view of the field effect transistor according to the first embodiment. This field effect transistor is a so-called HEMT, and is a semi-insulating Ga.
An undoped i-GaAs buffer layer 2 having a thickness of 500 nm, which is a high resistance semiconductor layer grown on an As substrate 1;
A 20 nm thick n-type GaAs channel lower layer 55 (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) containing a relatively high concentration of n-type impurity (Si) grown on the buffer layer 2 and a low impurity concentration ( Undoped) 20 nm thick i-In _0.15 Ga
_{0. 85} As channel layer 6, the thickness of 40nm which contains a relatively high concentration of n-type impurity (Si) n-type Al _0.2 Ga
_0.8 As Upper electron supply layer 7 (Si concentration: 1.5 × 10 ¹⁸ c
m ^-3 ), and a semiconductor layer 101 composed of an n-type GaAs contact layer 8 (Si concentration: 3 × 10 ¹⁸ cm ^-3 ) containing a high concentration of n-type impurity (Si) and having a thickness of 100 nm, and the contact layer 8 A source electrode 9 and a drain electrode 10 made of AuGe / Ni / Au in ohmic contact with this layer formed above, and a recess groove 13 formed by etching the contact layer 8 between the source electrode and the drain electrode. And a gate electrode 11 made of Ti / Al provided inside. However, the contact between the gate electrode 11 and the upper electron supply layer 7 is a Schottky contact. Further, the n-type GaAs channel lower layer 55 has a function as an electron supply layer as well as a channel layer. Further, in the figure, reference numeral 100 is a channel layer composed of the channel upper layer 6 and the channel lower layer 55.

Next, a method of manufacturing the field effect transistor according to the first embodiment will be described with reference to FIG. First, FIG.
As shown in (a), an undoped i-GaAs buffer layer 2 having a thickness of 500 nm and Si having a thickness of 1 × 10 ¹⁸ cm are formed on a semi-insulating GaAs substrate 1 by MOCVD or MBE.
^-3 doped 20 nm thick n-type GaAs channel lower layer 55, 20 nm thick undoped i-In _0.15 Ga
_0.85 As channel upper layer 6, n-type Al _0.2 Ga _0.8 As electron supply layer 7 having a thickness of 40 nm doped with Si of 1.5 × 10 ¹⁸ cm ⁻³ , and 100 n thickness of Si doped with 3 × 10 ¹⁸ cm ⁻³
m n-type GaAs contact layer 8 is sequentially grown. Next, as shown in FIG. 2B, for example, AuGe / Ni / A
The source electrode 9 and the drain electrode 10 made of u are formed by usual photolithography, vacuum deposition, and lift-off. Subsequently, as shown in FIG. 2C, a resist pattern 12 for forming a gate electrode is formed on the entire surface of the contact layer 8 by the ordinary photolithography, and the resist pattern 12 is formed.
The contact layer 8 is etched using the as a mask,
A recess groove 13 is formed in a region where a gate electrode will be formed.
Furthermore, as shown in FIG. 2 (d), for example, Ti / A
After the gate electrode metal composed of 1 is deposited, the resist pattern 12 is removed to form the gate electrode 11 in the recess groove 13. As a result, the field effect transistor shown in FIG. 1 (a) is manufactured.

Further, as shown in FIG. 1 (b), Al _0.2 G
a _0.8 As upper electron supply layer 7 with an undoped i-Al _0.2 Ga _0.8 As spacer layer 71, Si having a thickness of 2 nm.
2.5 × 10 ¹⁸ cm ⁻³ Doped 20 nm thick n-type Al _0.2
Ga _0.8 As high concentration doping layer (upper layer lower layer) 72,
20 nm thick n-type Al doped with 1 × 10 ¹⁷ cm ^-3 Si
_0.2 Ga _0.8 As Low concentration doping layer (upper layer) 7
It may be a stack of three. The low-concentration doping layer (upper layer) 73 is undoped Al _0.2 G.
It may be made of a _0.8 As.

Generally, in order to obtain a high output in a field effect transistor, it is necessary to apply a high drain voltage. When the high drain voltage is applied, the gate electrode is in a state in which a negative bias is applied to the drain electrode, so that in the channel layer below the gate electrode, the charge depletion layer spreads downward from the gate electrode side, Therefore, most of the current flowing between the source and drain flows in the lower region of the channel layer. In the above-mentioned conventional field effect transistor, since the channel layer is composed entirely of InGaAs, when a high drain voltage is applied, a current concentrates on InGaAs in the lower region of the channel layer, causing a breakdown of the channel due to impact ionization. It was easy.

The above-mentioned impact ionization in GaAs is I
Less likely to occur in nGaAs. In the field effect transistor according to the first embodiment, when a high drain voltage is applied, the InGaAs channel upper layer 6 under the gate electrode 11 becomes a charge depletion layer, and the n-type GaAs channel lower layer 55 serves as a main current path. Ionization is suppressed as compared with impact ionization in the InGaAs channel layer in the above-mentioned conventional field effect transistor, and the breakdown voltage of the channel can be increased. Further, the current flowing through the channel layer 100 between the source and the gate is the same as the i-In1aAs channel upper layer 6 and the n-type GaA.
Since it flows in both the s-channel lower layer 55, a low source resistance equivalent to that of the conventional field effect transistor described above can be obtained, and high frequency, high gain, and high efficiency operation can be performed.

In fact, in the field effect transistor of the first embodiment, the gate length is 0.2 μm and the gate width is 480 μm.
Element, the power gain at a frequency of 60 GHz is 6 dB,
The gain equivalent to that of the conventional field effect transistor is obtained, and the breakdown voltage of the channel when the gate voltage is 0V is 6V or more, which is an improvement of 2V or more as compared with the conventional field effect transistor.

In addition, the AlGa shown in FIG.
The As upper electron supply layer 7 is an undoped spacer layer 71,
High concentration doping layer 72 and low concentration doping layer 73
In the field-effect transistor configured as described above, since the undoped spacer 71 is provided between the high-concentration doping layer 72 and the i-InGaAs channel upper layer 6, the upper electron supply layer 7 in the channel upper layer 6 is formed. It is possible to prevent the electrons traveling in the vicinity of the interface of (4) from being scattered by the n-type impurity that is a donor contained in the upper electron supply layer 7, and the field effect transistor shown in FIG. Further lower source resistance can be obtained, and high frequency, high gain and high efficiency operation characteristics can be further improved. Further, since the uppermost layer of the upper electron supply layer 7 is the low concentration doping layer 73, the gate electrode 11 is
Since the upper electron supply layer 7 comes into contact with the low-concentration doping layer 73 and the upper electron supply layer 7 is a uniformly highly-doped layer as shown in FIG. It is possible to reduce the leak current in the Schottky contact with the electron supply layer 7 and increase the gate breakdown voltage.

Although n-type AlGaAs is used for the upper electron supply layer 7 in the first embodiment, n-type InGaP or n-type GaAs may be used instead.

Embodiment 2 Configuration 1. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 1) includes a semiconductor layer 101 provided on a semiconductor substrate 1 including a channel layer 100, and a surface of the semiconductor layer 101. In the field effect transistor including the gate electrode 11 provided on the surface of the semiconductor layer 101 and the source electrode 9 and the drain electrode 10 provided on the surface of the semiconductor layer 101 so as to sandwich the gate electrode 11, the channel layer 100 is A channel lower layer 5 made of GaAs and I provided above the channel lower layer 5
The channel upper layer 6 made of nGaAs is included. As a result, in the channel layer 100 below the gate electrode 11 when a high drain voltage is applied, the InGaAs channel upper layer 6 located on the gate electrode 11 side becomes a charge depletion layer, and the GaAs channel lower layer 5 becomes the channel layer 10.
Since it becomes the main path of the current flowing through 0, the current does not flow through the InGaAs layer unlike the conventional field effect transistor described above. Therefore, impact ionization in the channel layer 100 is suppressed, the breakdown voltage of the channel can be increased, and this field effect transistor can be made suitable for high output operation. Further, between the source electrode 9 and the gate electrode 11, both the InGaAs channel upper layer 6 and the GaAs channel lower layer 5 serve as current paths, so that the field effect transistor using the conventional InGaAs layer as the channel layer is as low as the above. A source resistance is obtained, which enables high frequency, high gain, and high efficiency operation.

Configuration 2. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 2) is the same as the field effect transistor of the above configuration 1, except that the semiconductor layer 101 is provided above the channel layer 100.
An upper layer 7 made of a semiconductor having an electron affinity smaller than that of InGaAs forming the channel upper layer 6 is provided so as to be in contact with the channel upper layer 6.
As a result, electrons serving as carriers can be supplied to the channel upper layer 6 by using the upper layer 7 as an electron supply layer. By making the channel upper layer 6 an undoped layer, electrons serving as carriers are scattered by the donor. The channel layer 100 can be traveled without receiving. Therefore, it is possible to obtain a field effect transistor having a low source resistance and capable of high frequency, high gain, and high efficiency operation.

Configuration 3. As shown in FIG. 3B, the field effect transistor according to the second embodiment of the present invention (claim 3) is the same as the field effect transistor of the above-mentioned configuration 2, except that the upper layer 7 is formed with a high-concentration n-type impurity. And an upper layer upper layer 73 provided on the upper layer lower layer 72, the n type impurity concentration of which is lower than the n type impurity concentration of the upper layer lower layer 72. Is. Thereby, from the upper layer lower layer 72,
Electrons can be supplied to the channel layer 100, and n of the upper layer upper layer 73 in contact with the gate electrode 11 is n.
Since the type impurity concentration is low, the leak current at the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Structure 4. As shown in FIG. 3B, the field effect transistor according to the second embodiment of the present invention (claim 4) is the same as the field effect transistor having the configuration 2 or 3, and the upper layer 7 and the channel upper layer 6 are provided. And an undoped spacer layer 71 that is provided in contact with. As a result, electrons traveling in the vicinity of the interface of the channel layer 100 with the upper layer 7 are not generated in the upper layer 7.
It is possible to prevent scattering by an n-type impurity, which is a donor contained in, and further improve high frequency, high gain, and high efficiency operation characteristics.

Configuration 5. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 5) is the field effect transistor according to any one of the above configurations 2 to 4, wherein the upper layer 7 is formed of GaAs, AlGa.
It is made of As or InGaP. As a result, the electron affinity of the upper layer 7 can be made smaller than the electron affinity of InGaAs forming the channel upper layer 6, and the upper layer 7 can be used as an electron supply layer. It is possible to obtain a field effect transistor capable of high gain and high efficiency operation.

Configuration 6. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 6) is the field effect transistor according to any one of the above configurations 2 to 5, in which the semiconductor layer 101 is replaced by the channel layer 100. And a lower layer 4 made of a semiconductor having an electron affinity lower than that of GaAs, which is provided below the. Thereby, as described above, not only the upper layer 7 can be used as an electron supply layer, but the lower layer 4 can also be used as an electron supply layer and supplied to the upper channel layer 6 and the lower channel layer 5 as carriers. The field density of the generated electrons can be made larger than that of the field effect transistor provided with only the upper layer, and a field effect transistor having a lower source resistance and capable of high frequency, high gain, and high efficiency operation can be obtained. .

Structure 7. As shown in FIG. 3 (b), the field effect transistor according to the second embodiment of the present invention is the same as the field effect transistor of the above-mentioned constitution 6, but the lower layer 4 is in contact with the channel lower layer 5. An undoped spacer layer 42 is included.
This prevents electrons traveling in the vicinity of the interface between the channel layer 100 and the lower layer 4 from being scattered by the n-type impurity that is a donor included in the lower layer 4 (high-concentration doping layer 41). Therefore, high frequency, high gain, and high efficiency operation characteristics can be further improved.

Structure 8. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 8) is the same as the field effect transistor having the structure 6 or 7, and the lower layer 4 is made of AlGaAs or InGa.
It consists of P. As a result, the electron affinity of the lower layer 4 is changed to GaA which constitutes the channel lower layer 5.
Since the electron affinity of s can be made smaller and the lower layer 4 can be used as an electron supply layer, a field effect transistor having a low source resistance and capable of high frequency, high gain, and high efficiency operation can be obtained as described above. You can

Structure 9. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 9) is the same as the field effect transistor according to any one of the configurations 1 to 8, except that the semiconductor substrate 1 and the semiconductor layer 10 are
1 is provided with a buffer layer 2 made of a high resistance semiconductor. As a result, the semiconductor layer 101 formed on the buffer layer 2 has few crystal defects,
The layer can be made of a good semiconductor crystal, and the electric characteristics of the field effect transistor can be made excellent.

Structure 10. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 10) is the field effect transistor according to any one of the above configurations 1 to 9, wherein the semiconductor substrate 1 is made of a semi-insulating G
This is an aAs substrate. This facilitates electrical isolation between elements when a plurality of elements are formed on the semiconductor substrate 1, and also reduces the parasitic capacitance between the operating layer of the field effect transistor and the electrode and the semiconductor substrate. A field effect transistor that is reduced and has excellent high-frequency operating characteristics can be obtained.

Structure 11. As shown in FIG. 3, the field effect transistor according to the second embodiment of the present invention (claim 11) is the field effect transistor according to any one of the above constitutions 1 to 10, in which the gate electrode 11 and the upper layer 7 are provided. It is assumed that the semiconductor layer 10 is formed on the surface.
1 includes a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities provided in regions on both sides of the gate electrode 11 on the surface of the upper layer 7, the source electrode 9, and the drain. The electrode 10 is formed on the surface of the contact layer 8. Thereby, the contact resistance between the source electrode 9 and the drain electrode 10 and the semiconductor layer 101 can be reduced, and the impurity concentration of the gate electrode 11 is not on the contact layer 8 but higher than that of the contact layer 8. Since it is formed on the surface of the small upper layer 7, the leak current in the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Structure 12. A method of manufacturing a field effect transistor according to the second embodiment of the present invention (claim 26) is
A step of forming buffer layers 2 and 3 made of a high-resistance semiconductor on the semi-insulating GaAs substrate 1 shown in FIG. 4, a channel lower layer made of GaAs 5, a channel upper layer made of InGaAs 6, an upper layer 7 made of a semiconductor having an electron affinity lower than that of InGaAs constituting the channel upper layer 7, a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities A step of forming a semiconductor layer 101 formed by sequentially laminating the source electrode 9 on the contact layer 8 shown in FIGS. 2 (b)-(d), in which the contact with the contact layer 8 is ohmic contact, And a step of forming the drain electrode 10, and the contact between the source electrode 9 and the drain electrode 10 in a region where a gate electrode described later is to be formed. The coat layer 8 is removed by etching,
It includes a step of forming the recess groove 13 and a step of forming the gate electrode 11 in the recess groove 13 whose contact with the upper layer 7 becomes a Schottky contact. In the field effect transistor thus manufactured, the channel layer 100 below the gate electrode 11 when a high drain voltage is applied.
In the above, since the i-InGaAs channel upper layer 6 becomes a charge depletion layer, the GaAs channel lower layer 5 becomes the channel layer 1.
00 becomes a main path of the current flowing through the semiconductor layer 00, and unlike the conventional field effect transistor described above, the current does not flow through the InGaAs layer. Therefore, impact ionization in the channel layer 100 is suppressed, and the breakdown voltage of the channel is increased. Can be made. Therefore, this field effect transistor is suitable for high output operation. Further, between the source electrode 9 and the gate electrode 11, both the InGaAs channel upper layer 6 and the GaAs channel lower layer 5 serve as current paths, so that the field effect transistor using the conventional InGaAs layer as the channel layer is as low as the above. A source resistance is obtained, which enables high frequency, high gain, and high efficiency operation.

Structure 13. A method for manufacturing a field effect transistor according to the second embodiment of the present invention (claim 27) is
As shown in FIG. 3B, in the method of manufacturing a field effect transistor having the above structure 12, the upper layer 7 is composed of an upper layer lower layer 72 containing a high concentration of n-type impurities, and an upper layer lower layer 72. And an upper layer upper layer 73 whose n-type impurity concentration contained therein is lower than the n-type impurity concentration of the upper layer lower layer 72, the gate electrode 11 is formed in contact with the surface of the upper layer upper layer 73. It is supposed to be. Thereby, electrons can be supplied from the upper layer lower layer 72 to the channel layer 100, and
Since the n-type impurity concentration of the upper layer upper layer 73 in contact with the gate electrode 11 is low, the leak current in the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage is improved. be able to.

Structure 14. A method of manufacturing a field effect transistor according to Embodiment 2 of the present invention (claim 28) is
As shown in FIG. 3 (b), in the method of manufacturing a field effect transistor having the above structure 12 or 13, the upper layer 7
Includes an undoped spacer layer 71 formed in contact with the surface of the channel upper layer 6. As a result, electrons traveling in the vicinity of the interface of the channel layer 100 with the upper layer 7 can be prevented from being scattered by the n-type impurity that is a donor included in the upper layer 7, and high frequency and high gain can be obtained. ， High efficiency operation characteristics can be further improved.

Structure 15. A method of manufacturing a field effect transistor according to the second embodiment of the present invention (claim 29) is
As shown in FIG. 3 (b), in the method for manufacturing a field effect transistor according to any one of the configurations 12 to 14, the lower layer 4 includes an undoped spacer layer 42 as its uppermost layer. is there. Accordingly, electrons traveling near the interface of the channel layer 100 with the lower layer 4 can be prevented from being scattered by the n-type impurity that is a donor included in the lower layer 4, and high frequency,
High gain and high efficiency operation characteristics can be further improved.

Embodiment 2 FIG. A field effect transistor according to an example of the second embodiment of the present invention and a method for manufacturing the same will be described. FIG. 3A shows a sectional view of the field effect transistor according to the second embodiment. This field effect transistor is also a HEMT as in the first embodiment, and has a high resistance i-G grown on the semi-insulating GaAs substrate 1.
aAs buffer layer 2, and i-Al _0.2 Ga _0.8 As buffer layer 3 and a 10 nm-thick n-type Al _0.2 Ga containing a relatively high concentration of n-type impurities (Si) grown on this buffer layer 3. _0.8 As lower electron supply layer 4 (Si concentration: 1.5 × 10 ¹⁸ cm ⁻³ ), low impurity concentration (undoped) i-GaAs channel lower layer 20 nm thick 5, low impurity concentration (undoped) i 20 nm thick -In _0.15 Ga
_0.85 As channel upper layer 6, 40 nm thick n-type Al _0.2 Ga containing relatively high concentration n-type impurity (Si)
_0.8 As Upper electron supply layer 7 (Si concentration: 1.5 × 10 ¹⁸ c
m ^-3 ), and a semiconductor layer 101 composed of an n-type GaAs contact layer 8 (Si concentration: 3 × 10 ¹⁸ cm ^-3 ) containing a high concentration of n-type impurity (Si) and having a thickness of 100 nm, and the contact layer 8 A in ohmic contact with this layer formed above
A source electrode 9 and a drain electrode 10 made of uGe / Ni / Au, and a gate electrode 11 made of Ti / Al provided in a recess groove 13 formed by etching the contact layer 8 between the source electrode and the drain electrode. Composed of and. However, the contact between the gate electrode 11 and the upper electron supply layer 7 is a Schottky contact. Also,
In the figure, 100 is a channel layer composed of an upper channel layer 6 and a lower channel layer 5.

In the method for manufacturing the field effect transistor according to the second embodiment, first, as shown in FIG. 4, the semiconductor layers 101 including the buffer layers 2 and 3 and the channel layer 100 are grown on the semi-insulating GaAs substrate 1, After that, the field effect transistor shown in FIG. 3A is manufactured by using the same steps as those shown in FIGS. 2B to 2D in the first embodiment.

Further, as shown in FIG. 3 (b), Al _0.2 G
a _0.8 As upper electron supply layer 7 with an undoped i-Al _0.2 Ga _0.8 As spacer layer 71, Si having a thickness of 2 nm.
2.5 × 10 ¹⁸ cm ⁻³ Doped 20 nm thick n-type Al _0.2
Ga _0.8 As high concentration doping layer (upper layer lower layer) 72,
Alternatively, a low-concentration n-type Al _0.2 Ga _0.8 As low-concentration doping layer (upper layer upper layer) 73 having a thickness of 20 nm doped with 1 × 10 ¹⁷ cm ^{−3 of} Si may be laminated. Furthermore, Al
_0.2 Ga _0.8 As Lower electron supply layer 4 with Si 1.5 × 10
¹⁸ cm ^-3 doped 10 nm thick n-type Al _0.2 Ga _0.8
The As high-concentration doping layer 41 and the undoped i-Al _0.2 Ga _0.8 As spacer layer 42 having a thickness of 2 nm may be laminated. The low-concentration doping layer (upper layer upper layer) 73 is made of undoped Al _0.2 Ga _0.8 A.
You may comprise by s.

In the second embodiment, the channel layer 100 composed of the i-InGaAs layer and the n-type GaAs layer in the first embodiment is replaced by the i-InGaAs channel upper layer as shown in FIG. 3 (a). 6 and an i-GaAs channel lower layer 5, and n containing a high concentration of n-type impurities so as to sandwich the channel layer 100.
A lower electron supply layer 4 and an upper electron supply layer 7 made of AlGaAs of the type are provided, and electrons traveling in the channel layer 100 are supplied from both the lower electron supply layer 4 and the upper electron supply layer 7. Also in the second embodiment, the above first embodiment is used.
Similarly, in the channel layer 100 below the gate electrode 11 when a high drain voltage is applied, the i-InGaAs channel upper layer 6 becomes a charge depletion layer, and the i-GaAs channel lower layer 5 serves as a main path of a current flowing through the channel layer 100. Become. Therefore, the impact ionization in the channel layer 100 is
It is suppressed as compared with the impact ionization in the InGaAs channel layer of the conventional field effect transistor described above, and the breakdown voltage of the channel can be increased. Further, since the i-InGaAs channel upper layer 6 and the n-type GaAs channel lower layer 5 both serve as a current path between the source and the gate, a low source resistance equivalent to that of the conventional field effect transistor described above can be obtained, and high frequency, high gain, Highly efficient operation becomes possible.

In addition, the AlGa shown in FIG.
The As upper electron supply layer 7 is an undoped spacer layer 71,
High concentration doping layer 72 and low concentration doping layer 73
In addition, the AlGaAs lower electron supply layer 4 is composed of a high-concentration doping layer 41 and an undoped spacer layer 42.
In the field effect transistor configured as described above, since the undoped spacer 71 is provided between the high-concentration doping layer 72 and the i-InGaAs channel upper layer 6, the upper electron supply layer 7 of the channel upper layer 6 is formed. Electrons flowing in the vicinity of the interface can be prevented from being scattered by the n-type impurity that is a donor contained in the upper electron supply layer 7, and the high-concentration doping layers 41 and i can be prevented.
-Because the undoped spacer layer 42 is provided between the InGaAs channel lower layer 5 and the InGaAs channel lower layer 5,
Electrons traveling in the vicinity of the interface with the lower electron supply layer 41 in the inside can be suppressed from being scattered by the n-type impurity that is a donor contained in the lower electron supply layer 4, and thus FIG. A source resistance lower than that of the field effect transistor shown in FIG. 3 can be obtained, and high frequency, high gain, and high efficiency operation characteristics can be further improved. Further, since the uppermost layer of the upper electron supply layer 7 is the low-concentration doping layer 73, the gate electrode 11 comes into contact with the low-concentration doping layer 73, as shown in FIG. 3 (a) above. It is possible to reduce the leak current in the Schottky contact between the gate electrode 11 and the upper electron supply layer 7 and increase the gate breakdown voltage, as compared with the case where the upper electron supply layer 7 is a uniformly highly doped layer. it can.

Although n-type AlGaAs is used for the upper electron supply layer 7 in the second embodiment, n-type InGaP or n-type GaAs may be used instead. In addition, the second embodiment
Then, n-type AlGaAs was used for the lower electron supply layer 4,
N-type InGaP may be used for this.

Embodiment 3 Configuration 1. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention (claim 12) includes a semiconductor layer 101 provided on a semiconductor substrate 1 including a channel layer 61, and a surface of the semiconductor layer 101. In the field-effect transistor including the gate electrode 11 provided on the surface of the semiconductor layer 101 and the source electrode 9 and the drain electrode 10 provided on the surface of the semiconductor layer 101 so as to sandwich the gate electrode 11, the channel layer 61 is The In composition thereof includes the composition transition channel layer 61 made of InGaAs that increases from the semiconductor substrate 1 side toward the semiconductor layer 101 surface side. As a result, in the InGaAs composition transition channel layer 61 under the gate electrode 11 when a high drain voltage is applied, a region on the substrate side, that is, a region having a small In composition ratio and a composition close to GaAs flows through the channel layer 61. It serves as the main path of the current, and unlike the conventional field effect transistor described above, the current does not flow through the InGaAs layer having a large In composition ratio, so that impact ionization in the channel layer is suppressed and the breakdown voltage of the channel is increased. be able to. For this reason,
This field effect transistor is suitable for high output operation. Further, between the source electrode 9 and the gate electrode 11, the entire region of the InGaAs composition transition channel layer 61 serves as a current path, so that the low source resistance equivalent to that of the field effect transistor using the conventional InGaAs layer as the channel layer is used. Therefore, high frequency, high gain and high efficiency operation is possible.

Configuration 2. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention (claim 13) is the same as the field effect transistor of the above configuration 1,
The semiconductor layer 101 is provided above the channel layer 61,
InGaAs which is provided in contact with the composition transition channel layer 61 and constitutes the uppermost layer of the composition transition channel layer
The upper layer 7 made of a semiconductor having a smaller electron affinity is included. As a result, electrons serving as carriers can be supplied to the composition transition channel layer 61 by using the upper layer 7 as an electron supplying layer. By making the channel layer 61 an undoped layer, the electrons serving as carriers are generated by the donor. The channel layer 61 can travel without being subjected to scattering. Therefore, it is possible to obtain a field effect transistor having a low source resistance and capable of high frequency, high gain, and high efficiency operation.

Configuration 3. As shown in FIG. 5 (b), the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor of the above-mentioned configuration 2, except that the upper layer 7 is formed with a high-concentration n-type impurity. And an upper layer upper layer 73 provided on the upper layer lower layer 72, the n type impurity concentration of which is lower than the n type impurity concentration of the upper layer lower layer 72. Is. Thereby, from the upper layer lower layer 72,
Electrons can be supplied to the channel layer 61 and n of the upper layer upper layer 73 in contact with the gate electrode 11 is n.
Since the type impurity concentration is low, the leak current at the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Structure 4. As shown in FIG. 5 (b), the field effect transistor according to the third embodiment of the present invention is the same as in the field effect transistor of the above-mentioned constitution 2 or 3, but the upper layer 7 is replaced by the composition transition channel. Undoped spacer layer 71 provided in contact with the upper layer 61
Is included. As a result, electrons traveling in the vicinity of the interface between the channel layer 61 and the upper layer 7 can be prevented from being scattered by the n-type impurity that is a donor included in the upper layer 7, and high frequency and high gain can be achieved. ， High efficiency operation characteristics can be further improved.

Structure 5. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention is the field effect transistor according to any one of the above configurations 2 to 4, in which the upper layer 7 is made of GaAs or AlG.
It is made of aAs or InGaP. As a result, the electron affinity of the upper layer 7 can be made smaller than that of InGaAs forming the channel upper layer 61, and the upper layer 7 can be used as an electron supply layer. Thus, it is possible to obtain a field effect transistor capable of highly efficient operation.

Configuration 6. As shown in FIG. 5, a field effect transistor according to a third embodiment of the present invention (claim 17) is the field effect transistor according to any one of the above configurations 2 to 5, in which the semiconductor layer 101 is replaced by the channel layer 61. And a lower layer 4 made of a semiconductor having an electron affinity lower than that of GaAs, which is provided below the substrate. Thereby, as described above, not only the upper layer 7 can be used as the electron supply layer, but the lower layer 4 can be used as the electron supply layer, and the surface of the electrons supplied as carriers to the channel layer 61 can be obtained. The density can be made higher than that when electrons are supplied only from the upper layer 7, and a field effect transistor having a lower source resistance and capable of high frequency, high gain, and high efficiency operation can be obtained.

Structure 7. As shown in FIG. 5 (b), the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor having the above-mentioned structure 6, in which the lower layer 4 is replaced by the composition transition channel layer 61. And an undoped spacer layer 42 in contact with. As a result, electrons traveling in the vicinity of the interface of the channel layer 61 with the lower layer 4 can be prevented from being scattered by the n-type impurity that is a donor included in the lower layer 4, and high frequency and high gain can be obtained. ， High efficiency operation characteristics can be further improved.

Structure 8. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor having the configuration 6 or 7, but the lower layer 4 is AlGaAs or InG.
It is composed of aP. As a result, the electron affinity of the lower layer 4 can be made smaller than the electron affinity of InGaAs forming the channel layer 61, and the lower layer 4 can be used as an electron supply layer, so that the source resistance is low as described above. A field effect transistor capable of high frequency, high gain and high efficiency operation can be obtained.

Structure 9. As shown in FIG. 5, a field effect transistor according to a third embodiment of the present invention is the same as the semiconductor substrate 1 and the semiconductor layer 1 in the field effect transistor according to any one of the configurations 1 to 8.
And buffer layers 2 and 3 made of a high-resistance semiconductor provided between the buffer layers 1 and 01. As a result, the semiconductor layer 101 formed on the buffer layers 2 and 3 can be a layer made of a good semiconductor crystal with few crystal defects, and the electric characteristics of the field effect transistor can be improved. it can.

Structure 10. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor according to any one of the configurations 1 to 9, except that the semiconductor substrate 1 is made of semi-insulating G
This is an aAs substrate. This facilitates electrical isolation between the elements when a plurality of elements are formed on the semiconductor substrate 1, and the parasitic capacitance between the operation layer of the field effect transistor and the electrode and the semiconductor substrate. And a field effect transistor excellent in high frequency operation characteristics is obtained.

Structure 11. As shown in FIG. 5, the field effect transistor according to the third embodiment of the present invention (claim 22) is the field effect transistor according to any one of the above configurations 1 to 10, in which the gate electrode 11 and the upper layer 7 are provided. It is assumed that the semiconductor layer 10 is formed on the surface.
1 includes a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities provided in regions on both sides of the gate electrode 11 on the surface of the upper layer 7, the source electrode 9, and the drain. The electrode 10 is formed on the surface of the contact layer 8. As a result, the contact resistance between the source electrode 9 and the drain electrode 10 and the semiconductor layer 101 can be reduced, and the impurity concentration of the gate electrode 11 is not on the contact layer 8 but on the contact layer 8. Since it is formed on the smaller surface of the upper layer 7, the leak current in the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Structure 12. A method of manufacturing a field effect transistor according to the third embodiment of the present invention (claim 30) is
A step of forming buffer layers 2 and 3 made of a high resistance semiconductor on the semi-insulating GaAs substrate 1 shown in FIG. 6, and a lower layer made of a semiconductor having an electron affinity lower than that of GaAs on the buffer layers 2 and 3. 4, its In composition is GaAs
A composition transition channel layer 61 composed of InGaAs increasing from the substrate side upward, and this composition transition channel layer 6
A step of forming a semiconductor layer 101 in which an upper layer 7 made of a semiconductor having an electron affinity smaller than that of InGaAs forming the surface portion of No. 1 and a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities are sequentially stacked; 2 (b)-(d), a step of forming a source electrode 9 and a drain electrode 10 on the contact layer 8 whose contact with the contact layer 8 is ohmic contact, and the source electrode 9, And a step of forming a recess groove 13 by etching and removing the contact layer 8 in a region between the drain electrode 10 where a gate electrode 11 described later is to be formed, and the recess groove 13
And a step of forming the gate electrode 11 whose contact with the upper layer 7 becomes a Schottky contact therein. In the field effect transistor manufactured by this, InGaAs under the gate electrode 11 when a high drain voltage is applied is used.
In the composition transition channel layer 61, a region on the substrate side, that is, a region where the composition ratio of In is small and has a composition close to GaAs serves as a main path of a current flowing through the channel layer 61, and like the above-described conventional field effect transistor. Since the current does not flow through the InGaAs layer having a large In composition ratio, impact ionization in the channel layer is suppressed, and the breakdown voltage of the channel can be increased. Therefore, this field effect transistor is suitable for high output operation. Further, between the source electrode 9 and the gate electrode 11, the entire region of the InGaAs channel layer 61 serves as a current path, so that a low source resistance equivalent to that of the field effect transistor using the conventional InGaAs layer as the channel layer is obtained. Therefore, high frequency, high gain, and high efficiency operation are possible.

Structure 13. A method of manufacturing a field effect transistor according to Embodiment 3 of the present invention (claim 31) is
As shown in FIG. 5 (b), in the method of manufacturing a field effect transistor having the above structure 12, the upper layer is formed on an upper layer lower layer containing a high concentration of n-type impurities, and on the upper layer lower layer. The gate electrode is formed on the upper layer upper layer, and the upper electrode upper layer has an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer. As a result, electrons can be supplied from the upper layer lower layer 72 to the channel layer 61, and the n-type impurity concentration of the upper layer upper layer 73 in contact with the gate electrode 11 is low, so that the gate electrode 11 and It is possible to reduce the leak current in the Schottky contact with the upper layer 7 and improve the gate breakdown voltage.

Structure 14. A method of manufacturing a field effect transistor according to the third embodiment of the present invention (claim 32) is
As shown in FIG. 5B, in the method of manufacturing a field effect transistor having the above structure 12 or 13, the upper layer 7
Includes an undoped spacer layer 71 formed in contact with the surface of the composition transition channel layer 61. As a result, electrons traveling in the vicinity of the interface between the channel layer 61 and the upper layer 7 can be prevented from being scattered by the n-type impurity that is a donor included in the upper layer 7, and high frequency and high gain can be achieved. ， High efficiency operation characteristics can be further improved.

Structure 15. A method of manufacturing a field effect transistor according to the third embodiment of the present invention (claim 33) is
As shown in FIG. 5 (b), in the method of manufacturing a field effect transistor according to any one of the configurations 12 and 14, the lower layer 4 includes an undoped spacer layer 42 as its uppermost layer. is there. Thus, electrons traveling near the interface of the channel layer 61 with the lower layer 4 can be prevented from being scattered by the n-type impurity that is a donor included in the lower layer 4, and high frequency,
High gain and high efficiency operation characteristics can be further improved.

Example 3. A field effect transistor according to an example of the third embodiment of the present invention and a method for manufacturing the same will be described. FIG. 5A shows a sectional view of the field effect transistor according to the third embodiment. This field effect transistor is also a HEMT as in the first and second embodiments, and has a high resistance i-GaAs buffer layer 2 grown on a semi-insulating GaAs substrate 1 and i-Al _0.2 Ga _0.8.
As buffer layer 3 and a thickness 10 containing a relatively high concentration of n-type impurities (Si) grown on this buffer layer 3.
nm n-type Al _0.2 Ga _0.8 As lower electron supply layer 4 (S
i concentration: 1.5 × 10 ¹⁸ cm ⁻³ ), low impurity concentration (undoped) 40 nm thick i-In _X Ga _1-X As composition transition channel layer 61 (x = 0 → 0.25), relatively high 40 nm thick n-type Al containing a high concentration of n-type impurities (Si)
_0.2 Ga _0.8 As Upper electron supply layer 7 (Si concentration: 1.5 ×
10 ¹⁸ cm ^-3 ), and a high concentration n-type impurity (Si) -containing n-type GaAs contact layer 8 (Si
Concentration: 3 × 10 ¹⁸ cm ⁻³ ), a semiconductor layer 101 made of AuGe / Ni / Au, which is in ohmic contact with the semiconductor layer 101 formed on the contact layer 8, and a drain electrode 10. Recess groove 13 formed by etching the contact layer 8 between the source electrode and the drain electrode
And a gate electrode 11 made of Ti / Al provided therein. However, the In composition ratio x of the i-In _X Ga _1-X As composition transition channel layer 61 is equal to that of the channel layer 6
X = 0 (that is, GaAs) at the interface between 1 and the lower electron supply layer 4, and x at the interface between the upper electron supply layer 7 and
= 0.25, and x changes from 0 to 0.25 in an inclined or stepwise manner in the region between them.
Further, the contact between the gate electrode 11 and the upper electron supply layer 7 is
It is a Schottky contact.

In the method of manufacturing the field effect transistor according to the third embodiment, first, as shown in FIG. 6, the buffer layers 2 and 3 and the semiconductor layer 101 are grown on the semi-insulating GaAs substrate 1, and then the above embodiment is performed. The field effect transistor shown in FIG. 5 (a) is manufactured by using the same steps as those shown in FIGS. 2 (b)-(d) in FIG.

Further, as shown in FIG. 5 (b), Al _0.2 G
a _0.8 As upper electron supply layer 7 with an undoped i-Al _0.2 Ga _0.8 As spacer layer 71, Si having a thickness of 2 nm.
2.5 × 10 ¹⁸ cm ⁻³ Doped 20 nm thick n-type Al _0.2
Ga _0.8 As high concentration doping layer (upper layer lower layer) 72,
Alternatively, a low-concentration n-type Al _0.2 Ga _0.8 As low-concentration doping layer (upper layer upper layer) 73 having a thickness of 20 nm doped with 1 × 10 ¹⁷ cm ^{−3 of} Si may be laminated. Further, the lower layer 4 is doped with Si at 1.5 × 10 ¹⁸ cm ⁻³ and has an n-thickness of 10 nm.
A type Al _0.2 Ga _0.8 As high-concentration doping layer 41 and an undoped i-Al _0.2 Ga _0.8 As spacer layer 42 having a thickness of 2 nm may be laminated. The low-concentration doping layer (upper layer upper layer) 73 may be made of undoped Al _0.2 Ga _0.8 As.

In the third embodiment, as shown in FIG. 5, the In composition ratio of InGaAs forming the channel layer 61 is from the lower electron supply layer 4 side to the upper electron supply layer 7 side.
The structure is such that it increases from 0 (that is, GaAs) toward the side in an inclined or stepwise manner. This allows
When a high drain voltage is applied, i-I under the gate electrode 11
A portion of the nGaAs channel layer 61 on the gate electrode side becomes a charge depletion layer, and a region on the substrate side having a small In composition ratio, that is, a composition close to GaAs serves as a main path of a current flowing through the channel layer. Therefore, as in the first and second embodiments, the impact ionization in this layer is suppressed as compared with the impact ionization in the InGaAs channel layer of the conventional field effect transistor described above, and the breakdown voltage of the channel is increased. Can be made. Further, since all the layers of the i-InGaAs channel layer 61 serve as a current path between the source and the gate, a low source resistance equivalent to that of the conventional field effect transistor described above can be obtained, and high frequency, high gain and high efficiency operation is possible. Becomes

In addition, the AlGa shown in FIG.
The As upper electron supply layer 7 is an undoped spacer layer 71,
High concentration doping layer 72 and low concentration doping layer 73
In addition, the AlGaAs lower electron supply layer 4 is composed of a high-concentration doping layer 41 and an undoped spacer layer 42.
In the field effect transistor configured as described above, since the undoped spacer layer 71 is provided between the high-concentration doping layer 72 and the InGaAs composition transition channel layer 61, the upper electron supply layer 7 in the channel layer 61 is provided. Electrons traveling near the interface with the upper electron supply layer 7
It is possible to suppress scattering by an n-type impurity that is a donor contained in the channel layer 61, and the undoped spacer 42 is provided between the high-concentration doping layer 41 and the channel layer 61. The electrons traveling near the interface with the lower electron supply layer 4 in the inside can be suppressed from being scattered by the n-type impurity that is a donor included in the lower electron supply layer 4, and thus the electron shown in FIG. A source resistance lower than that of the field effect transistor shown in FIG. 3 can be obtained, and high frequency, high gain, and high efficiency operation characteristics can be further improved. Further, since the uppermost layer of the upper electron supply layer 7 is the low-concentration doping layer 73, the gate electrode 11 comes into contact with the low-concentration doping layer 73, as shown in FIG. 5 (a) above. Upper electron supply layer 7
Is uniformly doped with high concentration, the leakage current in the Schottky contact between the gate electrode 11 and the upper electron supply layer 7 can be reduced, and the gate breakdown voltage can be increased.

The upper electron supply layer 7 is made of n-type AlGa.
As was used, but n-type InGaP or n-type G
You may use aAs. In addition, the lower electron supply layer 4 also has n
Type AlGaAs was used, but n type InGaP may be used.

Fourth Embodiment Configuration 1. As shown in FIG. 7, the field effect transistor (Claim 1) according to the fourth embodiment of the present invention includes a semiconductor layer 101 provided on a semiconductor substrate 1 including a channel layer 100 and a surface of the semiconductor layer 101. In the field effect transistor including the gate electrode 11 provided on the surface of the semiconductor layer 101 and the source electrode 9 and the drain electrode 10 provided on the surface of the semiconductor layer 101 so as to sandwich the gate electrode 11, the channel layer 100 is The channel lower layer 55 made of GaAs and the channel upper layer 66 made of InGaAs provided above the channel lower layer 55 are included. As a result, in the channel layer 100 below the gate electrode 11 when a high drain voltage is applied, the InGaAs channel upper layer 66 located on the gate electrode side becomes a charge depletion layer, and the GaAs channel lower layer 55 becomes the main path of the current flowing through the channel layer. Therefore, the current does not flow through the InGaAs layer unlike the conventional field effect transistor described above. Therefore, impact ionization in the channel layer 100 is suppressed, the breakdown voltage of the channel can be increased, and this field effect transistor can be made suitable for high output operation. Further, between the source electrode 9 and the gate electrode 11, both the InGaAs channel upper layer 66 and the GaAs channel lower layer 55 serve as a current path, so that the field effect transistor using the conventional InGaAs layer as a channel layer is low. A source resistance is obtained, which enables high frequency, high gain, and high efficiency operation.

Configuration 2. As shown in FIG. 7, the field effect transistor according to the fourth embodiment of the present invention (claim 9) is provided between the semiconductor substrate 1 and the semiconductor layer 101 in the field effect transistor of the above configuration 1. And a buffer layer 2 made of a high resistance semiconductor. As a result, the semiconductor layer 101 formed on the buffer layer 2 can be a layer made of a good semiconductor crystal with few crystal defects, and the electric characteristics of the field effect transistor can be made excellent.

Configuration 3. As shown in FIG. 7, the field effect transistor according to the fourth embodiment of the present invention (claim 10) is the field effect transistor according to the above configuration 1 or 2, wherein the semiconductor substrate 1 is a semi-insulating GaAs substrate. It is a thing. This facilitates electrical isolation between elements when a plurality of elements are formed on the semiconductor substrate 1, and also reduces the parasitic capacitance between the operating layer of the field effect transistor and the electrode and the semiconductor substrate. A field effect transistor that is reduced and has excellent high-frequency operating characteristics can be obtained.

Configuration 4. As shown in FIG. 7, the field effect transistor according to the fourth embodiment of the present invention (claim 11) is the field effect transistor according to any one of the above configurations 1 to 3, in which the gate electrode 11 is replaced by the upper layer 77. It is assumed that the semiconductor layer 101 is formed on the surface.
Includes a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities provided in regions on both sides of the gate electrode 11 on the surface of the upper layer 77, and the source electrode 9 and the drain electrode. 10 is formed on the surface of the contact layer 8. As a result, the contact resistance between the source electrode 9 and the drain electrode 10 and the semiconductor layer 101 can be reduced, and the impurity concentration of the gate electrode 11 is not on the contact layer 8 but on the contact layer 8. Since it is formed on the smaller surface of the upper layer 7, the leak current in the Schottky contact between the gate electrode 11 and the upper layer 7 can be reduced, and the gate breakdown voltage can be improved.

Configuration 5. A method of manufacturing a field effect transistor according to a fourth embodiment of the present invention (claim 23) comprises a step of forming a buffer layer 2 made of a high resistance semiconductor on a semi-insulating GaAs substrate 1 shown in FIG. On the buffer layer 2, a channel lower layer 55 made of GaAs, InG
a step of forming a semiconductor layer in which a channel upper layer 66 made of aAs, an upper layer 77 for forming a Schottky gate, and a contact layer 8 made of a semiconductor containing a high concentration of n-type impurities are sequentially stacked; (b)-(d), a step of forming a source electrode 9 and a drain electrode 10 on the contact layer 8 whose contact with the contact layer 8 is ohmic contact; A step of etching and removing the contact layer 8 in a region between the drain electrodes 10 where a gate electrode 11 to be described later is to be formed to form the recess groove 13, and a contact with the upper layer 77 in the recess groove 13 is shot. And a step of forming the gate electrode 11 that makes a key contact. In the field effect transistor thus manufactured, in the channel layer 100 under the gate electrode 11 when a high drain voltage is applied, the InGaAs channel upper layer 66 becomes a charge depletion layer, so that the GaAs channel lower layer 55 is the channel layer 10.
It serves as the main path of the current flowing through 0, and unlike the above-described conventional field effect transistor, the current does not flow through the InGaAs layer, so that impact ionization in the channel layer is suppressed and the breakdown voltage of the channel is increased. be able to. Therefore, this field effect transistor is suitable for high output operation. In addition, the InGaAs channel upper layer 66 is provided between the source electrode 9 and the gate electrode 11.
Since both the GaAs channel lower layer 55 and the GaAs channel lower layer serve as a current path, a low source resistance equivalent to that of the field effect transistor using the conventional InGaAs layer for the channel layer can be obtained. It will be possible.

Embodiment 4 FIG. A field effect transistor according to an example of the fourth embodiment of the present invention and a manufacturing method thereof will be described. FIG. 7 shows a sectional view of the field effect transistor according to the fourth embodiment. This field effect transistor includes a high resistance i-GaAs buffer layer 2 formed on a semi-insulating GaAs substrate 1 and a relatively high concentration n-type impurity (Si) grown on the buffer layer 2. Containing 20 nm-thick n-type GaAs channel lower layer 55 (S
i concentration: 6 × 10 ¹⁷ cm ⁻³ ), 20 nm thick n-type In _0.15 Ga containing a relatively high concentration of n-type impurity (Si)
_0.85 As channel upper layer 66 (Si concentration: 6 × 10 ¹⁷ c
m ^-3 ), an n-type GaAs Schottky gate forming layer 77 (Si concentration: 1 × 10 ¹⁷ cm ^-3 ) containing a relatively low concentration of n-type impurities (Si) and having a thickness of 40 nm, and a high concentration of n. -Type GaAs containing 100-nm-thick impurities (Si)
A semiconductor layer 101 made of the contact layer 8 (Si concentration: 3 × 10 ¹⁸ cm ⁻³ ), a source electrode 9 made of AuGe / Ni / Au in ohmic contact with this layer formed on the contact layer 8, and It is composed of a drain electrode 10 and a gate electrode 11 made of Ti / Al provided in a recess groove 13 formed by etching the contact layer 8 between the source electrode and the drain electrode. Further, the contact between the gate electrode 11 and the Schottky gate formation layer 77 is
It is a Schottky contact. In the figure, 1
A channel layer 00 is composed of the channel upper layer 66 and the channel lower layer 55.

In the method of manufacturing the field effect transistor according to the fourth embodiment, first, as shown in FIG. 8, the buffer layer 2 and the semiconductor layer 101 are grown on the semi-insulating GaAs substrate 1, and then the first embodiment described above. 2 (b)-(d), the field effect transistor shown in FIG. 7 is manufactured by using the same steps as those shown in FIGS.

In the fourth embodiment, the channel upper layer composed of i-InGaAs in the first embodiment is changed to the channel upper layer 66 composed of n-type InGaAs as shown in FIG. 7, and further composed of n-type AlGaAs. The upper electron supply layer that has been formed is the Schottky gate formation layer 77 made of n-type GaAs. As a result, similarly to the first embodiment, in the channel layer 100 when a high drain voltage is applied, the n-type InGaA under the gate electrode 11 is formed.
The s-channel upper layer 66 becomes a charge depletion layer, and the n-type GaAs channel lower layer 55 becomes the main path of the current flowing through the channel layer 100. Therefore, this GaAs channel lower layer 5
The impact ionization in No. 5 is suppressed as compared with the impact ionization in the InGaAs channel layer in the above-mentioned conventional field effect transistor, and the breakdown voltage of the channel can be increased. Further, since the n-type InGaAs channel upper layer 66 and the n-type GaAs channel lower layer 55 both serve as a current path between the source and the gate, a low source resistance equivalent to that of the conventional field effect transistor described above can be obtained, and high frequency, high gain, Highly efficient operation becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method for manufacturing the field effect transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a method for manufacturing a field effect transistor according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a field effect transistor according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a method for manufacturing a field effect transistor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a field effect transistor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a method for manufacturing a field effect transistor according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a conventional field effect transistor.

[Explanation of symbols]

1 semi-insulating GaAs substrate, 2 i-GaAs buffer layer, 3 i-AlGaAs buffer layer, 4 n-type AlG
aAs lower electron supply layer (lower layer), 5 i-GaAs channel lower layer, 6 i-InGaAs channel upper layer, 7
n-type AlGaAs upper electron supply layer (upper layer), 8 n-type GaAs contact layer, 9 source electrode, 10 drain electrode, 11 gate electrode, 12 resist pattern,
13 recess grooves, 41 n-type AlGaAs high-concentration doping layer, 42 i-AlGaAs spacer layer, 55 n
Type GaAs channel lower layer, 61 i-In _X Ga _1-X A
s (x = 0 → 0.25) composition transition channel layer, 65 i
-InGaAs channel layer, 66 n-type InGaAs channel upper layer, 71 i-AlGaAs spacer layer, 72
n-type AlGaAs high-concentration doping layer (upper layer lower layer), 73 n-type AlGaAs low-concentration doping layer (upper layer upper layer), 75 n-type GaAs high-concentration doping layer (upper layer lower layer), 76 n-type GaAs low-concentration doping layer ( Upper layer upper layer), 77 n-type GaAs Schottky gate formation layer (upper layer), 100 channel layer, 101
Semiconductor layer.

Claims (33)

[Claims] 1. A semiconductor layer including a channel layer, which is provided on a semiconductor substrate, a gate electrode provided on the surface of the semiconductor layer, and provided on the surface of the semiconductor layer so as to sandwich the gate electrode. In a field effect transistor provided with a source electrode and a drain electrode, the channel layer is a channel lower layer made of GaAs,
A field effect transistor comprising an upper channel layer made of InGaAs provided above the lower channel layer. 2. The field effect transistor according to claim 1, wherein the semiconductor layer is provided above the channel layer and in contact with the channel upper layer, and has a smaller electron affinity than InGaAs forming the channel upper layer. A field effect transistor including an upper layer made of a semiconductor. 3. The field effect transistor according to claim 2, wherein the upper layer is an upper layer lower layer containing a high concentration of n-type impurities, and the n-type impurity contained therein is provided on the upper layer lower layer. An upper layer upper layer having a concentration lower than the n-type impurity concentration of the upper layer lower layer. 4. The field effect transistor according to claim 2, wherein the upper layer includes an undoped spacer layer provided in contact with the channel upper layer. 5. The field effect transistor according to claim 2, wherein the upper layer is GaAs, AlGaAs, or InG.
A field effect transistor comprising aP. 6. The field effect transistor according to claim 2, wherein the semiconductor layer is provided below the channel layer.
A field-effect transistor including a lower layer made of a semiconductor having an electron affinity lower than that of GaAs. 7. The field effect transistor according to claim 6, wherein the lower layer includes an undoped spacer layer in contact with the channel lower layer. 8. The field effect transistor according to claim 6 or 7, wherein the lower layer is made of AlGaAs or InGaP. 9. The field effect transistor according to claim 1, further comprising a buffer layer made of a high-resistance semiconductor provided between the semiconductor substrate and the semiconductor layer. Field effect transistor to be. 10. The field effect transistor according to claim 1, wherein the semiconductor substrate is a semi-insulating GaAs substrate. 11. The field effect transistor according to claim 1, wherein the gate electrode is formed on a surface of the upper layer, and the semiconductor layer is on a surface of the upper layer. A contact layer made of a semiconductor containing a high concentration of n-type impurities, which is provided on both sides of the gate electrode, and the source electrode and the drain electrode are formed on the surface of the contact layer. A field-effect transistor characterized by being present. 12. A semiconductor layer including a channel layer, which is provided on a semiconductor substrate, a gate electrode provided on the surface of the semiconductor layer, and provided on the surface of the semiconductor layer so as to sandwich the gate electrode. In a field effect transistor having a source electrode and a drain electrode, the channel layer is made of InGaAs whose In composition increases from the semiconductor substrate side toward the semiconductor layer surface side.
A field effect transistor comprising a composition transition channel layer comprising 13. The field effect transistor according to claim 12, wherein the semiconductor layer constitutes an uppermost portion of the composition transition channel layer, which is provided above the channel layer and in contact with the composition transition channel layer. A field-effect transistor including an upper layer made of a semiconductor having a smaller electron affinity than InGaAs. 14. The field effect transistor according to claim 13, wherein the upper layer is an upper layer lower layer containing a high-concentration n-type impurity, and the n-type included therein is provided on the upper layer lower layer. A field effect transistor, comprising: an upper layer upper layer having an impurity concentration lower than the n-type impurity concentration of the upper layer lower layer. 15. The field effect transistor according to claim 13, wherein the upper layer includes an undoped spacer layer provided in contact with the composition transition channel layer. 16. The field effect transistor according to claim 13, wherein the upper layer is GaAs, AlGaAs, or InG.
A field effect transistor comprising aP. 17. The field effect transistor according to claim 13, wherein the semiconductor layer is provided below the channel layer.
A field-effect transistor including a lower layer made of a semiconductor having an electron affinity lower than that of GaAs. 18. The field effect transistor according to claim 17, wherein the lower layer includes an undoped spacer layer provided in contact with the composition transition channel layer. 19. The field effect transistor according to claim 17, wherein the lower layer is made of AlGaAs or InGaP. 20. The field-effect transistor according to claim 12, further comprising a buffer layer made of a high-resistance semiconductor provided between the semiconductor substrate and the semiconductor layer. Field effect transistor to be. 21. The field effect transistor according to claim 12, wherein the semiconductor substrate is a semi-insulating GaAs substrate. 22. The field effect transistor according to claim 12, wherein the gate electrode is formed on the surface of the upper layer, and the semiconductor layer is on the surface of the upper layer. A contact layer made of a semiconductor containing a high concentration of n-type impurities, which is provided on both sides of the gate electrode, and the source electrode and the drain electrode are formed on the surface of the contact layer. A field-effect transistor characterized by being present. 23. A step of forming a buffer layer made of a high resistance semiconductor on a semi-insulating GaAs substrate, and a channel lower layer made of GaAs on the buffer layer,
A step of forming a semiconductor layer in which a channel upper layer made of InGaAs, an upper layer made of a semiconductor having an electron affinity lower than that of InGaAs forming the channel upper layer, and a contact layer made of a semiconductor containing a high concentration of n-type impurities are sequentially stacked. And a step of forming, on the contact layer, a source electrode and a drain electrode whose contact with the contact layer is an ohmic contact, and a gate electrode described below between the source electrode and the drain electrode should be formed. And a step of forming a recess groove by etching away the contact layer in the region, and a step of forming a gate electrode in the recess groove, the gate electrode being in Schottky contact with the upper layer. Method for manufacturing field effect transistor. 24. The method of manufacturing a field effect transistor according to claim 23, wherein the upper layer contains an upper layer lower layer containing a high concentration of n-type impurities, and the upper layer lower layer contains the upper layer lower layer. an upper layer upper layer having an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer, wherein the gate electrode is formed in contact with the upper layer upper layer surface. . 25. The method for manufacturing a field effect transistor according to claim 23, wherein the upper layer includes an undoped spacer layer formed in contact with the surface of the channel upper layer. Manufacturing method. 26. A step of forming a buffer layer made of a high-resistance semiconductor on a semi-insulating GaAs substrate, a lower layer made of a semiconductor having an electron affinity lower than that of GaAs, a channel lower layer made of GaAs, on the buffer layer. A step of forming a semiconductor layer in which a channel upper layer made of InGaAs, an upper layer made of a semiconductor having an electron affinity lower than that of InGaAs forming the channel upper layer, and a contact layer made of a semiconductor containing a high concentration of n-type impurities are sequentially stacked. And a step of forming, on the contact layer, a source electrode and a drain electrode whose contact with the contact layer is an ohmic contact, and a gate electrode described below between the source electrode and the drain electrode should be formed. Etching away the contact layer in the region to form a recess groove; Method of manufacturing a field effect transistor which comprises a step of forming a gate electrode contact is a Schottky contact between the upper layer in the groove. 27. The method of manufacturing a field effect transistor according to claim 26, wherein the upper layer includes an upper layer lower layer containing a high-concentration n-type impurity, and an upper layer lower layer formed on the upper layer lower layer. An upper layer upper layer having an n-type impurity concentration lower than that of the upper layer lower layer, the gate electrode being formed in contact with the upper layer upper layer surface. Method. 28. The field effect transistor according to claim 26, wherein the upper layer includes an undoped spacer layer formed in contact with the surface of the channel upper layer. Manufacturing method. 29. The method of manufacturing a field effect transistor according to claim 26, wherein the lower layer includes an undoped spacer layer as an uppermost layer thereof. . 30. A step of forming a buffer layer made of a semiconductor having a high resistance on a semi-insulating GaAs substrate, a lower layer made of a semiconductor having an electron affinity lower than that of GaAs, and an In composition thereof being GaAs A composition transition channel layer made of InGaAs increasing upward from the substrate side, an upper layer made of a semiconductor having an electron affinity smaller than that of InGaAs forming the surface portion of the composition transition channel layer, a semiconductor containing a high concentration of n-type impurities A step of forming a semiconductor layer formed by sequentially stacking contact layers made of, and forming a source electrode and a drain electrode on the contact layer, the source electrode and the drain electrode being in ohmic contact with the contact layer, and the source electrode , And etching the contact layer between the drain electrodes in a region where a gate electrode described later is to be formed. Forming a recessed groove to form a recessed groove, and a step of forming a gate electrode in the recessed groove, the gate electrode having a Schottky contact with the upper layer, the method for manufacturing a field effect transistor. . 31. The method of manufacturing a field effect transistor according to claim 30, wherein the upper layer includes an upper layer lower layer containing a high-concentration n-type impurity, and the upper layer lower layer containing the upper layer lower layer. An upper layer upper layer having an n-type impurity concentration lower than the n-type impurity concentration of the upper layer lower layer, and the gate electrode is formed in the upper layer upper layer. 32. The method of manufacturing a field effect transistor according to claim 30, wherein the upper layer includes an undoped spacer layer formed in contact with the surface of the composition transition channel layer. Effect transistor manufacturing method. 33. The method of manufacturing a field effect transistor according to claim 30, wherein the lower layer includes an undoped spacer layer as an uppermost layer thereof. .