WO2014128839A1 - Semiconductor device and power conversion device using same - Google Patents

Semiconductor device and power conversion device using same Download PDF

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WO2014128839A1
WO2014128839A1 PCT/JP2013/054069 JP2013054069W WO2014128839A1 WO 2014128839 A1 WO2014128839 A1 WO 2014128839A1 JP 2013054069 W JP2013054069 W JP 2013054069W WO 2014128839 A1 WO2014128839 A1 WO 2014128839A1
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conductivity type
emitter layer
layer
semiconductor device
concentration emitter
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PCT/JP2013/054069
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French (fr)
Japanese (ja)
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昌弘 増永
貴之 橋本
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株式会社 日立製作所
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Priority to PCT/JP2013/054069 priority Critical patent/WO2014128839A1/en
Priority to TW102147959A priority patent/TWI533451B/en
Publication of WO2014128839A1 publication Critical patent/WO2014128839A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a semiconductor device suitable for an insulated gate bipolar transistor having an insulated gate structure (hereinafter, abbreviated as IGBT) and the semiconductor device.
  • IGBT insulated gate bipolar transistor having an insulated gate structure
  • the present invention relates to a power conversion apparatus.
  • the IGBT is a switching element that controls the current flowing between the collector and the emitter by applying a voltage to the gate electrode.
  • IGBTs can control a wide range of power from tens of watts to hundreds of thousands of watts, and switching frequency ranges from tens of hertz to over a hundred kilohertz, so low-power devices such as air conditioners and high-power devices such as railways and steelworks Used up to. These power devices are strongly required to reduce the conduction loss and switching loss of the IGBT in order to increase the efficiency and miniaturization of the system.
  • the conduction loss is effective in reducing the voltage drop (ON voltage) at the time of ON, and can be reduced as the concentration of minority carriers accumulated in the drift layer increases. Further, the turn-off loss is smaller as the accumulated minority carrier concentration is lower, and there is a trade-off relationship between the on-voltage and the turn-off loss. In order to improve the trade-off, it is effective to enhance the IE (electron injection promotion) effect, but the characteristics of the IGBT are approaching the limit, and it is difficult to further improve the characteristics.
  • IE electron injection promotion
  • Patent Document 1 Japanese Patent Laid-Open No. 3-268363 discloses a four-terminal IGBT structure as shown in FIG.
  • the high-concentration p-type emitter layer 7 and the high-concentration n + layer 25 are adjacent to each other on the collector side, and individual electrodes are connected to the respective regions.
  • the high concentration n + layer 25 is operated during turn-off, minority carrier accumulation can be reduced and tail current can be reduced, so that turn-off loss can be reduced.
  • it since it operates as an IGBT when it is on and operates as a MOSFET with a fast switching speed when it is turned off, the trade-off between the on voltage and the turn-off loss can be improved.
  • the IGBT structure shown in FIG. 15 has a problem that the jumping voltage between the collector and the emitter is large because it operates as a MOSFET when it is off. Further, since there is no hole injection while the high-concentration n + layer 25 is operated, there is a problem that conduction loss immediately before turn-off increases.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in jumping voltage and improving a trade-off between on-voltage and turn-off loss, and power conversion using the same. Is to provide a device.
  • a semiconductor device includes a second conductivity type high-concentration emitter layer and a second conductivity type low-concentration emitter layer provided separately from each other in order to inject carriers into the semiconductor device. And a main electrode which is electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer, respectively.
  • the present invention since the amount of carriers accumulated in the semiconductor device can be controlled during the operation of the semiconductor device, it is possible to improve the trade-off between the on-voltage and the turn-off loss while suppressing an increase in jumping voltage. Further, when the semiconductor device according to the present invention is used for a power conversion device, the reliability of the power conversion device can be improved and the power loss can be reduced.
  • Embodiment 1 shows an IGBT according to a first embodiment of the present invention.
  • 3 is an example of a circuit using the IGBT according to the first embodiment.
  • the drive sequence of Embodiment 1 is shown.
  • the trade-off relationship between the on-voltage and the turn-off loss in the first embodiment is shown.
  • the IGBT which is Embodiment 2 of this invention is shown.
  • the IGBT which is Embodiment 3 of this invention is shown.
  • the IGBT which is a modification of Embodiment 3 is shown.
  • the IGBT which is Embodiment 4 of this invention is shown.
  • the IGBT which is a modification of Embodiment 4 is shown.
  • the IGBT which is Embodiment 5 of this invention is shown.
  • the IGBT which is Embodiment 6 of this invention is shown.
  • An IGBT which is a modification of the sixth embodiment is shown.
  • An IGBT according to a seventh embodiment of the present invention will be described.
  • the power converter device which is Embodiment 9 of this invention is shown.
  • the conventional IGBT currently disclosed by patent document 1 is shown.
  • 10 shows a diode according to an eighth embodiment of the present invention.
  • FIG. 1 shows a cross-sectional structure of the IGBT according to the first embodiment of the present invention.
  • n ⁇ substrate 1, p-type base layer 2 selectively formed on the surface of n ⁇ substrate 1, and n + -type formed on the surface of p-type base layer.
  • a gate electrode 6 is provided on the surface of the p-type base layer 2 sandwiched between the source layers 3 via a gate oxide film 5.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are disposed on the opposite surface of the n ⁇ substrate 1, and the n ⁇ layer 1 is interposed between them. By interposing a part, they are separated from each other as individual p-type conductivity type semiconductor layers. Separate electrodes 9 and 10 are electrically connected to the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8, respectively. That is, this IGBT is a four-terminal element.
  • FIG. 2 shows an example of a circuit using the IGBT of FIG. 1, in which the collector terminal c1 corresponds to a terminal connected to the p + type high concentration emitter layer 7 of FIG. 1, and the terminal c2 is a p ⁇ type low concentration emitter layer. 8 corresponds to the terminal connected to 8.
  • the collector terminal c2 of the IGBT 201 is connected to the output terminal 209 (C) via the MOSFET 202 serving as a switch, and the other collector terminal c1 is directly connected to the output terminal 209 (C).
  • the collector terminal c1 may be connected to the output terminal 209 (C) via a switching element different from the MOSFET 202, and the switching element is preferably an insulated gate type element such as MOSFET or IGBT. Further, instead of MOSFET 202, another insulated gate control type element such as IGBT may be used.
  • a voltage for example, 15V
  • a voltage for example, 0V
  • the collector terminal c1 and the emitter terminal 210 Current is passed between Accordingly, since minority carriers (holes) are highly injected from the p + -type high-concentration emitter layer 7 connected to the terminal c1 into the n ⁇ substrate 1, conductivity modulation is promoted and the on-voltage is reduced.
  • An ON signal is input to the terminal G2 from several ⁇ s before the terminal G1 (IGBT 201) is turned off, and a current flows mainly between the collector terminal c2 and the emitter terminal 210.
  • the collector terminals c1 and c2 are both connected to the output terminal 209 (C), but the p-type low-concentration emitter layer 8 having a lower impurity concentration has a lower built-in voltage. 8 (terminal c2) becomes easy to flow. For this reason, the minority carriers injected from the collector are reduced and the charge accumulated in the n ⁇ substrate 1 is reduced, so that the turn-off loss can be reduced. Further, since it operates as a low-injection IGBT when it is off, a tail current is generated, and an increase in jumping voltage between the collector and the emitter can be suppressed.
  • FIG. 3 shows a driving sequence of the gate electrode 6 (terminal G1) and the gate electrode 212 (terminal G2) of the MOSFET 202.
  • Period 1 is a period in which minority carriers are highly injected. A voltage at which the MOS transistor 204 is turned on is input to the terminal G1, and a voltage at which the MOSFET 202 is turned off is input to the terminal G2. During this period, minority carriers are injected at a high rate, so that the on-voltage is smaller than in other periods.
  • Period 2 is a period during which minority carriers are injected at a low rate, and an ON signal is input to the terminal G2 from 0.1 to 10 ⁇ s before the terminal G1 is turned off.
  • Period 3 is a period in which the IGBT 201 is turned off. First, a voltage at which the IGBT 201 is turned off is input to the terminal G1, and a voltage at which the MOSFET 202 is turned on is input to the terminal G2.
  • the terminal G2 receives an OFF signal during the period 3 in which the OFF signal is input to the terminal G1, and thereafter, only the terminal G1 is switched from OFF to ON, and the period 4 is shifted to.
  • Period 4 is the same as period 1, and thereafter, the sequence of periods 1 to 3 is repeated. In the present embodiment, such a drive sequence can improve the trade-off between the on-voltage and the turn-off loss.
  • FIG. 4 shows an example of the trade-off relationship between the on-voltage and the turn-off loss, and the jump-up voltage has the same magnitude.
  • the figure shows a comparative example corresponding to FIG. 15 and the first embodiment.
  • the turn-off loss of the present embodiment is reduced by 57% compared with the comparative example, and the characteristics are greatly improved.
  • the collector and emitter are formed by forming the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8 on the collector side and providing individual electrodes for each.
  • the trade-off between the on-voltage and the turn-off loss can be improved while suppressing an increase in jumping voltage.
  • FIG. 5 shows a cross-sectional structure of the IGBT according to the second embodiment of the present invention.
  • FIG. 6 shows a cross-sectional structure of the IGBT according to the third embodiment of the present invention.
  • n + with an impurity concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 is provided between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8.
  • Layer 13 is provided.
  • the operation of the parasitic pnp bipolar transistor composed of the p + -type high concentration emitter layer 7, the n ⁇ substrate 1 (or the n buffer layer 12), and the p ⁇ type low concentration emitter layer 8 is suppressed. it can.
  • the parasitic pnp transistor When the parasitic pnp transistor operates, it becomes difficult to control minority carrier injection by the external switching element 11 (switching between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8), and the on-voltage and turn-off loss Affects the trade-off.
  • the parasitic transistor operates when the external switching element 11 is turned on, since the minority carriers are highly injected from the p + -type high-concentration emitter layer 7, the amount of accumulated holes in the n ⁇ substrate 1 increases. Turn-off loss increases.
  • the entire region sandwiched between the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8 is the high concentration n + layer 13.
  • the structure in which a part of the region sandwiched between the p ⁇ -type low-concentration emitter layer 8 is the high-concentration n + layer 13 can also suppress the operation of the parasitic transistor.
  • the depth of the high concentration n + layer 13 may be shallower than that of the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8.
  • FIG. 8 shows a cross-sectional structure of an IGBT according to the fourth embodiment of the present invention.
  • an insulating layer 14 is provided between the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8.
  • the operation of the parasitic transistor can be suppressed as compared with the third embodiment.
  • the operation of the parasitic transistor is suppressed by providing the high-concentration n + layer 13, but in the fourth embodiment, the operation of the parasitic transistor is performed by using a part of the n layer of the parasitic pnp transistor as an insulating layer. Suppressed. In FIG.
  • the entire region sandwiched between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 is the insulating layer 14, but the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 7 A part of the region sandwiched between the emitter layers 8 may be an insulating layer 14, and the depth of the insulating layer 14 is shallower than that of the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8. May be. Further, as shown in FIG.
  • FIG. 10 shows a cross-sectional structure of an IGBT according to the fifth embodiment of the present invention.
  • the distance ln between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8 is longer than the hole diffusion distance Lp (ln> Lp).
  • the operation of the parasitic pnp bipolar transistor can be performed without providing a high concentration n + layer, an insulating layer, or the like between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8. Can be suppressed.
  • the hole diffusion distance Lp is obtained from the square root of the product of the hole diffusion coefficient Dp and lifetime ⁇ p, and the parasitic transistor operates when Lp is longer than the width ln of the base region.
  • the cause is that holes injected from the emitter region (for example, p ⁇ -type low-concentration emitter layer 8) are not recombined and extinguished in the base region (n buffer layer 12 or n ⁇ substrate 1) but diffused to the collector region (for example, p This is to reach the + type high concentration emitter layer 7). Therefore, recombination annihilation occurs before the holes reach the collector region due to Lp shortening or ln increase, so that the operation of the parasitic transistor can be suppressed.
  • the impurity concentration of the n layer (n-substrate 1 in FIG. 10) between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8 is 1 ⁇ 10 17 cm ⁇ 3 or less, ln is 5 ⁇ m. It is desirable to set it above.
  • the diffusion distance Lp can be shortened by shortening the lifetime ⁇ p, and can be controlled by introducing a lifetime killer on the collector side.
  • Lifetime killer that recombines holes uses heavy metals such as gold and platinum, or irradiation damage caused by radiation such as electron beams, etc., thereby suppressing the operation of parasitic transistors even if ln is shortened to about 1 ⁇ m. it can.
  • (Embodiment 6) 11 and 12 show a cross-sectional structure of an IGBT which is a sixth embodiment of the present invention and a modification thereof, respectively. In these IGBTs, an n + -type hole barrier layer 15 is provided between the p + -type high-concentration emitter layer 7 and the n buffer layer 12 (or n ⁇ substrate 1).
  • FIG. 13 shows a cross-sectional structure of an IGBT which is an embodiment of the present invention.
  • the IGBT according to the seventh embodiment includes an n ⁇ substrate 1, a p-type base layer 2 selectively formed on the surface of the n ⁇ substrate 1, and an n + -type source formed on the surface of the p-type base layer.
  • a gate electrode 6 provided on the surface of the p-type base layer 2 sandwiched between the layers 3 via a gate oxide film 5 is provided.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are formed on the opposite surfaces of the n ⁇ substrate 1 so as to be separated from each other as in the first embodiment.
  • the collector electrode 20 is connected to the p + -type high concentration emitter layer 7, and a second gate is formed on the surface of the n ⁇ substrate 1 sandwiched between the p ⁇ -type high concentration emitter layer 7 and the p-type low concentration emitter layer 8.
  • a second gate electrode 18 is formed through the oxide film 17.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are electrically connected by the p-type inversion layer 19 formed by inputting a negative voltage to the second gate electrode.
  • FIG. 16 shows a sectional structure of a diode according to the eighth embodiment of the present invention.
  • the cathode side n + layer 21 formed on the surface of the n ⁇ substrate 1, and the cathode electrode 22 are provided on the surface of the n + layer 21.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are separated from each other on the opposite surface of the n ⁇ substrate 1 by interposing the n ⁇ substrate 1 therebetween, and Separate electrodes are connected to the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8, respectively.
  • FIG. 14 shows an example of a power conversion device using the IGBT or the diode described in each embodiment described above.
  • a series circuit in which two IGBTs 107 are connected in series is connected between the DC terminals 101 and 102.
  • This series circuit is provided for the number of AC phases, and the series connection point of each series circuit is connected to the AC terminals 103, 104, and 105.
  • the number of AC phases is three, and three series circuits are provided.
  • a diode 108 is connected in antiparallel to each IGBT 107.
  • each IGBT 107 When each IGBT 107 is turned on / off by the gate drive circuit 106, the DC power received by the DC terminals 101, 102 is converted into AC power, and the AC power is output from the AC terminals 103, 104, 105.
  • the IGBT 107 the IGBTs of the first to seventh embodiments described above are used. Further, as the diode 108, the diode of Embodiment 8 may be used. Further, the IGBT 107 may be a conventional IGBT, and the diode of the eighth embodiment may be used as the diode 108.
  • the power loss of the power conversion device can be reduced by applying the IGBT or the diode described in each embodiment described above to the power conversion device.
  • the ninth embodiment is an inverter device
  • the IGBT and the diode according to the present invention can be applied to other power conversion devices such as a converter and a chopper, and the same effect can be obtained.
  • the gate shape on the emitter side is not limited to the planar type, but may be a trench type, and the gates may be arranged in a stripe shape or a mesh shape.
  • the above embodiment is a vertical IGBT and a vertical diode, it may be a horizontal IGBT and a horizontal diode.
  • the semiconductor material may be silicon or silicon carbide.
  • n-substrate 2 p-type base layer 3: n-type source layer 4: emitter electrode 5: oxide film 6: gate electrode 7: p-type high-concentration emitter layer 8: p-type low-concentration emitter layer 9: p-type high Collector electrode connected to the concentration emitter layer 10: Collector electrode connected to the p-type low concentration emitter layer 11: External switching element 12: Buffer layer 13: High concentration n + layer 14: Insulating layer 15: Hole barrier layer 16 : External MOSFET 17: Second gate oxide film 18: Second gate electrode 19: P-type inversion layer 20: Collector electrode 21: Cathode side n + layer 22: Cathode electrode 23: Anode electrode connected to high-concentration p-type emitter layer 24 : Anode electrode connected to low-concentration p-type emitter layer 25: High-concentration n + layer 101, 102: DC terminals 103, 104, 105: AC terminal 106: Gate drive circuit 107: IGBT 108

Abstract

A semiconductor device is provided with: p-type base layers (2) selectively formed on one main surface of an n-substrate (1); n-type source layers (3) formed on the surfaces of the p-type base layers; p-type high-concentration emitter layers (7) and p-type low-concentration emitter layers (8) provided separately from each other on another main surface of the n-substrate (1); an emitter electrode electrically connected to the p-type base layers (2) and the n-type source layers (3); gate electrodes (6) provided on the surfaces of the p-type base layers (2) so as to be sandwiched between the n-substrate (1) and the n-type source layers (3) across gate oxide films (5); and a collector electrode individually electrically connected to each of the p-type high-concentration emitter layers (7) and the p-type low-concentration emitter layers (8).

Description

半導体装置およびそれを用いた電力変換装置Semiconductor device and power conversion device using the same
　本発明は、半導体装置およびそれを用いた電力変換装置に係り、特に絶縁ゲート構造を有する絶縁ゲート型バイポーラトランジスタ（Insulated Gate Bipolar Transistor:以下、ＩＧＢＴと略する）に好適な半導体装置およびそれを用いた電力変換装置に関する。  The present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a semiconductor device suitable for an insulated gate bipolar transistor having an insulated gate structure (hereinafter, abbreviated as IGBT) and the semiconductor device. The present invention relates to a power conversion apparatus.
　ＩＧＢＴは、ゲート電極に電圧を印加することでコレクタ―エミッタ間に流れる電流を制御するスイッチング素子である。ＩＧＢＴが制御できる電力は数十ワットから数十万ワットと広範囲におよび、スイッチング周波数も数十ヘルツから百キロヘルツ超と幅広いため、エアーコンディショナー等の小電力機器から鉄道や製鉄所等の大電力機器まで使用される。これら電力機器では、システムの高効率化・小型化のため、ＩＧＢＴの導通損失とスイッチング損失の低減が強く求められる。 The IGBT is a switching element that controls the current flowing between the collector and the emitter by applying a voltage to the gate electrode. IGBTs can control a wide range of power from tens of watts to hundreds of thousands of watts, and switching frequency ranges from tens of hertz to over a hundred kilohertz, so low-power devices such as air conditioners and high-power devices such as railways and steelworks Used up to. These power devices are strongly required to reduce the conduction loss and switching loss of the IGBT in order to increase the efficiency and miniaturization of the system.
　導通損失はオン時の電圧降下(オン電圧)の低減が有効で、ドリフト層に蓄積される少数キャリア濃度が高いほど低減できる。また、ターンオフ損失は、蓄積される少数キャリア濃度が低いほど小さく、オン電圧とターンオフ損失との間にはトレードオフの関係が存在する。トレードオフを改善するためにはＩＥ（電子注入促進）効果を高めることが有効だが、ＩＧＢＴの特性は限界に近づきつつあり、更なる特性改善は難しい状況である。 The conduction loss is effective in reducing the voltage drop (ON voltage) at the time of ON, and can be reduced as the concentration of minority carriers accumulated in the drift layer increases. Further, the turn-off loss is smaller as the accumulated minority carrier concentration is lower, and there is a trade-off relationship between the on-voltage and the turn-off loss. In order to improve the trade-off, it is effective to enhance the IE (electron injection promotion) effect, but the characteristics of the IGBT are approaching the limit, and it is difficult to further improve the characteristics.
　特性を更に改善するため、特許文献１（特開平３－２６８３６３号公報）には図１５に示すような４端子のＩＧＢＴ構造が開示されている。本構造は、コレクタ側に高濃度ｐ形エミッタ層７と高濃度ｎ+層２５とが隣接しており、その各領域に個別の電極が接続される。このような構成とすることで、オン時は高濃度ｐ形エミッタ層７から少数キャリアが高注入されるため平均キャリア濃度を高くでき、オン電圧が低くできる。また、ターンオフ時は高濃度ｎ+層２５を動作させることで少数キャリアの蓄積を低減し、テール電流を小さくできるため、ターンオフ損失が低減できる。つまり、オン時はＩＧＢＴとして動作し、ターンオフ時はスイッチング速度の速いＭＯＳＦＥＴとして動作するため、オン電圧とターンオフ損失のトレードオフが改善できる。 In order to further improve the characteristics, Patent Document 1 (Japanese Patent Laid-Open No. 3-268363) discloses a four-terminal IGBT structure as shown in FIG. In this structure, the high-concentration p-type emitter layer 7 and the high-concentration n + layer 25 are adjacent to each other on the collector side, and individual electrodes are connected to the respective regions. With such a configuration, when on, minority carriers are highly injected from the high-concentration p-type emitter layer 7, so that the average carrier concentration can be increased and the on-voltage can be decreased. Further, since the high concentration n + layer 25 is operated during turn-off, minority carrier accumulation can be reduced and tail current can be reduced, so that turn-off loss can be reduced. In other words, since it operates as an IGBT when it is on and operates as a MOSFET with a fast switching speed when it is turned off, the trade-off between the on voltage and the turn-off loss can be improved.
特開平３－２６８３６３号公報JP-A-3-268363
　しかしながら、図１５に示すＩＧＢＴ構造においては、オフ時はＭＯＳＦＥＴとして動作するためコレクタ―エミッタ間の跳ね上り電圧が大きいという課題がある。また、高濃度ｎ+層２５を動作させている間は正孔注入がないため、ターンオフ直前の導通損失が増大するという課題もある。 However, the IGBT structure shown in FIG. 15 has a problem that the jumping voltage between the collector and the emitter is large because it operates as a MOSFET when it is off. Further, since there is no hole injection while the high-concentration n + layer 25 is operated, there is a problem that conduction loss immediately before turn-off increases.
　本発明は上述の点に鑑みなされたもので、その目的とするところは、跳ね上り電圧の増大を抑制すると共に、オン電圧とターンオフ損失のトレードオフを改善できる半導体装置およびそれを用いた電力変換装置を提供することである。 The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in jumping voltage and improving a trade-off between on-voltage and turn-off loss, and power conversion using the same. Is to provide a device.
　上記課題を解決するために、本発明による半導体装置は、半導体装置内にキャリアを注入するために、互いに分離されて設けられる第２導電形高濃度エミッタ層および第２導電形低濃度エミッタ層を備え、第２導電形高濃度エミッタ層と第２導電形低濃度エミッタ層に、それぞれ個別に電気的に接続される主電極を備える。 In order to solve the above problems, a semiconductor device according to the present invention includes a second conductivity type high-concentration emitter layer and a second conductivity type low-concentration emitter layer provided separately from each other in order to inject carriers into the semiconductor device. And a main electrode which is electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer, respectively.
　本発明によれば、半導体装置の動作中に、半導体装置内に蓄積されるキャリアの量を制御できるので、跳ね上り電圧増大を抑制しつつ、オン電圧とターンオフ損失のトレードオフを改善できる。また、本発明による半導体装置を電力変換装置に用いれば、電力変換装置の信頼性を向上できると共に、電力損失を低減できる。 According to the present invention, since the amount of carriers accumulated in the semiconductor device can be controlled during the operation of the semiconductor device, it is possible to improve the trade-off between the on-voltage and the turn-off loss while suppressing an increase in jumping voltage. Further, when the semiconductor device according to the present invention is used for a power conversion device, the reliability of the power conversion device can be improved and the power loss can be reduced.
本発明の実施の形態１であるＩＧＢＴを示す。1 shows an IGBT according to a first embodiment of the present invention. 実施の形態１のＩＧＢＴを用いた回路の一例である。3 is an example of a circuit using the IGBT according to the first embodiment. 実施の形態１の駆動シーケンスを示す。The drive sequence of Embodiment 1 is shown. 実施の形態１のオン電圧とターンオフ損失のトレードオフ関係を示す。The trade-off relationship between the on-voltage and the turn-off loss in the first embodiment is shown. 本発明の実施の形態２であるＩＧＢＴを示す。The IGBT which is Embodiment 2 of this invention is shown. 本発明の実施の形態３であるＩＧＢＴを示す。The IGBT which is Embodiment 3 of this invention is shown. 実施の形態３の変形例であるＩＧＢＴを示す。The IGBT which is a modification of Embodiment 3 is shown. 本発明の実施の形態４であるＩＧＢＴを示す。The IGBT which is Embodiment 4 of this invention is shown. 実施の形態４の変形例であるＩＧＢＴを示す。The IGBT which is a modification of Embodiment 4 is shown. 本発明の実施の形態５であるＩＧＢＴを示す。The IGBT which is Embodiment 5 of this invention is shown. 本発明の実施の形態６であるＩＧＢＴを示す。The IGBT which is Embodiment 6 of this invention is shown. 実施の形態６の変形例であるＩＧＢＴを示す。An IGBT which is a modification of the sixth embodiment is shown. 本発明の実施の形態７のＩＧＢＴを示す。An IGBT according to a seventh embodiment of the present invention will be described. 本発明の実施の形態９である電力変換装置を示す。The power converter device which is Embodiment 9 of this invention is shown. 特許文献１に開示されている従来のＩＧＢＴを示す。The conventional IGBT currently disclosed by patent document 1 is shown. 本発明の実施の形態８であるダイオードを示す。10 shows a diode according to an eighth embodiment of the present invention.
　以下、図示した実施例に基づき本発明の半導体装置を詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。なお、図中、ｐ-，ｐ，ｐ+という表記は、半導体層がｐ型であることを示し、かつこの順に不純物濃度が相対的に高いことを示す。また、ｎ-，ｎ，ｎ+という表記は、半導体層がｎ型であることを示し、かつこの順に不純物濃度が相対的に高いことを示す。
（実施の形態１）
　図１に、本発明の実施の形態１であるＩＧＢＴの断面構造を示す。 The semiconductor device of the present invention will be described in detail below based on the illustrated embodiments. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the figure, the notations p-, p, and p + indicate that the semiconductor layer is p-type and that the impurity concentration is relatively high in this order. The notations n−, n, n + indicate that the semiconductor layer is n-type, and that the impurity concentration is relatively high in this order.
(Embodiment 1)
FIG. 1 shows a cross-sectional structure of the IGBT according to the first embodiment of the present invention.
　本実施の形態１のＩＧＢＴにおいては、ｎ-基板１と、このｎ-基板１の表面に選択的に形成されたｐ形ベース層２と、ｐ形ベース層の表面に形成されたｎ+形ソース層３と、ｐ形ベース層２とｎ+形ソース層３に電気的に接続され、且つｎ+形ソース層３の表面に形成されたエミッタ電極４と、ｎ-基板１とｎ+形ソース層３とに挟まれたｐ形ベース層２の表面にゲート酸化膜５を介してゲート電極６とが設けられる。さらに本実施の形態１のＩＧＢＴにおいては、ｎ-基板１の反対側の表面にｐ+形高濃度エミッタ層７およびｐ-形低濃度エミッタ層８とが、これらの間にｎ-層１の一部が介在することにより、それぞれ個別のｐ形導電型の半導体層として互いに分離されている。且つｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とにはそれぞれ個別の電極９および１０が電気的に接続される。つまり、このＩＧＢＴは４端子素子となる。 In the IGBT according to the first embodiment, n − substrate 1, p-type base layer 2 selectively formed on the surface of n − substrate 1, and n + -type formed on the surface of p-type base layer. A source layer 3, an emitter electrode 4 electrically connected to the p-type base layer 2 and the n + -type source layer 3 and formed on the surface of the n + -type source layer 3, an n − substrate 1 and an n + -type A gate electrode 6 is provided on the surface of the p-type base layer 2 sandwiched between the source layers 3 via a gate oxide film 5. Further, in the IGBT of the first embodiment, the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are disposed on the opposite surface of the n − substrate 1, and the n − layer 1 is interposed between them. By interposing a part, they are separated from each other as individual p-type conductivity type semiconductor layers. Separate electrodes 9 and 10 are electrically connected to the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8, respectively. That is, this IGBT is a four-terminal element.
　図２は、図１のＩＧＢＴを用いた回路の一例で、コレクタ端子ｃ１が図１のｐ+形高濃度エミッタ層７に接続される端子に対応し、端子ｃ２がｐ-形低濃度エミッタ層８に接続される端子に対応する。この例では、ＩＧＢＴ２０１のコレクタ端子ｃ２はスイッチとして働くＭＯＳＦＥＴ２０２を介して出力端子２０９（Ｃ）に接続され、もう一方のコレクタ端子ｃ１は直接、出力端子２０９（Ｃ）に接続される。ただし、コレクタ端子ｃ１はＭＯＳＦＥＴ２０２とは異なるスイッチング素子を介して出力端子２０９（Ｃ）に接続されてもよく、スイッチング素子はＭＯＳＦＥＴやＩＧＢＴなどの絶縁ゲート型の素子とすることが望ましい。また、ＭＯＳＦＥＴ２０２に代えて、ＩＧＢＴなどの他の絶縁ゲート制御型の素子を用いてもよい。 FIG. 2 shows an example of a circuit using the IGBT of FIG. 1, in which the collector terminal c1 corresponds to a terminal connected to the p + type high concentration emitter layer 7 of FIG. 1, and the terminal c2 is a p− type low concentration emitter layer. 8 corresponds to the terminal connected to 8. In this example, the collector terminal c2 of the IGBT 201 is connected to the output terminal 209 (C) via the MOSFET 202 serving as a switch, and the other collector terminal c1 is directly connected to the output terminal 209 (C). However, the collector terminal c1 may be connected to the output terminal 209 (C) via a switching element different from the MOSFET 202, and the switching element is preferably an insulated gate type element such as MOSFET or IGBT. Further, instead of MOSFET 202, another insulated gate control type element such as IGBT may be used.
　ＩＧＢＴ２０１のオン時はゲート電極６（端子Ｇ１）に電圧（例えば１５Ｖ）を印加し、端子Ｇ２にはＭＯＳＦＥＴ２０２がオフとなる電圧（例えば０Ｖ）を入力することで、コレクタ端子ｃ１とエミッタ端子２１０との間に電流を流す。これにより、端子ｃ１に接続されたｐ+形高濃度エミッタ層７からｎ-基板１へ少数キャリア（ホール）が高注入されるため、伝導度変調が促進され、オン電圧が低減する。端子Ｇ１（ＩＧＢＴ２０１）をオフさせる数μｓ手前から端子Ｇ２にはオン信号を入力し、電流は主にコレクタ端子ｃ２とエミッタ端子２１０との間で流す。コレクタ端子ｃ１とｃ２は共に出力端子２０９（Ｃ）に接続されているが、不純物濃度が低いｐ形低濃度エミッタ層８の方がビルトイン電圧が低いため、電子電流はｐ-形低濃度エミッタ層８（端子ｃ２）の方へ流れ込み易くなる。このため、コレクタから注入される少数キャリアが少なくなり、ｎ-基板１に蓄積される電荷が低減するため、ターンオフ損失が低減できる。更に、オフ時は低注入のＩＧＢＴとして動作するため、テール電流が発生し、コレクタ－エミッタ間の跳ね上り電圧増大を抑制できる。 When the IGBT 201 is turned on, a voltage (for example, 15V) is applied to the gate electrode 6 (terminal G1), and a voltage (for example, 0V) at which the MOSFET 202 is turned off is input to the terminal G2, whereby the collector terminal c1 and the emitter terminal 210 Current is passed between Accordingly, since minority carriers (holes) are highly injected from the p + -type high-concentration emitter layer 7 connected to the terminal c1 into the n − substrate 1, conductivity modulation is promoted and the on-voltage is reduced. An ON signal is input to the terminal G2 from several μs before the terminal G1 (IGBT 201) is turned off, and a current flows mainly between the collector terminal c2 and the emitter terminal 210. The collector terminals c1 and c2 are both connected to the output terminal 209 (C), but the p-type low-concentration emitter layer 8 having a lower impurity concentration has a lower built-in voltage. 8 (terminal c2) becomes easy to flow. For this reason, the minority carriers injected from the collector are reduced and the charge accumulated in the n − substrate 1 is reduced, so that the turn-off loss can be reduced. Further, since it operates as a low-injection IGBT when it is off, a tail current is generated, and an increase in jumping voltage between the collector and the emitter can be suppressed.
　図３はゲート電極６（端子Ｇ１）とＭＯＳＦＥＴ２０２のゲート電極２１２（端子Ｇ２）の駆動シーケンスである。期間１は少数キャリアが高注入される期間で、端子Ｇ１にはＭＯＳトランジスタ２０４がオンする電圧が、端子Ｇ２にはＭＯＳＦＥＴ２０２がオフする電圧が入力される。この期間では少数キャリアが高注入されるため、オン電圧は他の期間と比較して小さい。期間２は少数キャリアが低注入される期間で、端子Ｇ１がオフする手前０．１～１０μｓから端子Ｇ２にオン信号が入力される。少数キャリアの注入が低いためｎ-基板に蓄積される電荷が低減し、端子Ｇ１がオンからオフへ切り替わる際の損失が低減する。ちなみに期間２はｎ-基板１に蓄積される少数キャリアが低減するためオン電圧が増大するが、端子Ｇ１とＧ２がオンする期間（デッドタイム）は短いため、全体の損失はほとんど増大しない。期間３はＩＧＢＴ２０１がオフする期間で、はじめ、端子Ｇ１にはＩＧＢＴ２０１がオフする電圧が、端子Ｇ２にはＭＯＳＦＥＴ２０２がオンする電圧が入力されている。端子Ｇ２は端子Ｇ１にオフ信号が入力されている期間３中にオフ信号が入力され、その後、端子Ｇ１のみがオフからオンへ切り替わり、期間４へと移行する。期間４は期間１と同じ期間で、以後、期間１から３のシーケンスが繰り返される。本実施形態においては、このような駆動シーケンスによりオン電圧とターンオフ損失のトレードオフが改善できる。 FIG. 3 shows a driving sequence of the gate electrode 6 (terminal G1) and the gate electrode 212 (terminal G2) of the MOSFET 202. Period 1 is a period in which minority carriers are highly injected. A voltage at which the MOS transistor 204 is turned on is input to the terminal G1, and a voltage at which the MOSFET 202 is turned off is input to the terminal G2. During this period, minority carriers are injected at a high rate, so that the on-voltage is smaller than in other periods. Period 2 is a period during which minority carriers are injected at a low rate, and an ON signal is input to the terminal G2 from 0.1 to 10 μs before the terminal G1 is turned off. Since the minority carrier injection is low, the charge accumulated in the n − substrate is reduced, and the loss when the terminal G1 is switched from on to off is reduced. Incidentally, in the period 2, the minority carriers accumulated in the n − substrate 1 are reduced, so that the on-voltage is increased. However, since the period during which the terminals G 1 and G 2 are turned on (dead time) is short, the overall loss hardly increases. Period 3 is a period in which the IGBT 201 is turned off. First, a voltage at which the IGBT 201 is turned off is input to the terminal G1, and a voltage at which the MOSFET 202 is turned on is input to the terminal G2. The terminal G2 receives an OFF signal during the period 3 in which the OFF signal is input to the terminal G1, and thereafter, only the terminal G1 is switched from OFF to ON, and the period 4 is shifted to. Period 4 is the same as period 1, and thereafter, the sequence of periods 1 to 3 is repeated. In the present embodiment, such a drive sequence can improve the trade-off between the on-voltage and the turn-off loss.
　図４はオン電圧とターンオフ損失のトレードオフ関係の一例を示し、跳ね上り電圧は同じ大きさとした。図には図１５に対応する比較例と、本実施の形態１を示している。同じオン電圧で比較した場合、本実施の形態のターンオフ損失は比較例と比較して５７％低減しており、特性が大幅に改善される。 FIG. 4 shows an example of the trade-off relationship between the on-voltage and the turn-off loss, and the jump-up voltage has the same magnitude. The figure shows a comparative example corresponding to FIG. 15 and the first embodiment. When compared with the same on-voltage, the turn-off loss of the present embodiment is reduced by 57% compared with the comparative example, and the characteristics are greatly improved.
　以上のように、本実施の形態のＩＧＢＴでは、コレクタ側にｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８を形成し、それぞれに個別の電極を設けることで、コレクタ－エミッタ間の跳ね上り電圧増大を抑制しつつ、オン電圧とターンオフ損失のトレードオフを改善することができる。
（実施の形態２）
　図５は、本発明の実施の形態２のＩＧＢＴの断面構造を示すものである。実施の形態２に示すＩＧＢＴにおいては、ｎ-基板１とｐ+形高濃度エミッタ層７との間、およびｎ-基板１とｐ-形低濃度エミッタ層８との間にｎ-基板１より不純物濃度が高く、ｐ+形高濃度エミッタ層７よりも不純物濃度が低いｎバッファ層１２を設けている。ｎバッファ層１２により、所望の耐圧を得るためのｎ-基板１の厚さを低減できるので、オン電圧と耐圧のトレードオフが改善できる。
（実施の形態３）
　図６は、本発明の実施の形態３のＩＧＢＴの断面構造を示すものである。実施の形態３に示すＩＧＢＴにおいては、ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との間に不純物濃度1×１０18～１×１０21ｃｍ-3の高濃度ｎ+層１３が設けられている。 As described above, in the IGBT according to the present embodiment, the collector and emitter are formed by forming the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8 on the collector side and providing individual electrodes for each. The trade-off between the on-voltage and the turn-off loss can be improved while suppressing an increase in jumping voltage.
(Embodiment 2)
FIG. 5 shows a cross-sectional structure of the IGBT according to the second embodiment of the present invention. In the IGBT shown in the second embodiment, the n-substrate 1 and the p + -type high-concentration emitter layer 7 and the n-substrate 1 and the p--type low-concentration emitter layer 8 are separated from the n-substrate 1. An n buffer layer 12 having a high impurity concentration and a lower impurity concentration than the p + -type high concentration emitter layer 7 is provided. Since the n buffer layer 12 can reduce the thickness of the n − substrate 1 for obtaining a desired breakdown voltage, the trade-off between the on-voltage and the breakdown voltage can be improved.
(Embodiment 3)
FIG. 6 shows a cross-sectional structure of the IGBT according to the third embodiment of the present invention. In the IGBT shown in the third embodiment, a high concentration n + with an impurity concentration of 1 × 10 18 to 1 × 10 21 cm −3 is provided between the p + type high concentration emitter layer 7 and the p − type low concentration emitter layer 8. Layer 13 is provided.
　このような構造にすることで、ｐ+形高濃度エミッタ層７とｎ-基板１（もしくはｎバッファ層１２）、ｐ-形低濃度エミッタ層８から構成される寄生ｐｎｐバイポーラトランジスタの動作を抑制できる。寄生ｐｎｐトランジスタが動作すると、外付けのスイッチング素子１１による少数キャリア注入の調節（ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との切り替え）が難しくなり、オン電圧とターンオフ損失のトレードオフに影響する。例えば、外付けスイッチング素子１１をオンさせた時に寄生トランジスタが動作すると、ｐ+形高濃度エミッタ層７から少数キャリアが高注入されるため、ｎ-基板１の正孔の蓄積量が増加し、ターンオフ損失が増大する。 With such a structure, the operation of the parasitic pnp bipolar transistor composed of the p + -type high concentration emitter layer 7, the n − substrate 1 (or the n buffer layer 12), and the p − type low concentration emitter layer 8 is suppressed. it can. When the parasitic pnp transistor operates, it becomes difficult to control minority carrier injection by the external switching element 11 (switching between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8), and the on-voltage and turn-off loss Affects the trade-off. For example, when the parasitic transistor operates when the external switching element 11 is turned on, since the minority carriers are highly injected from the p + -type high-concentration emitter layer 7, the amount of accumulated holes in the n − substrate 1 increases. Turn-off loss increases.
　図６の実施形態ではｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とに挟まれた全ての領域を高濃度ｎ+層１３としているが、ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とに挟まれた一部の領域を高濃度ｎ+層１３とする構造でも寄生トランジスタの動作を抑制できる。また、高濃度ｎ+層１３の深さはｐ+形高濃度エミッタ層７およびｐ-形低濃度エミッタ層８より浅くした構造でもよい。ただし、図７に示すように、高濃度ｎ+層１３をｐ形高濃度エミッタ層７およびｐ形低濃度エミッタ層８よりも深くすると、寄生ｐｎｐバイポーラトランジスタの動作を更に抑制できる。
（実施の形態４）
　図８は、本発明の実施の形態４であるＩＧＢＴの断面構造を示す。実施の形態４に示すＩＧＢＴにおいては、ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との間に絶縁層１４が設けられている。 In the embodiment of FIG. 6, the entire region sandwiched between the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8 is the high concentration n + layer 13. And the structure in which a part of the region sandwiched between the p − -type low-concentration emitter layer 8 is the high-concentration n + layer 13 can also suppress the operation of the parasitic transistor. The depth of the high concentration n + layer 13 may be shallower than that of the p + type high concentration emitter layer 7 and the p − type low concentration emitter layer 8. However, if the high-concentration n + layer 13 is deeper than the p-type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 as shown in FIG. 7, the operation of the parasitic pnp bipolar transistor can be further suppressed.
(Embodiment 4)
FIG. 8 shows a cross-sectional structure of an IGBT according to the fourth embodiment of the present invention. In the IGBT shown in the fourth embodiment, an insulating layer 14 is provided between the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8.
　このような構造にすることで、実施の形態３よりも寄生トランジスタの動作を抑制できる。実施の形態２では高濃度ｎ+層１３を設けることで寄生トランジスタの動作を抑制したが、実施の形態４では寄生ｐｎｐトランジスタのｎ層の一部を絶縁層とすることで寄生トランジスタの動作を抑制している。図８ではｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とに挟まれた全ての領域を絶縁層１４としているが、ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とに挟まれた一部の領域を絶縁層１４とする構造でもよく、また、絶縁層１４の深さはｐ+形高濃度エミッタ層７およびｐ-形低濃度エミッタ層８より浅くてもよい。また、図９に示すように、絶縁層１４をｐ+形高濃度エミッタ層７およびｐ-形低濃度エミッタ層８よりも深くすると、寄生ｐｎｐバイポーラトランジスタの動作を更に抑制できる。
（実施の形態５）
　図１０は、本発明の実施の形態５であるＩＧＢＴの断面構造を示すものである。実施の形態５に示すＩＧＢＴにおいては、ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との間の距離ｌｎが正孔の拡散距離Ｌｐより長い（ｌｎ＞Ｌｐ）。 With such a structure, the operation of the parasitic transistor can be suppressed as compared with the third embodiment. In the second embodiment, the operation of the parasitic transistor is suppressed by providing the high-concentration n + layer 13, but in the fourth embodiment, the operation of the parasitic transistor is performed by using a part of the n layer of the parasitic pnp transistor as an insulating layer. Suppressed. In FIG. 8, the entire region sandwiched between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 is the insulating layer 14, but the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 7 A part of the region sandwiched between the emitter layers 8 may be an insulating layer 14, and the depth of the insulating layer 14 is shallower than that of the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8. May be. Further, as shown in FIG. 9, when the insulating layer 14 is deeper than the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8, the operation of the parasitic pnp bipolar transistor can be further suppressed.
(Embodiment 5)
FIG. 10 shows a cross-sectional structure of an IGBT according to the fifth embodiment of the present invention. In the IGBT shown in the fifth embodiment, the distance ln between the p + type high concentration emitter layer 7 and the p − type low concentration emitter layer 8 is longer than the hole diffusion distance Lp (ln> Lp).
　このような構造にすることにより、高濃度ｎ+層や絶縁層などをｐ+型高濃度エミッタ層７とｐ-型低濃度エミッタ層８との間に設けることなく寄生ｐｎｐバイポーラトランジスタの動作を抑制できる。正孔の拡散距離Ｌｐは正孔の拡散係数Ｄｐとライフタイムτｐの積の平方根より求められ、Ｌｐがベース領域の幅ｌｎより長い場合に寄生トランジスタが動作する。原因はエミッタ領域（例えばｐ-形低濃度エミッタ層８）から注入される正孔が、ベース領域（ｎバッファ層１２もしくはｎ-基板１）で再結合消滅されずに拡散によりコレクタ領域（例えばｐ+形高濃度エミッタ層７）へ到達するためである。したがって、Ｌｐ短縮又はｌｎ増大により、正孔がコレクタ領域に到達する前に再結合消滅するので、寄生トランジスタの動作を抑制できる。ｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との間のｎ層（図１０ではｎ-基板１）の不純物濃度が１×１０17ｃｍ-3以下の場合、ｌｎは５μｍ以上とすることが望ましい。 With such a structure, the operation of the parasitic pnp bipolar transistor can be performed without providing a high concentration n + layer, an insulating layer, or the like between the p + type high concentration emitter layer 7 and the p − type low concentration emitter layer 8. Can be suppressed. The hole diffusion distance Lp is obtained from the square root of the product of the hole diffusion coefficient Dp and lifetime τp, and the parasitic transistor operates when Lp is longer than the width ln of the base region. The cause is that holes injected from the emitter region (for example, p − -type low-concentration emitter layer 8) are not recombined and extinguished in the base region (n buffer layer 12 or n − substrate 1) but diffused to the collector region (for example, p This is to reach the + type high concentration emitter layer 7). Therefore, recombination annihilation occurs before the holes reach the collector region due to Lp shortening or ln increase, so that the operation of the parasitic transistor can be suppressed. When the impurity concentration of the n layer (n-substrate 1 in FIG. 10) between the p + type high concentration emitter layer 7 and the p− type low concentration emitter layer 8 is 1 × 10 17 cm −3 or less, ln is 5 μm. It is desirable to set it above.
　拡散距離Ｌｐはライフタイムτｐを短くすることで短縮でき、ライフタイムキラーをコレクタ側に導入することで制御できる。正孔を再結合させるライフタイムキラーには金や白金などの重金属、あるいは電子線等の放射線による照射損傷などが用いられ、これにより、ｌｎは１μｍ程度まで短くしても寄生トランジスタの動作を抑制できる。
（実施の形態６）
　図１１、１２は、それぞれ本発明の実施の形態６およびその変形例であるＩＧＢＴの断面構造を示す。これらＩＧＢＴにおいては、ｐ+形高濃度エミッタ層７とｎバッファ層１２（もしくはｎ-基板１）との間にｎ+形のホールバリア層１５が設けられる。 The diffusion distance Lp can be shortened by shortening the lifetime τp, and can be controlled by introducing a lifetime killer on the collector side. Lifetime killer that recombines holes uses heavy metals such as gold and platinum, or irradiation damage caused by radiation such as electron beams, etc., thereby suppressing the operation of parasitic transistors even if ln is shortened to about 1 μm. it can.
(Embodiment 6)
11 and 12 show a cross-sectional structure of an IGBT which is a sixth embodiment of the present invention and a modification thereof, respectively. In these IGBTs, an n + -type hole barrier layer 15 is provided between the p + -type high-concentration emitter layer 7 and the n buffer layer 12 (or n − substrate 1).
　このような構造にすることにより、ｐ-形低濃度エミッタ層８からｐ+形高濃度エミッタ層７へ流れる正孔電流を抑制でき、寄生ｐｎｐバイポーラトランジスタの動作を抑制できる。
（実施の形態７）
　図１３は、本発明の実施の形態であるＩＧＢＴの断面構造を示す。 With such a structure, the hole current flowing from the p − type low concentration emitter layer 8 to the p + type high concentration emitter layer 7 can be suppressed, and the operation of the parasitic pnp bipolar transistor can be suppressed.
(Embodiment 7)
FIG. 13 shows a cross-sectional structure of an IGBT which is an embodiment of the present invention.
　本実施の形態７のＩＧＢＴは、ｎ-基板１と、このｎ-基板１の表面に選択的に形成されたｐ形ベース層２と、ｐ形ベース層の表面に形成されたｎ+形ソース層３と、ｐ形ベース層２とｎ+形ソース層３に電気的に接続され、且つｎ+形ソース層３の表面に形成されたエミッタ電極４と、ｎ-基板１とｎ+形ソース層３とに挟まれたｐ形ベース層２の表面にゲート酸化膜５を介して設けられたゲート電極６とを備える。さらに、本実施形態では、ｎ-基板１の逆の表面にｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とが、実施の形態１と同様に互いに分離した状態で形成され、ｐ+形高濃度エミッタ層７にはコレクタ電極２０が接続され、ｐ-形高濃度エミッタ層７とｐ形低濃度エミッタ層８とに挟まれたｎ-基板１の表面に第２のゲート酸化膜１７を介して第２ゲート電極１８が形成される。この第２ゲート電極に負電圧を入力することで形成されるｐ形反転層１９によりｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とが電気的に接続される。 The IGBT according to the seventh embodiment includes an n − substrate 1, a p-type base layer 2 selectively formed on the surface of the n − substrate 1, and an n + -type source formed on the surface of the p-type base layer. Layer 3, emitter electrode 4 electrically connected to p-type base layer 2 and n + -type source layer 3 and formed on the surface of n + -type source layer 3, n − substrate 1 and n + -type source A gate electrode 6 provided on the surface of the p-type base layer 2 sandwiched between the layers 3 via a gate oxide film 5 is provided. Further, in this embodiment, the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are formed on the opposite surfaces of the n − substrate 1 so as to be separated from each other as in the first embodiment. The collector electrode 20 is connected to the p + -type high concentration emitter layer 7, and a second gate is formed on the surface of the n − substrate 1 sandwiched between the p − -type high concentration emitter layer 7 and the p-type low concentration emitter layer 8. A second gate electrode 18 is formed through the oxide film 17. The p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are electrically connected by the p-type inversion layer 19 formed by inputting a negative voltage to the second gate electrode.
　このような構造にすることにより、外部スイッチング素子を設けた場合と同様に、オン電圧とターンオフ損失のトレードオフを改善できる。図１３ではｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８との間の領域をｎ-基板１としているが、ｎ-基板より不純物濃度が高いｎ形ウェル層（図示せず）を挿入する構造にしてもよい。
（実施の形態８）
　図１６は、本発明の実施の形態８であるダイオードの断面構造を示す。 With such a structure, the trade-off between the on-voltage and the turn-off loss can be improved as in the case where the external switching element is provided. In FIG. 13, the region between the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8 is the n − substrate 1. ) May be inserted.
(Embodiment 8)
FIG. 16 shows a sectional structure of a diode according to the eighth embodiment of the present invention.
　本実施の形態８のダイオードにおいては、ｎ-基板１と、このｎ-基板１の表面に形成されたカソード側ｎ+層２１と、ｎ+層２１の表面にカソード電極２２を設けた構造において、ｎ-基板１の反対側の表面にｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とが、これらの間にｎ-基板１が介在することにより、互いに分離され、且つｐ+形高濃度エミッタ層７とｐ-形低濃度エミッタ層８とにはそれぞれ個別の電極が接続される。 In the diode of the eighth embodiment, in the structure in which the n − substrate 1, the cathode side n + layer 21 formed on the surface of the n − substrate 1, and the cathode electrode 22 are provided on the surface of the n + layer 21. The p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are separated from each other on the opposite surface of the n − substrate 1 by interposing the n − substrate 1 therebetween, and Separate electrodes are connected to the p + -type high concentration emitter layer 7 and the p − -type low concentration emitter layer 8, respectively.
　このような構造にすることにより、ｎ-基板１に蓄積される少数キャリアの量を調節できるため、順方向の電圧降下とリカバリ損失のトレードオフが改善できる。
（実施の形態９）
　図１４は、上述した各実施の形態で説明したＩＧＢＴまたはダイオードを用いた電力変換装置の一例を示す。 By adopting such a structure, the amount of minority carriers accumulated in the n − substrate 1 can be adjusted, so that the trade-off between forward voltage drop and recovery loss can be improved.
(Embodiment 9)
FIG. 14 shows an example of a power conversion device using the IGBT or the diode described in each embodiment described above.
　図１４の実施の形態９はインバータである。２個のＩＧＢＴ１０７が直列に接続された直列回路が直流端子１０１と１０２の間に接続される。この直列回路は交流の相数分備えられ、各直列回路の直列接続点は交流端子１０３，１０４，１０５に接続される。本実施携帯においては、交流の相数は３相であり、３個の直列回路を備える。また、各ＩＧＢＴ１０７にはダイオード１０８が逆並列に接続される。 14 is an inverter. A series circuit in which two IGBTs 107 are connected in series is connected between the DC terminals 101 and 102. This series circuit is provided for the number of AC phases, and the series connection point of each series circuit is connected to the AC terminals 103, 104, and 105. In this embodiment, the number of AC phases is three, and three series circuits are provided. A diode 108 is connected in antiparallel to each IGBT 107.
　各ＩＧＢＴ１０７がゲート駆動回路１０６によってオン・オフ駆動されることにより、直流端子１０１，１０２に受電する直流電力が交流電力に変換され、交流電力が交流端子１０３，１０４，１０５から出力される。 When each IGBT 107 is turned on / off by the gate drive circuit 106, the DC power received by the DC terminals 101, 102 is converted into AC power, and the AC power is output from the AC terminals 103, 104, 105.
　ＩＧＢＴ１０７としては、上述した本実施の形態１から７のＩＧＢＴが用いられる。また、ダイオード１０８として、実施の形態８のダイオードを用いてもよい。さらに、ＩＧＢＴ１０７を従来のＩＧＢＴとし、ダイオード１０８として、実施の形態８のダイオードを用いてもよい。 As the IGBT 107, the IGBTs of the first to seventh embodiments described above are used. Further, as the diode 108, the diode of Embodiment 8 may be used. Further, the IGBT 107 may be a conventional IGBT, and the diode of the eighth embodiment may be used as the diode 108.
　上述した各実施の形態で説明したＩＧＢＴまたはダイオードを電力変換装置に適用することで、電力変換装置の電力損失を低減することができる。 The power loss of the power conversion device can be reduced by applying the IGBT or the diode described in each embodiment described above to the power conversion device.
　尚、本実施の形態９はインバータ装置であるが、コンバータやチョッパ等のその他の電力変換装置についても本発明によるＩＧＢＴおよびダイオードを適用でき、同様の効果が得られる。 Although the ninth embodiment is an inverter device, the IGBT and the diode according to the present invention can be applied to other power conversion devices such as a converter and a chopper, and the same effect can be obtained.
　本発明の実施の形態は前記の実施の形態に限定されるものではなく、本発明の技術的思想の範囲内で、で種々変更可能であることはいうまでもない。 It goes without saying that the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made within the scope of the technical idea of the present invention.
　例えば、エミッタ側のゲート形状は、プレーナ型に限らず、トレンチ型としてもよく、そのゲートはストライプ状やメッシュ状に配置してもよい。 For example, the gate shape on the emitter side is not limited to the planar type, but may be a trench type, and the gates may be arranged in a stripe shape or a mesh shape.
　また、前記実施の形態は、縦型ＩＧＢＴと縦型ダイオードであるが、横型ＩＧＢＴ及び横型ダイオードとしてもよい。また、半導体材料は、シリコンでもシリコンカーバイドでもよい。 Further, although the above embodiment is a vertical IGBT and a vertical diode, it may be a horizontal IGBT and a horizontal diode. The semiconductor material may be silicon or silicon carbide.
　　１：ｎ-基板
　　２：ｐ形ベース層
　　３：ｎ形ソース層
　　４：エミッタ電極
　　５：酸化膜
　　６：ゲート電極
　　７：ｐ形高濃度エミッタ層
　　８：ｐ形低濃度エミッタ層
　　９：ｐ形高濃度エミッタ層に接続されるコレクタ電極
　１０：ｐ形低濃度エミッタ層に接続されるコレクタ電極
　１１：外付けスイッチング素子
　１２：バッファ層
　１３：高濃度ｎ+層
　１４：絶縁層
　１５：ホールバリア層
　１６：外付けＭＯＳＦＥＴ
　１７：第２のゲート酸化膜
　１８：第２ゲート電極
　１９：ｐ形反転層
　２０：コレクタ電極
　２１：カソード側ｎ+層
　２２：カソード電極
　２３：高濃度ｐ形エミッタ層に接続されるアノード電極
　２４：低濃度ｐ形エミッタ層に接続されるアノード電極
　２５：高濃度ｎ+層
１０１、１０２：直流端子
１０３、１０４、１０５：交流端子
１０６：ゲート駆動回路
１０７：ＩＧＢＴ
１０８：ダイオード
２０１：ＩＧＢＴ
２０２：外付けＭＯＳＦＥＴ
２０３：ドライバーＩＣ
２０４：エミッタ側に内蔵されるＭＯＳトランジスタ
２０５：ドリフト抵抗
２０６、２０７：コレクタに内蔵されるｐｎダイオード
２０８：電源端子
２０９：出力端子
２１０：エミッタ端子
２１１：ゲート電極
２１２：ゲート電極 1: n-substrate 2: p-type base layer 3: n-type source layer 4: emitter electrode 5: oxide film 6: gate electrode 7: p-type high-concentration emitter layer 8: p-type low-concentration emitter layer 9: p-type high Collector electrode connected to the concentration emitter layer 10: Collector electrode connected to the p-type low concentration emitter layer 11: External switching element 12: Buffer layer 13: High concentration n + layer 14: Insulating layer 15: Hole barrier layer 16 : External MOSFET
17: Second gate oxide film 18: Second gate electrode 19: P-type inversion layer 20: Collector electrode 21: Cathode side n + layer 22: Cathode electrode 23: Anode electrode connected to high-concentration p-type emitter layer 24 : Anode electrode connected to low-concentration p-type emitter layer 25: High-concentration n + layer 101, 102: DC terminals 103, 104, 105: AC terminal 106: Gate drive circuit 107: IGBT
108: Diode 201: IGBT
202: External MOSFET
203: Driver IC
204: MOS transistor 205 built in the emitter side: Drift resistor 206, 207: Pn diode 208 built in the collector: Power supply terminal 209: Output terminal 210: Emitter terminal 211: Gate electrode 212: Gate electrode

Claims (15)

  1. 　第１導電形半導体基板の第１の主表面に選択的に形成された第２導電形ベース層と、
    　前記第２導電形ベース層の表面に形成された第１導電形ソース層と、
    　前記第１導電形半導体基板の第２の主表面に、互いに分離されて設けられる第２導電形高濃度エミッタ層および第２導電形低濃度エミッタ層と、
    　前記第２導電形ベース層および前記第１導電形ソース層に電気的に接続される第１の主電極と、
    　前記第１導電形半導体基板と前記第１導電形ソース層とに挟まれた前記第２導電形ベース層の表面にゲート酸化膜を介して設けられるゲート電極と、
    を備え、
    　前記第２導電形高濃度エミッタ層と前記第２導電形低濃度エミッタ層に、それぞれ個別に電気的に接続される複数の第２の主電極とを備えることを特徴とする半導体装置。     A second conductivity type base layer selectively formed on the first main surface of the first conductivity type semiconductor substrate;
    A first conductivity type source layer formed on a surface of the second conductivity type base layer;
    A second conductivity type high-concentration emitter layer and a second conductivity type low-concentration emitter layer provided separately from each other on the second main surface of the first conductivity type semiconductor substrate;
    A first main electrode electrically connected to the second conductivity type base layer and the first conductivity type source layer;
    A gate electrode provided on a surface of the second conductivity type base layer sandwiched between the first conductivity type semiconductor substrate and the first conductivity type source layer via a gate oxide film;
    With
    A semiconductor device comprising: a plurality of second main electrodes individually electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer.
  2. 　請求項１に記載される半導体装置において、前記第２導電形低濃度エミッタ層はスイッチング手段を介して前記第２導電形高濃度エミッタ層に電気的に接続されることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the second conductivity type low concentration emitter layer is electrically connected to the second conductivity type high concentration emitter layer through a switching means.
  3. 　請求項１または請求項２に記載される半導体装置において、前記第１導電形半導体基板は、前記第２導電形高濃度エミッタ層および前記第２導電形低濃度エミッタ層と接する領域に第１導電形バッファ層を備えることを特徴とする半導体装置。 3. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor substrate has first conductivity in a region in contact with the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer. A semiconductor device comprising a buffer layer.
  4. 　請求項１から３のいずれか１項に記載される半導体装置において、　前記第２導電形高濃度エミッタ層と前記第２導電形エミッタ低濃度エミッタ層との間に第１導電形高濃度層を備えることを特徴とする半導体装置。 4. The semiconductor device according to claim 1, wherein a first conductivity type high concentration layer is provided between the second conductivity type high concentration emitter layer and the second conductivity type emitter low concentration emitter layer. 5. A semiconductor device comprising:
  5. 　請求項４に記載される半導体装置において、前記第１導電形高濃度層の前記第２の主表面からの深さが前記第２導電形高濃度エミッタ層および前記第２導電形エミッタ層より深いことを特徴とする半導体装置。 5. The semiconductor device according to claim 4, wherein a depth of the first conductivity type high concentration layer from the second main surface is deeper than that of the second conductivity type high concentration emitter layer and the second conductivity type emitter layer. A semiconductor device.
  6. 　請求項１から３のいずれか１項に記載される半導体装置において、前記第２導電形高濃度エミッタ層と前記第２導電形エミッタ層との間に絶縁を備えることを特徴とする半導体装置。 4. The semiconductor device according to claim 1, further comprising an insulation between the second conductivity type high-concentration emitter layer and the second conductivity type emitter layer.
  7. 　請求項６に記載される半導体装置において、前記絶縁層の前記第２の主表面からの深さが前記第２導電形高濃度エミッタ層および前記第２導電形エミッタ層より深いことを特徴とする半導体装置。 7. The semiconductor device according to claim 6, wherein a depth of the insulating layer from the second main surface is deeper than that of the second conductivity type high-concentration emitter layer and the second conductivity type emitter layer. Semiconductor device.
  8. 　請求項１または請求項２に記載の半導体装置において、前記第２導電形高濃度エミッタ層と前記第２導電形低濃度エミッタ層との間の距離が、前記第１導電形半導体基板における少数キャリアの拡散距離より長いことを特徴とする半導体装置。 3. The semiconductor device according to claim 1, wherein a distance between the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer is a minority carrier in the first conductivity type semiconductor substrate. A semiconductor device characterized in that it is longer than the diffusion distance.
  9. 　請求項１から請求項８のいずれか１項に記載の半導体装置において、前記第２導電形高濃度エミッタ層と前記第１導電形半導体基板との間に、前記第１導電形半導体基板より不純物濃度が高い第１導電形ホールバリア層を備えることを特徴とする半導体装置。 9. The semiconductor device according to claim 1, wherein an impurity is introduced between the second conductivity type high-concentration emitter layer and the first conductivity type semiconductor substrate from the first conductivity type semiconductor substrate. A semiconductor device comprising a first conductivity type hole barrier layer having a high concentration.
  10. 　請求項２に記載の半導体装置において、前記スイッチング手段が絶縁ゲートであることを特徴とする半導体装置。 3. The semiconductor device according to claim 2, wherein the switching means is an insulated gate.
  11. 　請求項２に記載の半導体装置において、前記スイッチング手段がＭＯＳＦＥＴ(Metal-Oxide-Semiconductor Field-Effect Transistor)であることを特徴とする半導体装置。 3. The semiconductor device according to claim 2, wherein the switching means is a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor).
  12. 　請求項２に記載の半導体装置において、前記スイッチング手段は、前記ゲート電極に与えられる信号がオンからオフへ切り替わる前に、オフからオンへ切り替わり、且つ前記ゲート電極の信号がオフしている間に前記スイッチング手段はオンからオフへ切り替わることを特徴とする半導体装置。 3. The semiconductor device according to claim 2, wherein the switching means switches from off to on before the signal applied to the gate electrode switches from on to off and the signal of the gate electrode is off. The semiconductor device according to claim 1, wherein the switching means is switched from on to off.
  13. 　第１導電形半導体基板の第１の主表面に形成された第１導電形高濃度カソード側層と、
    　前記第１導電形半導体基板の第２の主表面に、互いに分離されて設けられる第２導電形高濃度エミッタ層および第２導電形低濃度エミッタ層と、
    　前記第１導電形高濃度カソード側層に電気的に接続される第１の主電極と、
    　前記第２導電形高濃度エミッタ層と前記第２導電形低濃度エミッタ層に、それぞれ個別に電気的に接続される複数の第２の主電極と、
    　前記第２導電形低濃度エミッタ層と前記第２導電形高濃度エミッタ層とを電気的に接続するためのスイッチング手段と、
    を有するダイオードを備えることを特徴とする半導体装置。     A first conductivity type high concentration cathode side layer formed on the first main surface of the first conductivity type semiconductor substrate;
    A second conductivity type high-concentration emitter layer and a second conductivity type low-concentration emitter layer provided separately from each other on the second main surface of the first conductivity type semiconductor substrate;
    A first main electrode electrically connected to the first conductivity type high concentration cathode side layer;
    A plurality of second main electrodes respectively electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer;
    Switching means for electrically connecting the second conductivity type low-concentration emitter layer and the second conductivity type high-concentration emitter layer;
    A semiconductor device comprising a diode having
  14. 　一対の直流端子と、該入力端子間に接続され、複数の半導体スイッチング素子が直列接続される複数の直列接続回路と、該複数の直列接続回路の各直列接続点に接続される複数の交流端子とを備え、前記複数の半導体スイッチング素子がオン・オフすることにより電力変換を行う電力変換装置において、
    　前記複数の半導体スイッチング素子の各々が、請求項１乃至１２のいずれかに記載の半導体装置であることを特徴とする電力変換装置。     A pair of DC terminals, a plurality of series connection circuits connected between the input terminals and a plurality of semiconductor switching elements connected in series, and a plurality of AC terminals connected to each series connection point of the plurality of series connection circuits In a power conversion device that performs power conversion by turning on and off the plurality of semiconductor switching elements,
    Each of these semiconductor switching elements is the semiconductor device in any one of Claims 1 thru | or 12, The power converter device characterized by the above-mentioned.
  15. 　一対の直流端子と、該入力端子間に接続され、複数の半導体スイッチング素子が直列接続される複数の直列接続回路と、前記複数の半導体スイッチング素子の各々に逆並列に接続される複数のダイオードと、該複数の直列接続回路の各直列接続点に接続される複数の交流端子とを備え、前記複数の半導体スイッチング素子がオン・オフすることにより電力変換を行う電力変換装置において、
    　前記複数のダイオードの各々が、請求項１３に記載の半導体装置であることを特徴とする電力変換装置。     A pair of DC terminals, a plurality of series connection circuits connected between the input terminals, and a plurality of semiconductor switching elements connected in series; a plurality of diodes connected in antiparallel to each of the plurality of semiconductor switching elements; A plurality of AC terminals connected to each series connection point of the plurality of series connection circuits, and a power conversion device that performs power conversion by turning on and off the plurality of semiconductor switching elements,
    Each of the plurality of diodes is the semiconductor device according to claim 13.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111448668A (en) * 2017-12-18 2020-07-24 株式会社日立制作所 Power semiconductor device, module and manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268363A (en) * 1990-03-16 1991-11-29 Fuji Electric Co Ltd Insulated-gate bipolar transistor
JPH0661495A (en) * 1992-08-07 1994-03-04 Hitachi Ltd Semiconductor device and its manufacture
JP2006332199A (en) * 2005-05-24 2006-12-07 Shindengen Electric Mfg Co Ltd SiC SEMICONDUCTOR DEVICE

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268363A (en) * 1990-03-16 1991-11-29 Fuji Electric Co Ltd Insulated-gate bipolar transistor
JPH0661495A (en) * 1992-08-07 1994-03-04 Hitachi Ltd Semiconductor device and its manufacture
JP2006332199A (en) * 2005-05-24 2006-12-07 Shindengen Electric Mfg Co Ltd SiC SEMICONDUCTOR DEVICE

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111448668A (en) * 2017-12-18 2020-07-24 株式会社日立制作所 Power semiconductor device, module and manufacturing method
CN111448668B (en) * 2017-12-18 2023-09-01 株式会社日立制作所 Power semiconductor device, module, and method of manufacturing the same

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