JP2016012582A - Semiconductor device and power conversion equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve controllability of dv/dt by a gate drive circuit during a turn-on switching period while keeping low loss, high breakdown voltage and high breakdown resistance.SOLUTION: A semiconductor device of the present invention comprises: gate electrodes of a side wall structure on side walls of a wide trench gate; and a polysilicon electrode for breakdown voltage holding which are provided between the gate electrodes; and p layers each provided in a silicon layer between the gate electrode and the polysilicon electrode.

Description

  The present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) having a trench insulated gate structure and flowing a current in a vertical direction. ) And a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a semiconductor device suitable for low loss, improved controllability, and high breakdown resistance, and a power converter using the same.

  Conventionally, in IGBTs, as a technique for suppressing the overcurrent flowing at the time of a short circuit and improving the breakdown tolerance of the element, the arrangement pitch of the trench gates is changed, and a channel layer is not formed at a location where the distance between the trench gates is wide. Some have a floating p layer (see, for example, Patent Document 1).

  Conventionally, in the IGBT, as a technique for reducing the displacement current flowing from the floating p layer to the gate electrode and suppressing the rise of the gate potential, thereby improving the controllability of dv / dt, the floating p layer, the emitter electrode, There is a configuration in which is electrically connected through a resistor (for example, see Patent Document 2).

  Conventionally, in the IGBT, as a technique for improving the controllability of dv / dt by eliminating the potential fluctuation of the gate due to the influence of the floating p layer, there is a technique of providing a wide trench and omitting the floating p layer. (For example, refer to Patent Document 3).

  Conventionally, as a technique for reducing the electric field generated in the corner portion of the gate electrode and maintaining the breakdown voltage in the IGBT, an emitter is provided between one and the other of the two gate electrodes provided in the wide trench. Some have provided a polysilicon electrode connected to the electrode (for example, see Patent Document 4).

JP 2000-307116 A JP 2004-39838 A JP 2011-119416 A JP 2012-146810 A

  An IGBT is a switching element that controls a current flowing between a collector electrode and an emitter electrode by a voltage applied to a gate electrode. The power that the IGBT can control ranges from tens of watts to hundreds of thousands of watts, and the switching frequency ranges from tens of hertz to over 100 kilohertz, so it can be used from small power devices such as home air conditioners and microwave ovens to railways. It is widely used for high-power equipment such as inverters in steelworks.

  IGBTs are required to have low loss in order to increase the efficiency of these electric power devices, and reduction of conduction loss and switching loss is required. At the same time, in order to prevent problems such as EMC noise, malfunction, and motor dielectric breakdown, it is required that dv / dt can be controlled according to application specifications.

  Incidentally, Patent Document 1 discloses an IGBT having a structure in which the arrangement pitch of trench gates is changed as shown in FIG. The feature of the IGBT of FIG. 8 is that the channel layer 106 is not formed at the portion where the interval between the trench gates is wide, and the floating p layer 105 is provided.

  With such a configuration, the current flows only in a portion where the interval between the trench gates is narrow, so that the overcurrent flowing at the time of a short circuit can be suppressed, and the breakdown resistance of the element can be improved. In addition, since part of the hole current flows into the channel layer 106 via the floating p layer 105, the hole concentration in the vicinity of the trench gate increases, and the on-voltage can be reduced. Furthermore, the pn junction formed by the floating p layer 105 and the drift layer 104 can relieve the electric field applied to the trench gate and maintain the breakdown voltage.

  However, in the IGBT shown in FIG. 8, there is a case where the controllability of the time change rate dv / dt of the output voltage of the IGBT or the diode of the opposite arm is lowered when the IGBT is turned on. This is illustrated by FIG.

  FIG. 9 is a diagram showing a calculated waveform of the collector-emitter voltage when the IGBT shown in FIG. 8 is turned on. As shown in the figure, there is a period during which dvce / dt does not change and cannot be controlled even if the gate resistance is changed.

  The reason is considered as follows. That is, when the IGBT is turned on, holes transiently flow into the floating p layer 105 in FIG. 8, and the potential of the floating p layer 105 increases. At this time, a displacement current flows through the gate electrode 109 via the feedback capacitance formed by the gate insulating film 110, and the gate potential is raised. Therefore, the time change rate dvge of the mutual conductance gm of the MOSFET structure and the gate-emitter voltage is increased. The time change rate dic / dt of the collector current determined by the product of / dt increases, and the switching speed is accelerated. The amount of holes that flow transiently into the floating p layer 105 is mainly determined by the internal structure of the semiconductor and is difficult to control with an external gate resistance. Therefore, the accelerated dic / dt cannot be controlled by the external gate resistance, and as a result, as shown in FIG. 9, a period in which the collector voltage temporal change rate dvce / dt cannot be controlled by the gate resistance occurs. .

  In order to suppress the increase in gate potential due to the influence of the floating p layer 105, the following techniques have been conventionally proposed.

  In Patent Document 2, the floating p layer 105 and the emitter electrode 114 are electrically connected via a resistor 201 as shown in FIG. As a result, the displacement current flowing from the floating p layer 105 into the gate electrode 109 is reduced, and the rise of the gate potential is suppressed, and as a result, the controllability of dv / dt can be improved.

  Patent Document 3 improves dv / dt controllability by providing a wide trench 423 as shown in FIG. 11 to eliminate the floating p layer and eliminate the potential fluctuation of the gate due to the influence of the floating p layer. can do. Furthermore, since one side of the gate electrode 401 is covered with the thick insulating film 403, the feedback capacitance can be reduced and the controllability of dv / dt can be improved.

  In Patent Document 4, a polysilicon electrode 129 connected to the emitter electrode is provided between the gate electrodes 109 provided in the wide trench 117 as shown in FIG. By providing the polysilicon electrode 129, the electric field generated at the corner portion of the gate electrode 109 is relaxed, the withstand voltage is maintained, and the step generated by providing the wide trench 117 is mitigated.

  By the way, the IGBT is required to improve the controllability of the dv / dt gate drive circuit during the turn-on switching period while maintaining low loss, high breakdown voltage, and high breakdown tolerance. In response to this problem, it has been found that the structure of the above document has the following improvements.

  In the case of Patent Document 2, although the controllability of dv / dt improves as the resistance value of the resistor 201 between the floating p layer 105 and the emitter electrode 114 is decreased, a part of the hole current injected in the ON state is a resistance. Since it flows out to the emitter electrode 114 via 201, the effect of prompting electron injection is reduced, the on-voltage is increased, and the loss is increased. On the contrary, when the resistance value of the resistor 201 is increased, the rise of the on-voltage is reduced, but the controllability of dv / dt is lowered.

  In the case of Patent Document 3, since the feedback capacitance can be reduced, but a wide trench is provided, there is a problem that a large step is formed in the element, resist unevenness occurs in the photo process, and reliability of wire bonding is lowered. .

  In Patent Document 4, the provision of the polysilicon electrode 129 can eliminate the step and ensure the withstand voltage. However, from the inventors' investigation, the electric field at the corner portion of the gate electrode 109 is increased during the switching of the IGBT. It has been found that there is a problem that dynamic avalanche occurs and there is a concern about an increase in switching loss and element destruction.

  The present invention has been made in view of the above points, and the object of the present invention is to control the dv / dt by the gate drive circuit during the turn-on switching period while maintaining low loss, high breakdown voltage and high breakdown tolerance. An object of the present invention is to provide a semiconductor device that can be improved and a power conversion device using the same.

  Therefore, the semiconductor device of the present invention includes, for example, a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer formed near the surface of the first semiconductor layer, and the second semiconductor layer. A first main electrode electrically connected to the second semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near a surface opposite to the second semiconductor layer; A fourth semiconductor layer of a first conductivity type selectively provided on top of three semiconductor layers, a second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer, and the fourth semiconductor layer And a trench that penetrates through the third semiconductor layer and reaches the first semiconductor layer, a gate electrode provided on the inner wall of the trench, and a polysilicon provided between one and the other of the gate electrodes in the trench A first electrode between the gate electrode and the polysilicon electrode. Wherein the fifth semiconductor layer of the second conductivity type is provided in the semiconductor layer.

  Alternatively, the semiconductor device of the present invention includes, for example, a first conductivity type first semiconductor layer and a first conductivity type having a higher impurity concentration than the first semiconductor layer formed near the surface of the first semiconductor layer. A second semiconductor layer; a first main electrode electrically connected to the second semiconductor layer; and a second adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer. A conductive third semiconductor layer, a first conductive fourth semiconductor layer selectively provided on the third semiconductor layer, and electrically connected to the third semiconductor layer and the fourth semiconductor layer A second main electrode; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the first semiconductor layer; a gate electrode provided on an inner wall of the trench; and an insulating film filling the trench And in the first semiconductor layer between one and the other of the gate electrodes Wherein the conductivity type fifth semiconductor layer is provided.

  The power converter of the present invention includes, for example, a pair of input terminals, a plurality of series connection circuits connected between the input terminals, and a plurality of semiconductor switching elements connected in series, and the plurality of series connection circuits. A plurality of output terminals connected to each series connection point, and a power conversion device that converts power by turning on and off the plurality of semiconductor switching elements, wherein each of the plurality of semiconductor switching elements is A semiconductor device according to any one of the above.

  According to the present invention, it is possible to reduce the feedback capacity of the element while maintaining low loss, high breakdown voltage, and high breakdown voltage, thereby improving the controllability of the dv / dt gate drive circuit during the turn-on switching period. Can be made.

It is sectional drawing which shows IGBT which concerns on Example 1 which is one Embodiment of the semiconductor device of this invention. In the IGBT according to Example 1 of the present invention, it is a diagram showing the calculation result of the electric field distribution at the time of switching when there is no p layer 151. In the IGBT according to Example 1 of the present invention, it is a diagram showing a calculation result of the electric field distribution at the time of switching when there is a p layer 151. It is a characteristic view which shows the calculation waveform of the collector-emitter voltage at the time of turn-on in IGBT which concerns on Example 1 which is one Embodiment of the semiconductor device of this invention. It is sectional drawing which shows IGBT which concerns on Example 2 which is one Embodiment of the semiconductor device of this invention. It is sectional drawing which shows IGBT which concerns on Example 3 which is one Embodiment of the semiconductor device of this invention. It is a figure which shows the circuit structure of the power converter device which concerns on Example 4 which is one Embodiment of the power converter device of this invention. It is sectional drawing which shows power MOSFET which concerns on Example 5 which is one Embodiment of the semiconductor device of this invention. It is sectional drawing which shows the conventional IGBT currently disclosed by patent document 1. FIG. FIG. 10 is a characteristic diagram showing a calculated waveform of a collector-emitter voltage at turn-on in a conventional IGBT disclosed in Patent Document 1; It is sectional drawing which shows the conventional IGBT currently disclosed by patent document 2. FIG. It is sectional drawing which shows the conventional IGBT currently disclosed by patent document 3. It is sectional drawing which shows the conventional IGBT currently disclosed by patent document 4.

  The semiconductor device of the present invention has a gate electrode having a side wall structure on the side wall of a wide trench gate, a breakdown voltage maintaining polysilicon electrode is provided between the gate electrodes, and the gate electrode and the polysilicon electrode An impurity layer (p layer in the case of an n-channel type semiconductor device, n layer in the case of a p-channel type semiconductor device) for relaxing an electric field during switching is provided in a silicon layer between To do.

  More specifically, the semiconductor device of the present invention includes a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer formed near the surface of the first semiconductor layer, and the second conductivity type. A first main electrode electrically connected to the semiconductor layer, a third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer; A fourth semiconductor layer of a first conductivity type selectively provided on the third semiconductor layer; a second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer; A trench penetrating the semiconductor layer and the third semiconductor layer and reaching the first semiconductor layer; a gate electrode provided on an inner wall of the trench; and one of the gate electrodes in the trench and the other of the gate electrodes. A polysilicon electrode, and the first electrode between the gate electrode and the polysilicon electrode. Wherein the fifth semiconductor layer of the second conductivity type is provided in the semiconductor layer.

  In the above configuration, it is more preferable that the width of the trench is wider than the width of a region where the trench is not formed.

  In the above configuration, it is more preferable that the polysilicon electrode is electrically connected to the second main electrode.

  In the above configuration, it is more preferable that at least a part of the insulating film between the polysilicon electrode and the trench is thicker than the insulating film between the gate electrode and the trench.

  In the above configuration, it is more preferable that the surface position of the polysilicon electrode is the same as the surface position of the third semiconductor layer and the fourth semiconductor layer.

  In the above structure, a second conductivity type sixth semiconductor layer having an impurity concentration higher than that of the third semiconductor layer may be further provided in the third semiconductor layer. In this case, a seventh conductivity type first semiconductor layer may be further provided between the sixth semiconductor layer and the first semiconductor layer.

  The power conversion device of the present invention includes a pair of input terminals, a plurality of series connection circuits connected between the input terminals, and a plurality of semiconductor switching elements connected in series, and each of the series connection circuits. A plurality of output terminals connected to a connection point, and a power conversion device that performs power conversion by turning on and off the plurality of semiconductor switching elements, each of the plurality of semiconductor switching elements being The semiconductor device is any one of the above.

  According to the above configuration, in the semiconductor device, the floating p layer can be eliminated to reduce the feedback capacitance, and the breakdown resistance can be improved by relaxing the electric field applied to the corner of the gate electrode during switching. Moreover, in the power conversion device, low loss and high reliability can be realized.

  Hereinafter, embodiments of a semiconductor device and a power conversion device using the same according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a cross-sectional structure of an IGBT according to Example 1 which is the first embodiment of the semiconductor device of the present invention.

  The IGBT of the present invention includes a collector electrode 100, a p collector layer 102, an n buffer layer 103, an n − drift layer 104, a p channel layer 106, an n emitter layer 107, a p contact layer 108, a p − layer 151, a wide trench 117. , Gate electrode 109, gate insulating film 110, insulating film 119 in trench 117, polysilicon electrode 129 provided between gate electrodes 109, interlayer insulating film 113, emitter electrode 114, collector terminal 101, emitter terminal 116, gate terminal 115.

  The first feature of this structure is that the gate electrode 109 is formed on the side wall of the wide trench 117 in a side wall structure. By providing a wide trench 117, the floating p layer is eliminated. Further, since the side of the gate electrode 109 facing the gate insulating film 110 is surrounded by an insulating film 119 thicker than the gate insulating film 110, the feedback capacitance can be greatly reduced.

  The second feature of this structure is that a polysilicon electrode 129 is provided between the gate electrodes 109 in the wide trench 117. The polysilicon electrode 129 is connected to the emitter electrode 114, and has an effect of reducing the electric field applied to the corner of the gate electrode 109 when a voltage is applied and improving the withstand voltage.

  A third feature of this structure is that the surface positions of the surface of the polysilicon electrode 129 and the silicon surface of the device are the same. Thereby, the level | step difference in the wide trench 117 is relieve | moderated. If the level difference is large, there may be a problem that resist unevenness occurs in the photo process or the reliability of wire bonding is lowered. However, in this structure, since the level difference can be relaxed, the above problem can be avoided.

  A fourth feature of this structure is that a p − layer 151 is provided in the silicon layer between the gate electrode 109 and the polysilicon electrode 129. By providing the p − layer 151, the electric field applied to the corner portion of the gate electrode 109 during IGBT switching can be relaxed, dynamic avalanche can be suppressed, and the breakdown resistance of the device can be improved. 2a and 2b are diagrams for illustrating a difference (calculation result) in electric field distribution during switching depending on the presence or absence of the p-layer 151. FIG. 2a shows the case without the p-layer 151, and FIG. 2b shows the case with the p-layer 151. In the absence of the p-layer 151, there is a concern that the electric field concentrates on the corner of the gate electrode 109 and a dynamic avalanche occurs. However, by providing the p-layer 151, the corner is applied to the corner of the gate electrode 109. The electric field is alleviated, the generation of dynamic avalanche is suppressed, and the breakdown resistance of the device can be improved.

  FIG. 3 shows a calculated waveform of the collector-emitter voltage at turn-on in the IGBT according to the first embodiment of the present invention. From the figure, it can be seen that in the IGBT according to the first embodiment of the present invention, unlike the conventional IGBT shown in FIG. 9, the dvce / dt of the collector-emitter voltage can be controlled by changing the gate resistance.

  As described above, in the IGBT according to the first embodiment of the present invention, by providing the wide trench 117, the floating p layer is eliminated, and the gate electrode 109 is provided on the sidewall of the trench 117 by the sidewall, thereby returning the gate. The capacity can be reduced, and the controllability of the dv / dt gate drive circuit during the turn-on switching period can be improved. Further, by providing a polysilicon electrode 129 connected to the emitter electrode 114 between the gate electrodes 109, the breakdown voltage is maintained, and by providing a p− layer 151 in the silicon layer between the gate electrode 109 and the polysilicon electrode 129. The electric field applied to the corner of the gate electrode 109 during switching can be relaxed, the generation of dynamic avalanche can be suppressed, and the breakdown resistance of the device can be improved.

  FIG. 4 is a diagram showing a cross-sectional structure of an IGBT according to Example 2 which is a second embodiment of the present invention and is a modification of Example 1 described above. The feature of the second embodiment is that a p-layer 152 having a higher concentration than the p-channel layer is inserted in the p-channel layer 106, which differs from the first embodiment in that respect, but in other respects the embodiment. Same as 1.

  By adding the p layer 152, the hole current at the time of avalanche passes through the p layer 152 and easily escapes to the emitter. Therefore, the hole current passing under the n emitter layer 107 is reduced, and the operation of the parasitic npn transistor is suppressed. There is an effect that the breakdown resistance can be improved.

  FIG. 5 is a diagram showing a cross-sectional structure of an IGBT according to Example 3 which is a third embodiment of the present invention and is a modification of Example 2 described above. The feature of the third embodiment is that an n-layer 153 is further inserted below the p-layer 152 inserted in the structure of the second embodiment. Similar to Example 2.

  Since the pn junction of the p layer 152 and the n layer 153 is formed at the center of the channel layer 106 and the avalanche is generated at the pn junction instead of the corner of the trench, the hole current passing under the n emitter layer 107 is reduced. The parasitic npn transistor has an effect of suppressing the operation and improving the breakdown tolerance.

  FIG. 6 is a diagram showing a circuit configuration of a power conversion device according to a fourth embodiment which is a fourth embodiment of the present invention and is an embodiment of a power conversion device using the IGBT according to each of the above-described examples. It is. FIG. 6 is a circuit diagram of an inverter, in which 601 is a gate drive circuit, 602 is an IGBT, 603 is a diode, 604 and 605 are input terminals, and 606 to 608 are output terminals. In the present embodiment, any one of the IGBTs according to the first to third embodiments is applied to the inverter circuit of FIG. 6 to configure a power conversion device.

  By applying the IGBT according to each of the above-described embodiments to the power conversion device, it is possible to reduce the loss and increase the reliability of the power conversion device.

  In addition, although the inverter circuit was demonstrated in the present Example, the same effect is acquired also about other power converter devices, such as a converter and a chopper.

  FIG. 7 shows a cross-sectional structure of a MOSFET according to Example 5 which is a fifth embodiment of the present invention and is an embodiment in which the structure of the first to third embodiments of the present invention is expanded to a power MOSFET. FIG. The feature of the fifth embodiment is that the gate electrode 109 is provided on the side wall of the trench 117 as a side wall, and the p layer 154 is provided on the silicon layer between the gate electrodes, which is different from the first to third embodiments. However, it is the same as that of any one of Examples 1-3 in another point.

  Since the opposite side of the gate insulating film of the gate electrode 109 is covered with the thick insulating film 119, the feedback capacitance can be reduced, the switching speed of the power MOSFET can be improved, and the p-layer 154 allows the gate electrode during switching. It is possible to alleviate the electric field concentrated on the corner portion 109, suppress the dynamic avalanche, and improve the breakdown resistance of the device.

  As described above, the embodiment of the present invention has been exemplarily described with respect to the n-channel type IGBT and the power MOSFET in particular as the first to fifth embodiments. Of course, p-channel type IGBTs and power MOSFETs are also included in the scope of the present invention, and the same applies to other device structures having a trench gate.

100 collector electrode 101 collector terminal 102 p collector layer 103 n buffer layer 104 n-drift layer 105 floating p layer 106 p channel layer 107 n emitter layer 108 p contact layer 109, 401 gate electrode 110, 402 gate insulating film 113, 119, 403 Insulating film 117, 423 Trench 114, 404 Emitter electrode 115 Gate terminal 116 Emitter terminal 129 Polysilicon electrode 151 p layer 152 p layer 153 n layer 154 p layer 130 Source terminal 131 n + layer 132 Drain electrode 133 Drain terminal 134 Source electrode 201 resistance 601 gate drive circuit 602 IGBT
603 Diode 604,605 Input terminal 606,607,608 Output terminal

Claims (9)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type formed near the surface of the first semiconductor layer;
A first main electrode electrically connected to the second semiconductor layer;
A third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer;
A fourth semiconductor layer of a first conductivity type selectively provided on the third semiconductor layer;
A second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer;
A trench extending through the fourth semiconductor layer and the third semiconductor layer and reaching the first semiconductor layer;
A gate electrode provided on the inner wall of the trench;
A polysilicon electrode provided between one and the other of the gate electrodes in the trench,
A semiconductor device, wherein a fifth semiconductor layer of a second conductivity type is provided in the first semiconductor layer between the gate electrode and the polysilicon electrode. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the trench is formed wider than a region where the trench is not formed. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the polysilicon electrode is electrically connected to a second main electrode. The semiconductor device according to any one of claims 1 to 3,
At least a part of the insulating film between the polysilicon electrode and the trench is thicker than the insulating film between the gate electrode and the trench. The semiconductor device according to any one of claims 1 to 4,
2. The semiconductor device according to claim 1, wherein the surface position of the polysilicon electrode is the same as the surface position of the third semiconductor layer and the fourth semiconductor layer. The semiconductor device according to claim 1,
A semiconductor device, wherein a second conductivity type sixth semiconductor layer having an impurity concentration higher than that of the third semiconductor layer is further provided in the third semiconductor layer. The semiconductor device according to claim 6.
A semiconductor device, wherein a seventh semiconductor layer of a first conductivity type is further provided between the sixth semiconductor layer and the first semiconductor layer. A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a first conductivity type having an impurity concentration higher than that of the first semiconductor layer formed near the surface of the first semiconductor layer;
A first main electrode electrically connected to the second semiconductor layer;
A third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer;
A fourth semiconductor layer of a first conductivity type selectively provided on the third semiconductor layer;
A second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer;
A trench extending through the fourth semiconductor layer and the third semiconductor layer and reaching the first semiconductor layer;
A gate electrode provided on the inner wall of the trench;
An insulating film filling the trench,
A semiconductor device, wherein a fifth semiconductor layer of a second conductivity type is provided in the first semiconductor layer between one and the other of the gate electrodes. A pair of input terminals;
A plurality of series connection circuits connected between the input terminals and connected in series with a plurality of semiconductor switching elements;
A plurality of output terminals connected to each series connection point of the plurality of series connection circuits, and a power conversion device that performs power conversion by turning on and off the plurality of semiconductor switching elements,
Each of these semiconductor switching elements is the semiconductor device of any one of Claims 1 thru | or 8, The power converter device characterized by the above-mentioned.