WO2014128839A1 - Dispositif semi-conducteur et dispositif de conversion d'énergie l'utilisant - Google Patents

Dispositif semi-conducteur et dispositif de conversion d'énergie l'utilisant Download PDF

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WO2014128839A1
WO2014128839A1 PCT/JP2013/054069 JP2013054069W WO2014128839A1 WO 2014128839 A1 WO2014128839 A1 WO 2014128839A1 JP 2013054069 W JP2013054069 W JP 2013054069W WO 2014128839 A1 WO2014128839 A1 WO 2014128839A1
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conductivity type
emitter layer
layer
semiconductor device
concentration emitter
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PCT/JP2013/054069
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English (en)
Japanese (ja)
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昌弘 増永
貴之 橋本
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株式会社 日立製作所
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Priority to PCT/JP2013/054069 priority Critical patent/WO2014128839A1/fr
Priority to TW102147959A priority patent/TWI533451B/zh
Publication of WO2014128839A1 publication Critical patent/WO2014128839A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a semiconductor device suitable for an insulated gate bipolar transistor having an insulated gate structure (hereinafter, abbreviated as IGBT) and the semiconductor device.
  • IGBT insulated gate bipolar transistor having an insulated gate structure
  • the present invention relates to a power conversion apparatus.
  • the IGBT is a switching element that controls the current flowing between the collector and the emitter by applying a voltage to the gate electrode.
  • IGBTs can control a wide range of power from tens of watts to hundreds of thousands of watts, and switching frequency ranges from tens of hertz to over a hundred kilohertz, so low-power devices such as air conditioners and high-power devices such as railways and steelworks Used up to. These power devices are strongly required to reduce the conduction loss and switching loss of the IGBT in order to increase the efficiency and miniaturization of the system.
  • the conduction loss is effective in reducing the voltage drop (ON voltage) at the time of ON, and can be reduced as the concentration of minority carriers accumulated in the drift layer increases. Further, the turn-off loss is smaller as the accumulated minority carrier concentration is lower, and there is a trade-off relationship between the on-voltage and the turn-off loss. In order to improve the trade-off, it is effective to enhance the IE (electron injection promotion) effect, but the characteristics of the IGBT are approaching the limit, and it is difficult to further improve the characteristics.
  • IE electron injection promotion
  • Patent Document 1 Japanese Patent Laid-Open No. 3-268363 discloses a four-terminal IGBT structure as shown in FIG.
  • the high-concentration p-type emitter layer 7 and the high-concentration n + layer 25 are adjacent to each other on the collector side, and individual electrodes are connected to the respective regions.
  • the high concentration n + layer 25 is operated during turn-off, minority carrier accumulation can be reduced and tail current can be reduced, so that turn-off loss can be reduced.
  • it since it operates as an IGBT when it is on and operates as a MOSFET with a fast switching speed when it is turned off, the trade-off between the on voltage and the turn-off loss can be improved.
  • the IGBT structure shown in FIG. 15 has a problem that the jumping voltage between the collector and the emitter is large because it operates as a MOSFET when it is off. Further, since there is no hole injection while the high-concentration n + layer 25 is operated, there is a problem that conduction loss immediately before turn-off increases.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in jumping voltage and improving a trade-off between on-voltage and turn-off loss, and power conversion using the same. Is to provide a device.
  • a semiconductor device includes a second conductivity type high-concentration emitter layer and a second conductivity type low-concentration emitter layer provided separately from each other in order to inject carriers into the semiconductor device. And a main electrode which is electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer, respectively.
  • the present invention since the amount of carriers accumulated in the semiconductor device can be controlled during the operation of the semiconductor device, it is possible to improve the trade-off between the on-voltage and the turn-off loss while suppressing an increase in jumping voltage. Further, when the semiconductor device according to the present invention is used for a power conversion device, the reliability of the power conversion device can be improved and the power loss can be reduced.
  • Embodiment 1 shows an IGBT according to a first embodiment of the present invention.
  • 3 is an example of a circuit using the IGBT according to the first embodiment.
  • the drive sequence of Embodiment 1 is shown.
  • the trade-off relationship between the on-voltage and the turn-off loss in the first embodiment is shown.
  • the IGBT which is Embodiment 2 of this invention is shown.
  • the IGBT which is Embodiment 3 of this invention is shown.
  • the IGBT which is a modification of Embodiment 3 is shown.
  • the IGBT which is Embodiment 4 of this invention is shown.
  • the IGBT which is a modification of Embodiment 4 is shown.
  • the IGBT which is Embodiment 5 of this invention is shown.
  • the IGBT which is Embodiment 6 of this invention is shown.
  • An IGBT which is a modification of the sixth embodiment is shown.
  • An IGBT according to a seventh embodiment of the present invention will be described.
  • the power converter device which is Embodiment 9 of this invention is shown.
  • the conventional IGBT currently disclosed by patent document 1 is shown.
  • 10 shows a diode according to an eighth embodiment of the present invention.
  • FIG. 1 shows a cross-sectional structure of the IGBT according to the first embodiment of the present invention.
  • n ⁇ substrate 1, p-type base layer 2 selectively formed on the surface of n ⁇ substrate 1, and n + -type formed on the surface of p-type base layer.
  • a gate electrode 6 is provided on the surface of the p-type base layer 2 sandwiched between the source layers 3 via a gate oxide film 5.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are disposed on the opposite surface of the n ⁇ substrate 1, and the n ⁇ layer 1 is interposed between them. By interposing a part, they are separated from each other as individual p-type conductivity type semiconductor layers. Separate electrodes 9 and 10 are electrically connected to the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8, respectively. That is, this IGBT is a four-terminal element.
  • FIG. 2 shows an example of a circuit using the IGBT of FIG. 1, in which the collector terminal c1 corresponds to a terminal connected to the p + type high concentration emitter layer 7 of FIG. 1, and the terminal c2 is a p ⁇ type low concentration emitter layer. 8 corresponds to the terminal connected to 8.
  • the collector terminal c2 of the IGBT 201 is connected to the output terminal 209 (C) via the MOSFET 202 serving as a switch, and the other collector terminal c1 is directly connected to the output terminal 209 (C).
  • the collector terminal c1 may be connected to the output terminal 209 (C) via a switching element different from the MOSFET 202, and the switching element is preferably an insulated gate type element such as MOSFET or IGBT. Further, instead of MOSFET 202, another insulated gate control type element such as IGBT may be used.
  • a voltage for example, 15V
  • a voltage for example, 0V
  • the collector terminal c1 and the emitter terminal 210 Current is passed between Accordingly, since minority carriers (holes) are highly injected from the p + -type high-concentration emitter layer 7 connected to the terminal c1 into the n ⁇ substrate 1, conductivity modulation is promoted and the on-voltage is reduced.
  • An ON signal is input to the terminal G2 from several ⁇ s before the terminal G1 (IGBT 201) is turned off, and a current flows mainly between the collector terminal c2 and the emitter terminal 210.
  • the collector terminals c1 and c2 are both connected to the output terminal 209 (C), but the p-type low-concentration emitter layer 8 having a lower impurity concentration has a lower built-in voltage. 8 (terminal c2) becomes easy to flow. For this reason, the minority carriers injected from the collector are reduced and the charge accumulated in the n ⁇ substrate 1 is reduced, so that the turn-off loss can be reduced. Further, since it operates as a low-injection IGBT when it is off, a tail current is generated, and an increase in jumping voltage between the collector and the emitter can be suppressed.
  • FIG. 3 shows a driving sequence of the gate electrode 6 (terminal G1) and the gate electrode 212 (terminal G2) of the MOSFET 202.
  • Period 1 is a period in which minority carriers are highly injected. A voltage at which the MOS transistor 204 is turned on is input to the terminal G1, and a voltage at which the MOSFET 202 is turned off is input to the terminal G2. During this period, minority carriers are injected at a high rate, so that the on-voltage is smaller than in other periods.
  • Period 2 is a period during which minority carriers are injected at a low rate, and an ON signal is input to the terminal G2 from 0.1 to 10 ⁇ s before the terminal G1 is turned off.
  • Period 3 is a period in which the IGBT 201 is turned off. First, a voltage at which the IGBT 201 is turned off is input to the terminal G1, and a voltage at which the MOSFET 202 is turned on is input to the terminal G2.
  • the terminal G2 receives an OFF signal during the period 3 in which the OFF signal is input to the terminal G1, and thereafter, only the terminal G1 is switched from OFF to ON, and the period 4 is shifted to.
  • Period 4 is the same as period 1, and thereafter, the sequence of periods 1 to 3 is repeated. In the present embodiment, such a drive sequence can improve the trade-off between the on-voltage and the turn-off loss.
  • FIG. 4 shows an example of the trade-off relationship between the on-voltage and the turn-off loss, and the jump-up voltage has the same magnitude.
  • the figure shows a comparative example corresponding to FIG. 15 and the first embodiment.
  • the turn-off loss of the present embodiment is reduced by 57% compared with the comparative example, and the characteristics are greatly improved.
  • the collector and emitter are formed by forming the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8 on the collector side and providing individual electrodes for each.
  • the trade-off between the on-voltage and the turn-off loss can be improved while suppressing an increase in jumping voltage.
  • FIG. 5 shows a cross-sectional structure of the IGBT according to the second embodiment of the present invention.
  • FIG. 6 shows a cross-sectional structure of the IGBT according to the third embodiment of the present invention.
  • n + with an impurity concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 is provided between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8.
  • Layer 13 is provided.
  • the operation of the parasitic pnp bipolar transistor composed of the p + -type high concentration emitter layer 7, the n ⁇ substrate 1 (or the n buffer layer 12), and the p ⁇ type low concentration emitter layer 8 is suppressed. it can.
  • the parasitic pnp transistor When the parasitic pnp transistor operates, it becomes difficult to control minority carrier injection by the external switching element 11 (switching between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8), and the on-voltage and turn-off loss Affects the trade-off.
  • the parasitic transistor operates when the external switching element 11 is turned on, since the minority carriers are highly injected from the p + -type high-concentration emitter layer 7, the amount of accumulated holes in the n ⁇ substrate 1 increases. Turn-off loss increases.
  • the entire region sandwiched between the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8 is the high concentration n + layer 13.
  • the structure in which a part of the region sandwiched between the p ⁇ -type low-concentration emitter layer 8 is the high-concentration n + layer 13 can also suppress the operation of the parasitic transistor.
  • the depth of the high concentration n + layer 13 may be shallower than that of the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8.
  • FIG. 8 shows a cross-sectional structure of an IGBT according to the fourth embodiment of the present invention.
  • an insulating layer 14 is provided between the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8.
  • the operation of the parasitic transistor can be suppressed as compared with the third embodiment.
  • the operation of the parasitic transistor is suppressed by providing the high-concentration n + layer 13, but in the fourth embodiment, the operation of the parasitic transistor is performed by using a part of the n layer of the parasitic pnp transistor as an insulating layer. Suppressed. In FIG.
  • the entire region sandwiched between the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 is the insulating layer 14, but the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 7 A part of the region sandwiched between the emitter layers 8 may be an insulating layer 14, and the depth of the insulating layer 14 is shallower than that of the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8. May be. Further, as shown in FIG.
  • FIG. 10 shows a cross-sectional structure of an IGBT according to the fifth embodiment of the present invention.
  • the distance ln between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8 is longer than the hole diffusion distance Lp (ln> Lp).
  • the operation of the parasitic pnp bipolar transistor can be performed without providing a high concentration n + layer, an insulating layer, or the like between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8. Can be suppressed.
  • the hole diffusion distance Lp is obtained from the square root of the product of the hole diffusion coefficient Dp and lifetime ⁇ p, and the parasitic transistor operates when Lp is longer than the width ln of the base region.
  • the cause is that holes injected from the emitter region (for example, p ⁇ -type low-concentration emitter layer 8) are not recombined and extinguished in the base region (n buffer layer 12 or n ⁇ substrate 1) but diffused to the collector region (for example, p This is to reach the + type high concentration emitter layer 7). Therefore, recombination annihilation occurs before the holes reach the collector region due to Lp shortening or ln increase, so that the operation of the parasitic transistor can be suppressed.
  • the impurity concentration of the n layer (n-substrate 1 in FIG. 10) between the p + type high concentration emitter layer 7 and the p ⁇ type low concentration emitter layer 8 is 1 ⁇ 10 17 cm ⁇ 3 or less, ln is 5 ⁇ m. It is desirable to set it above.
  • the diffusion distance Lp can be shortened by shortening the lifetime ⁇ p, and can be controlled by introducing a lifetime killer on the collector side.
  • Lifetime killer that recombines holes uses heavy metals such as gold and platinum, or irradiation damage caused by radiation such as electron beams, etc., thereby suppressing the operation of parasitic transistors even if ln is shortened to about 1 ⁇ m. it can.
  • (Embodiment 6) 11 and 12 show a cross-sectional structure of an IGBT which is a sixth embodiment of the present invention and a modification thereof, respectively. In these IGBTs, an n + -type hole barrier layer 15 is provided between the p + -type high-concentration emitter layer 7 and the n buffer layer 12 (or n ⁇ substrate 1).
  • FIG. 13 shows a cross-sectional structure of an IGBT which is an embodiment of the present invention.
  • the IGBT according to the seventh embodiment includes an n ⁇ substrate 1, a p-type base layer 2 selectively formed on the surface of the n ⁇ substrate 1, and an n + -type source formed on the surface of the p-type base layer.
  • a gate electrode 6 provided on the surface of the p-type base layer 2 sandwiched between the layers 3 via a gate oxide film 5 is provided.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are formed on the opposite surfaces of the n ⁇ substrate 1 so as to be separated from each other as in the first embodiment.
  • the collector electrode 20 is connected to the p + -type high concentration emitter layer 7, and a second gate is formed on the surface of the n ⁇ substrate 1 sandwiched between the p ⁇ -type high concentration emitter layer 7 and the p-type low concentration emitter layer 8.
  • a second gate electrode 18 is formed through the oxide film 17.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are electrically connected by the p-type inversion layer 19 formed by inputting a negative voltage to the second gate electrode.
  • FIG. 16 shows a sectional structure of a diode according to the eighth embodiment of the present invention.
  • the cathode side n + layer 21 formed on the surface of the n ⁇ substrate 1, and the cathode electrode 22 are provided on the surface of the n + layer 21.
  • the p + -type high-concentration emitter layer 7 and the p--type low-concentration emitter layer 8 are separated from each other on the opposite surface of the n ⁇ substrate 1 by interposing the n ⁇ substrate 1 therebetween, and Separate electrodes are connected to the p + -type high concentration emitter layer 7 and the p ⁇ -type low concentration emitter layer 8, respectively.
  • FIG. 14 shows an example of a power conversion device using the IGBT or the diode described in each embodiment described above.
  • a series circuit in which two IGBTs 107 are connected in series is connected between the DC terminals 101 and 102.
  • This series circuit is provided for the number of AC phases, and the series connection point of each series circuit is connected to the AC terminals 103, 104, and 105.
  • the number of AC phases is three, and three series circuits are provided.
  • a diode 108 is connected in antiparallel to each IGBT 107.
  • each IGBT 107 When each IGBT 107 is turned on / off by the gate drive circuit 106, the DC power received by the DC terminals 101, 102 is converted into AC power, and the AC power is output from the AC terminals 103, 104, 105.
  • the IGBT 107 the IGBTs of the first to seventh embodiments described above are used. Further, as the diode 108, the diode of Embodiment 8 may be used. Further, the IGBT 107 may be a conventional IGBT, and the diode of the eighth embodiment may be used as the diode 108.
  • the power loss of the power conversion device can be reduced by applying the IGBT or the diode described in each embodiment described above to the power conversion device.
  • the ninth embodiment is an inverter device
  • the IGBT and the diode according to the present invention can be applied to other power conversion devices such as a converter and a chopper, and the same effect can be obtained.
  • the gate shape on the emitter side is not limited to the planar type, but may be a trench type, and the gates may be arranged in a stripe shape or a mesh shape.
  • the above embodiment is a vertical IGBT and a vertical diode, it may be a horizontal IGBT and a horizontal diode.
  • the semiconductor material may be silicon or silicon carbide.
  • n-substrate 2 p-type base layer 3: n-type source layer 4: emitter electrode 5: oxide film 6: gate electrode 7: p-type high-concentration emitter layer 8: p-type low-concentration emitter layer 9: p-type high Collector electrode connected to the concentration emitter layer 10: Collector electrode connected to the p-type low concentration emitter layer 11: External switching element 12: Buffer layer 13: High concentration n + layer 14: Insulating layer 15: Hole barrier layer 16 : External MOSFET 17: Second gate oxide film 18: Second gate electrode 19: P-type inversion layer 20: Collector electrode 21: Cathode side n + layer 22: Cathode electrode 23: Anode electrode connected to high-concentration p-type emitter layer 24 : Anode electrode connected to low-concentration p-type emitter layer 25: High-concentration n + layer 101, 102: DC terminals 103, 104, 105: AC terminal 106: Gate drive circuit 107: IGBT 108

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur qui comprend : des couches de base de type p (2) formées de manière sélective sur une surface principale d'un substrat de type n (1) ; des couches de source de type n (3) formées sur les surfaces des couches de base de type p ; des couches d'émetteur à concentration élevée de type p (7) et des couches d'émetteur à faible concentration de type p (8) agencées séparément les unes des autres sur une autre surface principale du substrat de type n (1) ; une électrode d'émetteur connectée électriquement aux couches de base de type p (2) et aux couches de source de type n (3) ; des électrodes de grille (6) agencées sur les surfaces des couches de base de type p (2) de façon à être prises en sandwich entre le substrat de type n (1) et les couches de source de type n (3) sur des films d'oxyde de grille (5) ; et une électrode de collecteur électriquement connectée de manière individuelle à chacune des couches d'émetteur à concentration élevée de type p (7) et des couches d'émetteur à faible concentration de type p (8).
PCT/JP2013/054069 2013-02-20 2013-02-20 Dispositif semi-conducteur et dispositif de conversion d'énergie l'utilisant WO2014128839A1 (fr)

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TW102147959A TWI533451B (zh) 2013-02-20 2013-12-24 半導體裝置及使用其之電力轉換裝置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111448668A (zh) * 2017-12-18 2020-07-24 株式会社日立制作所 功率半导体装置、模块及制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268363A (ja) * 1990-03-16 1991-11-29 Fuji Electric Co Ltd 絶縁ゲートバイポーラトランジスタ
JPH0661495A (ja) * 1992-08-07 1994-03-04 Hitachi Ltd 半導体装置及びその製法
JP2006332199A (ja) * 2005-05-24 2006-12-07 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268363A (ja) * 1990-03-16 1991-11-29 Fuji Electric Co Ltd 絶縁ゲートバイポーラトランジスタ
JPH0661495A (ja) * 1992-08-07 1994-03-04 Hitachi Ltd 半導体装置及びその製法
JP2006332199A (ja) * 2005-05-24 2006-12-07 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111448668A (zh) * 2017-12-18 2020-07-24 株式会社日立制作所 功率半导体装置、模块及制造方法
CN111448668B (zh) * 2017-12-18 2023-09-01 株式会社日立制作所 功率半导体装置、模块及制造方法

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