JP2007288094A - Igbt, and gate drive circuit for driving it - Google Patents

Igbt, and gate drive circuit for driving it Download PDF

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JP2007288094A
JP2007288094A JP2006116584A JP2006116584A JP2007288094A JP 2007288094 A JP2007288094 A JP 2007288094A JP 2006116584 A JP2006116584 A JP 2006116584A JP 2006116584 A JP2006116584 A JP 2006116584A JP 2007288094 A JP2007288094 A JP 2007288094A
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gate
igbt
resistance
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drive circuit
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Yuichi Onozawa
勇一 小野沢
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IGBT in which spike voltage is reduced while reducing turn-off loss at turn-off in an inductive load circuit, and to provide a gate drive circuit for driving the IGBT. <P>SOLUTION: A gate of the IGBT 1 is connected to the gate resistance Rg of the gate drive circuit 2, and an emitter of the IGBT 1 and a lower potential side of the gate drive circuit 2 are connected. The gate drive circuit 2 consists of a gate drive unit 3 and the gate resistance Rg. A time constant which is a product of the gate resistance Rg and the gate input capacitance Cg of the IGBT 1 is set to 500 ns or below, and peak impurity concentration of a collector layer of the IGBT 1 is set to 1×10<SP>16</SP>cm<SP>-3</SP>or above, reducing thereby the spike voltage is made small and the turn-off loss. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）とそれを駆動するゲート駆動回路に関する。     The present invention relates to an IGBT (Insulated Gate Bipolar Transistor) and a gate driving circuit for driving the IGBT.

電力変換装置の低消費電力化が進む中で、その装置の中で中心的な役割を果たすパワーデバイス（スイッチングデバイス）の低損失化の期待が大きい。しかしながら、スイッチングスピードの高速化やバス電圧（電源電圧）の高圧化に伴い、ターンオフ時のスパイク電圧（跳ね上がり電圧）が高くなりデバイスに印加される責務が厳しくなっている。このスパイク電圧は配線インダクタンスに大きく依存しているため、スパイク電圧を抑制するために、配線インダクタンスを低減することが重要となる。しかし、配線インダクタンスを低減することには限界があり、素子で決まるターンオフ時の電流の傾き（電流減少率：−ｄＩ／ｄｔ）を小さくすることが望まれている。   As power consumption of power converters is reduced, there is a great expectation for lower loss of power devices (switching devices) that play a central role in the devices. However, as switching speed is increased and bus voltage (power supply voltage) is increased, a spike voltage (bounce voltage) at the time of turn-off is increased, and the duty to be applied to the device becomes severe. Since this spike voltage greatly depends on the wiring inductance, it is important to reduce the wiring inductance in order to suppress the spike voltage. However, there is a limit to reducing the wiring inductance, and it is desired to reduce the current gradient (current reduction rate: -dI / dt) at turn-off determined by the element.

まず、ＩＧＢＴの構造について説明する。
図７はＩＧＢＴの断面図であり、（ａ）がＰＴ（パンチスルー）型、（ｂ）がＮＰＴ（ノン・パンチスルー）型、（ｃ）がＦＳ（フィールドストップ）型で、ゲート構造がプレーナゲート型である。（ｄ）は（ｂ）のＮＰＴ型をトレンチゲート型としたものである。尚、裏面側のコレクタ金属電極については省略してある。 First, the structure of the IGBT will be described.
FIG. 7 is a cross-sectional view of an IGBT, where (a) is a PT (punch through) type, (b) is an NPT (non punch through) type, (c) is an FS (field stop) type, and the gate structure is planar. It is a gate type. (D) is a trench gate type of the NPT type of (b). The collector metal electrode on the back side is omitted.

これらの構造は公知であるので、その特徴のみ説明する。（ａ）のＰＴ型はｐ＋コレクタ層３１、ｎ＋バッファ層３２、ｎ−ドリフト層３３からなるエピタキシャルシリコンウェハの基板を用い、ｐウェル層３４、ｎ＋エミッタ層３５を拡散で形成し、基板上にゲート酸化膜３６を介したゲート電極３７と、さらに層間絶縁膜３８とエミッタ電極３９を有する構造である。このＰＴ型はエピタキシャルシリコンウェハを用いているため、基板の厚みが３５０μｍ程度である。 Since these structures are known, only their features will be described. The PT type (a) uses an epitaxial silicon wafer substrate comprising a p + collector layer 31, an n + buffer layer 32, and an n − drift layer 33, and a p well layer 34 and an n + emitter layer 35 are formed by diffusion. In this structure, a gate electrode 37 with a gate oxide film 36 interposed therebetween, an interlayer insulating film 38 and an emitter electrode 39 are provided on the substrate. Since this PT type uses an epitaxial silicon wafer, the thickness of the substrate is about 350 μm.

（ｂ）のＮＰＴ型は、ＦＺウェハを用い、基板表面にｐウェル層３４、ｎ＋エミッタ層３５を形成してから基板裏面を削り、ｐ＋層４１をイオン注入で形成している。コストメリットのあるＦＺウェハを使用でき、低結晶欠陥であるので信頼性も高い。基板の厚みは１００μｍ程度である。
（ｃ）のＦＳ型は、ＦＺウェハを用い、基板表面にｐウェル層３４、ｎ＋エミッタ層３５を形成してから基板裏面を削り、ｎ型のフィールドストップ層４３とｐ＋コレクタ層４１をイオン注入で形成している。ＮＰＴ型では、オフ時に空乏層がコレクタ側に到達しないようにｎ−ドリフト層４２を厚くする必要があるが、ＦＳ型では空乏層を止めるためのフィールドストップ層４３を形成しているため、ＮＰＴ型に対してｎ−ドリフト層４２の厚さが薄くでき、オン電圧を低減することができる。また、ＦＳ型ではｎ−ドリフト層４２の厚さが薄いので過剰キャリアが少なく、空乏層が伸びきった状態での中性領域の残り幅が少ないため、ターンオフ損失を低減できる。 The NPT type (b) uses an FZ wafer, and after forming a p-well layer 34 and an n + emitter layer 35 on the substrate surface, the back surface of the substrate is shaved and a p + layer 41 is formed by ion implantation. Cost-effective FZ wafers can be used, and the reliability is high because of low crystal defects. The thickness of the substrate is about 100 μm.
The FS type (c) uses an FZ wafer, and after forming a p-well layer 34 and an n + emitter layer 35 on the substrate surface, the back surface of the substrate is shaved, and an n-type field stop layer 43 and a p + collector layer 41 are formed. It is formed by ion implantation. In the NPT type, it is necessary to increase the thickness of the n − drift layer 42 so that the depletion layer does not reach the collector side at the time of OFF. However, in the FS type, the field stop layer 43 for stopping the depletion layer is formed. The n − drift layer 42 can be made thinner with respect to the mold, and the on-voltage can be reduced. In the FS type, since the thickness of the n − drift layer 42 is thin, there are few excess carriers, and the remaining width of the neutral region when the depletion layer is fully extended is small, so that the turn-off loss can be reduced.

（ｄ）はゲート構造のトレンチゲート型を説明するものである。基板表面からトレンチ４５を形成し、そのトレンチ４５内にゲート酸化膜４７を介してポリシリコンのゲート電極４６を形成している。トレンチゲート型では、プレーナゲート型に対してセル密度を大幅に増加させられるのでチャネル部４９の電圧降下を抑えることができる。また、プレーナゲート型特有のチャネル部４８で挟まれたＪＦＥＴ５０という部分がトレンチゲート型では存在しないので、この部分の電圧降下を完全に削減でき、結果としてオン電圧を大幅に低減することができる。尚、（ｂ）のＮＰＴ型についてトレンチゲート型を（ｄ）で例示したが、（ａ）のＰＴ型、（ｃ）のＦＳ型でトレンチゲーチ型としてもよい。   (D) illustrates the trench gate type of the gate structure. A trench 45 is formed from the substrate surface, and a polysilicon gate electrode 46 is formed in the trench 45 via a gate oxide film 47. In the trench gate type, since the cell density can be greatly increased as compared with the planar gate type, a voltage drop in the channel portion 49 can be suppressed. In addition, since the portion called JFET 50 sandwiched between the channel portions 48 peculiar to the planar gate type does not exist in the trench gate type, the voltage drop in this portion can be completely reduced, and as a result, the on-voltage can be greatly reduced. In addition, although the trench gate type was illustrated by (d) about the NPT type of (b), it is good also as a trench gate type with the PT type of (a) and the FS type of (c).

次に、スイッチング動作について説明する。
図５は、誘導負荷回路の一例を示す回路図である。ＩＧＢＴ２１のコレクタに誘導負荷２４の一端とダイオード２５のアノードが接続し、誘導負荷２４の他端とダイオード２５のカソードが高電圧電源２６の高電位側に接続し、高電圧電源２６のグランド（低電位側）とＩＧＢＴ２１のエミッタが接続する。ＩＧＢＴ２１のゲートはゲート駆動回路２２のゲート抵抗Ｒｇｏと接続し、ＩＧＢＴ２１のエミッタとゲート駆動回路２１の低電位側と接続する。ゲート駆動回路２２は、ゲート駆動ユニット２３とゲート抵抗Ｒｇｏで構成され、ゲート駆動ユニット２３内には低電圧電源が組み込まれている。図中のＫ部が本発明に関係する箇所でＩＧＢＴ２１とそれを駆動するゲート駆動回路２２である。 Next, the switching operation will be described.
FIG. 5 is a circuit diagram illustrating an example of an inductive load circuit. One end of the inductive load 24 and the anode of the diode 25 are connected to the collector of the IGBT 21, the other end of the inductive load 24 and the cathode of the diode 25 are connected to the high potential side of the high voltage power source 26, and the ground of the high voltage power source 26 (low The potential side) and the emitter of the IGBT 21 are connected. The gate of the IGBT 21 is connected to the gate resistance Rgo of the gate drive circuit 22, and is connected to the emitter of the IGBT 21 and the low potential side of the gate drive circuit 21. The gate drive circuit 22 includes a gate drive unit 23 and a gate resistor Rgo, and a low voltage power source is incorporated in the gate drive unit 23. The portion K in the figure is the IGBT 21 and the gate drive circuit 22 for driving the IGBT 21 at locations related to the present invention.

図５の回路動作を説明する。ＩＧＢＴ２１のゲートにオン信号を入力し、ＩＧＢＴ２１をオン状態にする。ＩＧＢＴ２１がオンすると、高電圧電源２６から誘導負荷２４とＩＧＢＴ２１を通ってコレクタ電流ＩＣが流れる。つぎに、ゲート抵抗Ｒｇｏを介してＩＧＢＴ２１のゲートにオフ信号を入力し、ＩＧＢＴ２１をオフ状態にする。ＩＧＢＴ２１がオフ状態になると、ＩＧＢＴ２１のゲート入力容量Ｃｇに蓄積した電荷がゲート抵抗Ｒｇｏを介してゲート駆動ユニット２３に流れ、ゲート電圧は低下して行く。ゲート電圧がゲート閾値電圧以上にある間はチャネルを介してＩＧＢＴ２１のエミッタ層からドリフト層へ電子が注入される。またＩＧＢＴ２１のエミッタ層とドリフト層のｐｎ接合が回復すると、空乏層がコレクタ層に向って広がって行き、電子がコレクタ層側へ向って吐き出される。チャネルを介して注入された電子と吐き出された電子はコレクタ層からドリフト層へ注入された正孔と再結合する。この再結合でドリフト層内のキャリアは減少し、ＩＧＢＴ２１のコレクタ電流ＩＣは減少し、その電流減少率(−ｄＩ／ｄｔ)と配線インダクタンスＬの積（ＬｄＩ／ｄｔ）により、コレクタ・エミッタ間電圧ＶＣＥは上昇してスパイク電圧ＶＳＰを発生させる。図６に、図５の回路の動作波形で、コレクタ電流（ＩＣ）波形とコレクタ電圧（ＶＣＥ）波形を示す。   The circuit operation of FIG. 5 will be described. An ON signal is input to the gate of the IGBT 21 to turn on the IGBT 21. When the IGBT 21 is turned on, a collector current IC flows from the high voltage power supply 26 through the inductive load 24 and the IGBT 21. Next, an off signal is input to the gate of the IGBT 21 through the gate resistor Rgo, and the IGBT 21 is turned off. When the IGBT 21 is turned off, the charge accumulated in the gate input capacitance Cg of the IGBT 21 flows to the gate drive unit 23 through the gate resistance Rgo, and the gate voltage is lowered. While the gate voltage is equal to or higher than the gate threshold voltage, electrons are injected from the emitter layer of the IGBT 21 into the drift layer through the channel. Further, when the pn junction between the emitter layer and the drift layer of the IGBT 21 is recovered, the depletion layer spreads toward the collector layer, and electrons are discharged toward the collector layer. Electrons injected and discharged through the channel recombine with holes injected from the collector layer to the drift layer. By this recombination, carriers in the drift layer decrease, the collector current IC of the IGBT 21 decreases, and the collector-emitter voltage is calculated by the product of the current decrease rate (−dI / dt) and the wiring inductance L (LdI / dt). VCE rises and generates a spike voltage VSP. FIG. 6 shows a collector current (IC) waveform and a collector voltage (VCE) waveform as operation waveforms of the circuit of FIG.

また、特許文献１において、ゲート駆動回路の最終段のトランジスタとＩＧＢＴの間に、直列に複数の抵抗Ｒｇ（ｅｘｔ）、Ｒｇ（ｉｎｔ）を配置し、その間にキャパシタンスＣ（ｅｘｔ）をＩＧＢＴのゲート−エミッタ間に並列接続することで，低損失なターンオンを実現できるゲート駆動回路が開示されている。
また、特許文献２において、電力変換器の主回路を構成するＩＧＢＴのゲート信号供給回路を２回路での２重化構成とし、各ゲート信号供給回路をターンオン用ゲート電圧とターンオフ用ゲート電圧を切り替える制御用スイッチング回路とゲート抵抗により構成し、一定の時間間隔でそれぞれのゲート信号供給回路を動作させることで、小損失、低サージ電圧（スパイク電圧）でターンオフできるゲート駆動回路が開示されている。 Further, in Patent Document 1, a plurality of resistors Rg (ext) and Rg (int) are arranged in series between the final stage transistor of the gate drive circuit and the IGBT, and the capacitance C (ext) is set between the gates of the IGBTs. A gate drive circuit that can realize low-loss turn-on by connecting in parallel between emitters is disclosed.
Also, in Patent Document 2, the IGBT gate signal supply circuit that constitutes the main circuit of the power converter has a dual configuration with two circuits, and each gate signal supply circuit is switched between a turn-on gate voltage and a turn-off gate voltage. There has been disclosed a gate drive circuit that is configured by a control switching circuit and a gate resistor, and can be turned off with a small loss and a low surge voltage (spike voltage) by operating each gate signal supply circuit at regular time intervals.

また、特許文献３において、ターンオフのとき、主電流がフォール時間に移行する前に、制御電極の電圧を半導体素子の閾値電圧Ｖｔｈ以下に低下させることにより、主電極間の電圧上昇前に電子注入を停止させ、電流密度の安定性を向上でき、電流集中や発振などを阻止して信頼性を向上させることができることが開示されている。
また、特許文献４において、プレーナ構造のＰＴ型のＩＧＢＴで、不純物濃度が１×１０１３ｃｍ−３からなるｎベース層の裏面に層幅が４０μｍで、ピーク濃度が１×１０１６ｃｍ−３を有するｎバッファ層を形成し、このｎバッファ層の裏面に層厚が５μｍで、ピーク濃度が１×１０１６ｃｍ−３のｐ−層と、層厚が１μｍで、ピーク濃度が１×１０１７ｃｍ−３のｐ＋層を形成することで、ターンオフ損失を増大させずに低オン抵抗化できることが開示されている。
特開２００３−１２５５７４号公報 特開平１０−７５１６４号公報 特開２０００−４０９５１号公報 特開２００４−３１１４８１号公報 Further, in Patent Document 3, at the time of turn-off, before the main current shifts to the fall time, the voltage of the control electrode is lowered below the threshold voltage Vth of the semiconductor element, thereby injecting electrons before increasing the voltage between the main electrodes. It is disclosed that the stability of current density can be improved and the reliability can be improved by preventing current concentration and oscillation.
In Patent Document 4, a planar type PT-type IGBT has an n-type base layer having an impurity concentration of 1 × 10 13 cm −3 on the back surface with a layer width of 40 μm and a peak concentration of 1 × 10 16 cm −3. An n buffer layer having a thickness of 5 μm on the back surface of the n buffer layer, a p − layer having a peak concentration of 1 × 10 16 cm −3 , a layer thickness of 1 μm, and a peak concentration of 1 × 10 It is disclosed that the on-resistance can be reduced without increasing the turn-off loss by forming a 17 cm −3 p + layer.
JP 2003-125574 A JP-A-10-75164 JP 2000-40951 A JP 2004-311481 A

ＭＯＳＦＥＴやＩＧＢＴでは、一般にターンオフ時のスパイク電圧ＶＳＰを小さくするには図５に示すゲート駆動回路のゲート抵抗Ｒｇｏ（外付け）を大きくして、−ｄＩ／ｄｔを小さくする方法が行われている。しかしながらゲート抵抗Ｒｇｏを大きくするとゲート入力容量Ｃｇに蓄積した電荷が放電し難くなり、ミラー期間（空乏層が延びて行く時間：キャリアが吐き出される時間）が延びて、ターンオフ損失が増大するという問題がある。   In MOSFETs and IGBTs, in general, in order to reduce the spike voltage VSP at the time of turn-off, a method of increasing the gate resistance Rgo (external) of the gate driving circuit shown in FIG. 5 to reduce -dI / dt is performed. . However, if the gate resistance Rgo is increased, the charge accumulated in the gate input capacitance Cg becomes difficult to be discharged, the mirror period (time for the depletion layer to extend: time for carriers to be discharged) is extended, and turn-off loss increases. is there.

このように、従来のＩＧＢＴのゲート駆動回路２２では、ゲート抵抗Ｒｇｏを大きくして、ターンオフ時のスパイク電圧ＶＳＰの低減を図るとターンオフ損失が増大してしまう。
この発明の目的は、前記の課題を解決して、誘導負荷回路において、ターンオフ時のターンオフ損失を低減しながらスパイク電圧の低減を図ることができるＩＧＢＴとそれを駆動するゲート駆動回路を提供することにある。 As described above, in the gate drive circuit 22 of the conventional IGBT, if the gate resistance Rgo is increased to reduce the spike voltage VSP at the time of turn-off, the turn-off loss increases.
SUMMARY OF THE INVENTION An object of the present invention is to provide an IGBT capable of reducing the spike voltage while reducing the turn-off loss at turn-off in an inductive load circuit and a gate drive circuit for driving the IGBT in order to solve the above-described problems. It is in.

前記の目的を達成するために、主に誘導負荷回路で用いられるＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）と該ＩＧＢＴを駆動するゲート駆動回路において、前記ＩＧＢＴのコレクタ層のピーク不純物濃度を１×１０１６ｃｍ−３以上とし、前記ＩＧＢＴのゲートと直結する前記ゲート駆動回路のゲート抵抗Ｒｇの抵抗値と前記ＩＧＢＴのゲート入力容量Ｃｇの積（時定数）が５００ｎｓ以上であるＩＧＢＴを駆動するゲート駆動回路とする。 In order to achieve the above object, in an IGBT (insulated gate bipolar transistor) mainly used in an inductive load circuit and a gate driving circuit for driving the IGBT, the peak impurity concentration of the collector layer of the IGBT is set to 1 × 10 16. cm -3 or more and then, the gate drive circuit product of the gate input capacitance Cg of the resistance value and the IGBT gate resistor Rg (time constant) to drive the IGBT is more than 500ns of the gate driving circuit is directly connected to the gate of the IGBT And

また、前記ゲート抵抗Ｒｇの抵抗値を、前記ゲート抵抗Ｒｇの抵抗値を増大させるにつれて前記IＧＢＴのコレクタ・エミッタ間に印加されるスパイク電圧ＶＳＰが増大して行く範囲に設定するとよい。
また、前記ＩＧＢＴがプレーナゲート型もしくはトレンチゲート型であるとよい。
また，前記ＩＧＢＴがＮＰＴ（ノン・パンチスルー）型、ＰＴ（パンチスルー）型もしくはＦＳ（フィールドストップド）型のいずれか一つであるとよい。 The resistance value of the gate resistor Rg may be set in a range in which the spike voltage VSP applied between the collector and the emitter of the IGBT increases as the resistance value of the gate resistor Rg increases.
The IGBT may be a planar gate type or a trench gate type.
The IGBT may be one of an NPT (non-punch through) type, a PT (punch through) type, or an FS (field stopped) type.

この発明によれば、不純物濃度が１０１６ｃｍ−３以上のコレクタ層を有するＩＧＢＴを、ゲート抵抗ＲｇとＩＧＢＴのゲート入力容量Ｃｇの積が５００ｎｓ以下となるようなゲート抵抗Ｒｇを有するゲート駆動回路で駆動することで、ＩＧＢＴのターンオフ時のスパイク電圧ＶＳＰを小さくし、且つターンオフ損失の低減を図ることができる。つまり、ＩＧＢＴのターンオフ時のスパイク電圧ＶＳＰとターンオフ損失のトレードオフを改善できる。 According to the present invention, an IGBT having a collector layer with an impurity concentration of 10 16 cm −3 or more has a gate drive circuit having a gate resistance Rg such that the product of the gate resistance Rg and the gate input capacitance Cg of the IGBT is 500 ns or less. By driving with, the spike voltage VSP when the IGBT is turned off can be reduced and the turn-off loss can be reduced. That is, the trade-off between the spike voltage VSP and the turn-off loss when the IGBT is turned off can be improved.

図５のような誘導負荷回路においては、ＩＧＢＴのターンオフにおいて、ＭＯＳＦＥＴと異なり、ゲート抵抗Ｒｇ（図５のＲｇｏに相当する抵抗）が小さい値の範囲で、このゲート抵抗Ｒｇを大きくして行くと、−ｄＩ／ｄｔが増加し、スパイク電圧ＶＳＰが大きくなる抵抗範囲が存在する。以下にさらに詳細に説明する。
図１はＮＰＴ（ノン・パンチスルー）−ＩＧＢＴにおいて、コレクタ層のピーク不純物濃度をパラメータとしてゲート駆動回路のゲート抵抗Ｒｇを変えた時のスパイク電圧ＶＳＰである。図のように、ゲート抵抗Ｒｇの増大とともにスパイク電圧ＶＳＰは増大し、さらにゲート抵抗Ｒｇを大きくするとスパイク電圧ＶＳＰは下がる。この理由は以下のように説明できる。ＩＧＢＴのコレクタ層のピーク不純物濃度は４．０×１０１５ｃｍ−３、１．０×１０１６ｃｍ−３、３．９×１０１６ｃｍ−３、２．０×１０１７ｃｍ−３である。 In the inductive load circuit as shown in FIG. 5, when the IGBT is turned off, unlike the MOSFET, the gate resistance Rg (resistance corresponding to Rgo in FIG. 5) is increased within a range of a small value. , -DI / dt increases, and there is a resistance range in which the spike voltage VSP increases. This will be described in more detail below.
FIG. 1 shows a spike voltage VSP when the gate resistance Rg of the gate driving circuit is changed using the peak impurity concentration of the collector layer as a parameter in NPT (non-punch through) -IGBT. As shown in the figure, the spike voltage VSP increases as the gate resistance Rg increases, and the spike voltage VSP decreases as the gate resistance Rg is further increased. The reason for this can be explained as follows. The peak impurity concentration of the collector layer of the IGBT is 4.0 × 10 15 cm −3 , 1.0 × 10 16 cm −3 , 3.9 × 10 16 cm −3 , and 2.0 × 10 17 cm −3 . .

図１において、ゲート抵抗Ｒｇが比較的小さなＡの領域は、ＩＧＢＴの遮断電流は少数キャリアの再結合と空乏層の拡張によって吐き出されるキャリア量が支配的であるため、ゲート抵抗Ｒｇを大きくしてもターンオフ時の−ｄＩ／ｄｔは小さくならない。このキャリア量は、コレクタ層からドリフト層へのキャリアの注入効率に依存し、コレクタ層の不純物濃度を高くすると注入効率が大きくなり、ドリフト層に注入されるホール量が多くなる。   In FIG. 1, in the region A having a relatively small gate resistance Rg, the gate current Rg is increased because the IGBT cutoff current is dominated by the amount of carriers discharged by minority carrier recombination and depletion layer expansion. However, -dI / dt at turn-off does not become small. The amount of carriers depends on the efficiency of carrier injection from the collector layer to the drift layer. Increasing the impurity concentration of the collector layer increases the injection efficiency and increases the amount of holes injected into the drift layer.

逆に、このＡの領域では、ゲート抵抗Ｒｇを大きくすると、ターンオフのタイミングが遅くなるため（ストレージ期間が長くなるため）、少数キャリアの再結合によってドリフト層内部に蓄えられているキャリア量が少なくなり、その結果、ターンオフ時の−ｄＩ／ｄｔが大きくなってスパイク電圧ＶＳＰは増大する。
ゲート抵抗Ｒｇが比較的大きなＢの領域では、表面のＭＯＳＦＥＴを介する電流（チャネルを介して流れる電流）が支配的になるため、ゲート抵抗Ｒｇの増大とともにゲート電圧が緩やかに低下するので、ターンオフ時の−ｄＩ／ｄｔは小さくなり、その結果、スパイク電圧ＶＳＰは減少に転じる。このＢの領域のＲｇの抵抗値が従来のゲート抵抗Ｒｇｏの抵抗値に相当する。 On the contrary, in the region A, if the gate resistance Rg is increased, the turn-off timing is delayed (the storage period becomes longer), so that the amount of carriers stored in the drift layer due to recombination of minority carriers is small. As a result, -dI / dt at turn-off increases and the spike voltage VSP increases.
In the region B where the gate resistance Rg is relatively large, the current through the surface MOSFET (current flowing through the channel) becomes dominant, so that the gate voltage gradually decreases as the gate resistance Rg increases. -DI / dt becomes smaller, and as a result, the spike voltage VSP starts to decrease. The resistance value of Rg in the region B corresponds to the resistance value of the conventional gate resistance Rgo.

つまり、Ｂの領域の大きなゲート抵抗ＲｇからＡの領域の小さなゲート抵抗Ｒｇに向って抵抗値を小さくしてスパイク電圧ＶＳＰを測定すると、スパイク電圧ＶＳＰがＡ領域で極大値を持ち、この極大値から減少に転ずる。このＡの領域のスパイク電圧ＶＳＰを小さくできるゲート抵抗Ｒｇとすることで、ターンオフ損失も低減できる。
また、Ａの領域ではコレクタ層のホールの注入が支配的になるので、この注入を大きくすればターンオフ時の−ｄＩ／ｄｔを小さくできるので、スパイク電圧を小さくできる。 That is, when the spike voltage VSP is measured by decreasing the resistance value from the large gate resistance Rg in the region B to the small gate resistance Rg in the region A, the spike voltage VSP has a maximum value in the region A. To decrease. By using the gate resistance Rg that can reduce the spike voltage VSP in the region A, the turn-off loss can also be reduced.
In addition, since the hole injection in the collector layer becomes dominant in the region A, if this injection is increased, −dI / dt at the turn-off time can be reduced, so that the spike voltage can be reduced.

したがって、コレクタ層のピーク不純物濃度を高くして、コレクタ層からのホールの注入を大きくすると、ゲート抵抗Ｒｇに関係なく、ターンオフ時の−ｄＩ／ｄｔはドリフト層内部に蓄積された少数キャリアの再結合によって決まる値に小さくできる。そのため、ゲート抵抗Ｒｇを小さく設定しミラー期間を短縮することで、ターンオフ損失を小さくすることができる。   Therefore, when the peak impurity concentration of the collector layer is increased and the hole injection from the collector layer is increased, −dI / dt at the time of turn-off is the resumption of minority carriers accumulated in the drift layer regardless of the gate resistance Rg. It can be reduced to a value determined by coupling. Therefore, the turn-off loss can be reduced by setting the gate resistance Rg small and shortening the mirror period.

本発明は、ホールの注入効率に関係するＩＧＢＴのコレクタ層の不純物濃度と、ゲート抵抗Ｒｇをそれぞれ所定の範囲に定めて、スパイク電圧ＶＳＰとターンオフ損失のトレードオフを改善することである。
発明の実施の形態を以下の実施例にて説明する。 The present invention is to improve the trade-off between the spike voltage VSP and the turn-off loss by setting the impurity concentration of the collector layer of the IGBT related to the hole injection efficiency and the gate resistance Rg within a predetermined range.
Embodiments of the invention will be described in the following examples.

図２は、この発明の一実施例のＩＧＢＴとそれを駆動するゲート駆動回路図である。この図は、図５のＫ部に相当する。
ＩＧＢＴ１のゲートはゲート駆動回路２のゲート抵抗Ｒｇと接続し、ＩＧＢＴ１のエミッタとゲート駆動回路２の低電位側と接続する。ゲート駆動回路２はゲート駆動ユニット３とゲート抵抗Ｒｇで構成され、ゲート駆動ユニット３内には図示しないゲート駆動用の低電圧電源が組み込まれている。 FIG. 2 is a diagram showing an IGBT according to one embodiment of the present invention and a gate driving circuit for driving the IGBT. This figure corresponds to the portion K in FIG.
The gate of the IGBT 1 is connected to the gate resistance Rg of the gate drive circuit 2, and is connected to the emitter of the IGBT 1 and the low potential side of the gate drive circuit 2. The gate drive circuit 2 includes a gate drive unit 3 and a gate resistor Rg, and a low voltage power source for driving a gate (not shown) is incorporated in the gate drive unit 3.

前記のゲート抵抗ＲｇとＩＧＢＴ１のゲート入力容量Ｃｇの積である時定数を５００ｎｓ以下とし、ＩＧＢＴ１のコレクタ層のピーク不純物濃度を１×１０１６ｃｍ−３以上とすることで、スパイク電圧を小さくし、且つ、ターンオフ損失の低減を図ることができる。ゲート入力容量Ｃｇはゲート・エミッタ間容量Ｃ１とゲート・コレクタ間容量Ｃ２を合わせた容量である。 The time constant, which is the product of the gate resistance Rg and the gate input capacitance Cg of the IGBT 1, is set to 500 ns or less, and the peak impurity concentration of the collector layer of the IGBT 1 is set to 1 × 10 16 cm −3 or more, thereby reducing the spike voltage. In addition, the turn-off loss can be reduced. The gate input capacitance Cg is a total capacitance of the gate-emitter capacitance C1 and the gate-collector capacitance C2.

また、図４で示すように、コレクタ層のピーク不純物濃度が１×１０１６ｃｍ−３の場合のようにスパイク電圧のピークが５００ｎｓ以下に位置する場合（２５０ｎｓ付近）は、スパイク電圧がピークとなる時定数を最大の値（２５０ｎｓ）とし、これより小さな時定数にすると、時定数を５００ｎｓに設定した場合よりスパイク電圧とターンオフ損失が改善されてさらに好ましくなる。 As shown in FIG. 4, when the peak impurity concentration of the collector layer is 1 × 10 16 cm −3 and the peak of the spike voltage is located below 500 ns (near 250 ns), the spike voltage reaches the peak. If the time constant is set to the maximum value (250 ns) and a time constant smaller than this is set, the spike voltage and the turn-off loss are further improved as compared with the case where the time constant is set to 500 ns.

また、素子としては、ゲート構造がプレーナゲート型もしくはトレンチゲート型であり、素子構造がＮＰＴ（ノン・パンチスルー）型、ＰＴ（パンチスルー）型もしくはＦＳ（フィールドストップド）型の各ＩＧＢＴに適用できる。
図３は、ゲート抵抗Ｒｇおよびコレクタ層のピーク不純物濃度をパラメータとして、スパイク電圧とターンオフ損失のトレードオフを示した図である。ゲート抵抗Ｒｇを３３Ω（時定数５００ｎｓに相当する）から６Ω（９０ｎｓに相当する）に変更することにより、このトレードオフが改善していることが分かる。コレクタ層のピーク不純物濃度は４．０×１０１５ｃｍ−３、１．０×１０１６ｃｍ−３、３．９×１０１６ｃｍ−３、２．０×１０１７ｃｍ−３である。 In addition, as a device, the gate structure is a planar gate type or a trench gate type, and the device structure is applied to each IGBT of NPT (non-punch through) type, PT (punch through) type, or FS (field stopped) type. it can.
FIG. 3 is a diagram showing a trade-off between spike voltage and turn-off loss using the gate resistance Rg and the peak impurity concentration of the collector layer as parameters. It can be seen that the trade-off is improved by changing the gate resistance Rg from 33Ω (corresponding to a time constant of 500 ns) to 6Ω (corresponding to 90 ns). The peak impurity concentration of the collector layer is 4.0 × 10 15 cm −3 , 1.0 × 10 16 cm −3 , 3.9 × 10 16 cm −3 , and 2.0 × 10 17 cm −3 .

図４は、ゲート抵抗ＲｇとＩＧＢＴのゲート入力容量Ｃｇ（ＶＣＥ（コレクタ・エミッタ間電圧）＝０Ｖの場合の値）の積（時定数）で表わした時定数とスパイク電圧の関係を示す図である。パラメータはコレクタ層のピーク不純物濃度であり、そのピーク不純物濃度は４．０×１０１５ｃｍ−３、１．０×１０１６ｃｍ−３、３．９×１０１６ｃｍ−３、２．０×１０１７ｃｍ−３である。 FIG. 4 is a diagram showing the relationship between the time constant represented by the product (time constant) of the gate resistance Rg and the gate input capacitance Cg of the IGBT (value when VCE (collector-emitter voltage) = 0V) and the spike voltage. is there. The parameter is the peak impurity concentration of the collector layer, and the peak impurity concentration is 4.0 × 10 15 cm −3 , 1.0 × 10 16 cm −3 , 3.9 × 10 16 cm −3 , 2.0 ×. 10 17 cm −3 .

図４からコレクタ層のピーク不純物濃度を１×１０１６ｃｍ−３以上にして、ゲート抵抗Ｒｇと入力容量Ｃｇとの積を５００ｎｓｅｃ以下にすると、スパイク電圧を小さくできる。
尚、数１００Ｖ以上、数１０Ａ以上の電圧・電流定格を有するＩＧＢＴでは、半導体チップのゲート抵抗ｒｇの抵抗値は１Ω程度以下であり、ゲート駆動回路のゲート抵抗Ｒｇに比べて無視できる大きさである。そのため、図４で示すスパイク電圧はゲート抵抗ｒｇには殆ど依存しない。 From FIG. 4, the spike voltage can be reduced by setting the peak impurity concentration of the collector layer to 1 × 10 16 cm −3 or more and the product of the gate resistance Rg and the input capacitance Cg to 500 nsec or less.
In an IGBT having a voltage / current rating of several hundred volts or more and several tens of amperes or more, the resistance value of the gate resistance rg of the semiconductor chip is about 1Ω or less, which is negligible compared to the gate resistance Rg of the gate drive circuit. is there. Therefore, the spike voltage shown in FIG. 4 hardly depends on the gate resistance rg.

ＮＰＴ（ノン・パンチスルー）−ＩＧＢＴにおいて、コレクタ層のピーク不純物濃度をパラメータとしてゲート駆動回路のゲート抵抗Ｒｇを変えた時のスパイク電圧ＶＳＰを示した図A diagram showing a spike voltage VSP when the gate resistance Rg of the gate drive circuit is changed using the peak impurity concentration of the collector layer as a parameter in NPT (non-punch through) -IGBT. この発明の一実施例のＩＧＢＴとそれを駆動するゲート駆動回路図IGBT of one embodiment of the present invention and a gate drive circuit diagram for driving the IGBT ゲート抵抗Ｒｇおよびコレクタ層のピーク不純物濃度をパラメータとして、スパイク電圧とターンオフ損失のトレードオフを示した図Figure showing the trade-off between spike voltage and turn-off loss using the gate resistance Rg and the peak impurity concentration of the collector layer as parameters ゲート抵抗ＲｇとＩＧＢＴのゲート入力容量Ｃｇ（ＶＣＥ（コレクタ・エミッタ間電圧）＝０Ｖの場合の値）の積（時定数）で表わした時定数とスパイク電圧の関係を示す図The figure which shows the relationship between the time constant represented by the product (time constant) of the gate resistance Rg and the gate input capacitance Cg of IGBT (value in case of VCE (collector-emitter voltage) = 0V) and the spike voltage. 誘導負荷回路の一例を示す回路図Circuit diagram showing an example of an inductive load circuit 図５の回路の動作波形図Operation waveform diagram of the circuit of FIG. ＩＧＢＴの構造を示す断面図Sectional view showing structure of IGBT

符号の説明Explanation of symbols

１ ＩＧＢＴ
２ ゲート駆動回路
３ ゲート駆動ユニット
Ｒｇ ゲート抵抗（外付け）
ｒｇ ゲート抵抗（半導体チップ内）
Ｃｇ ゲート入力容量 1 IGBT
2 Gate drive circuit 3 Gate drive unit Rg Gate resistance (external)
rg Gate resistance (in semiconductor chip)
Cg Gate input capacitance

Claims (4)

ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）と該ＩＧＢＴを駆動するゲート駆動回路において、前記ＩＧＢＴのコレクタ層のピーク不純物濃度が１×１０１６ｃｍ−３以上であり、前記ＩＧＢＴのゲートと直結する前記ゲート駆動回路のゲート抵抗の抵抗値と前記ＩＧＢＴのゲート入力容量の積（時定数）が５００ｎｓ以下であることを特徴とするＩＧＢＴとそれを駆動するゲート駆動回路。 In the gate drive circuit for driving an IGBT (insulated gate bipolar transistor) and the IGBT, the gate drive having a peak impurity concentration in the collector layer of the IGBT of 1 × 10 16 cm −3 or more and directly connected to the gate of the IGBT An IGBT and a gate driving circuit for driving the IGBT, wherein a product (time constant) of a resistance value of a gate resistance of the circuit and a gate input capacitance of the IGBT is 500 ns or less. 前記ゲート抵抗の抵抗値を、前記ゲート抵抗の抵抗値を増大させるにつれて前記IＧＢＴのコレクタ・エミッタ間に印加されるスパイク電圧が増大して行く範囲に設定することを特徴とする請求項１に記載のＩＧＢＴとそれを駆動するゲート駆動回路。 The resistance value of the gate resistance is set to a range in which a spike voltage applied between the collector and the emitter of the IGBT is increased as the resistance value of the gate resistance is increased. IGBT and a gate drive circuit for driving the IGBT. 前記ＩＧＢＴがプレーナゲート型もしくはトレンチゲート型であることを特徴とする請求項１または２に記載のＩＧＢＴとそれを駆動するゲート駆動回路。 3. The IGBT according to claim 1, wherein the IGBT is a planar gate type or a trench gate type, and a gate driving circuit for driving the IGBT. 前記ＩＧＢＴがＮＰＴ（ノン・パンチスルー）型、ＰＴ（パンチスルー）型もしくはＦＳ（フィールドストップド）型のいずれか一つであることを特徴とする請求項３に記載のＩＧＢＴとそれを駆動するゲート駆動回路。
The IGBT according to claim 3, wherein the IGBT is one of an NPT (non-punch through) type, a PT (punch through) type, and an FS (field stopped) type. Gate drive circuit.
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