JPH03155677A - Mosfet of conductivity modulation type - Google Patents

Abstract

PURPOSE:To improve largely a switching speed of a device and to reduce a current gain of a parasitic bipolar transistor formed on a substrate in order to prevent a latching phenomenon by contacting an electrode forming a Schottky barrier junction with an n type semiconductor substrate on the reverse side of an insulation gate part of a longitudinal type DMOS structure. CONSTITUTION:In this metal-collector IGBT, a p base region 3, an n<+> source region 4 and a p<+> well 5 are formed on the surface part of an n<-> high resistance region 2, and on the surface of region 2, a gate oxide film 6 and a polycrystalline silicon gate electrode 7 are provided. Also, a metal electrode 10 for joining directly a Schottky barrier to the high resistance region 2 is contacted with the region 2 on the reverse side of the region 2. As the used barrier metal, the one which has a suitable barrier height phib by the necessary implanting quantity of a minority carrier is selected. Therefore, the trade-off relation between an ON voltage and a switching time in the IGBT can be improved largely. Also, since a parasitic pnp bipolar transistor is changed from a pn junction bipolar transistor into a bipolar transistor of a Schottky junction emitter type, its current gain alpha is reduced largely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conductivity modulated MO3FET used as a power switching element.

[Conventional technology]

In recent years, the demand for power switching elements has been expanding to higher speed, higher voltage resistance, and higher power devices. Against this background, high-power MO3FETs (insulated high-power MO3FETs) are showing great growth, mainly for switching power supply applications. On the other hand, conductivity modulated MOSFETs (!GBTs) are used as switching devices with higher breakdown voltage, higher power, and higher speed than conventional bipolar transistors, and their main applications are expanding, especially to inverter control applications, and their field of application continues to expand. I am trying to do.

FIG. 2 shows the basic structure of an n-channel IGBT, which can be said to be replaced with an n+ region p+ collector region 1 which becomes the drain region of a high power MO3FET called a normal vertical DMO3. n- which is in contact with this p middle region
A p base region 3 is selectively formed on the surface of the drift region 20, and two n+
A source region 4 is formed in the center, and a p well 5 deeper than the p region is formed. The p base region 3o sandwiched between the exposed portions of the n+ source region 4 and the n− drift region 2 is
A gate electrode 7 connected to a gate terminal G via an insulating film 6 is provided to form a channel. tt
In the contact hole opened in the AIR film 6, the emitter electrode 8 connected to the emitter terminal E is connected to the p-well 5.
and in contact with n+ source region 4. Also, p,′
A collector electrode 9 connected to a collector terminal C is in contact with the collector region 1 .

The emitter terminal E of this IGET is grounded, and the gate terminal G
When a positive voltage is applied to the collector terminal C, the surface of the p base layer 3 under the gate electrode 7 is inverted to form an electron channel, based on the same principle as in a high-power MO3FET. Therefore, the n-region 2 is connected to the ground potential,
A hole current is injected from the p+ collector region 1. In other words, minority carriers (holes) are injected into the n-drift region 2, which is a high resistance layer region. This injection of minority carriers increases the concentration of electrons, which are majority carriers, in order to satisfy the charge neutrality condition, and the resistance of this n-region 2 is significantly reduced, resulting in a device with sufficiently low on-resistance due to the so-called conductivity modulation effect. becomes.

[Problem to be solved by the invention]

As shown in FIG. 3, the emitter current is L
= lh+ Ixos, p base region 3° n-drift region 2. pnp consisting of pゝcollector region 1
) The current gain of the run lister 21 is αPIIP.
h (hole current) changes, that is, +GBT current changes. I gos is the electron current. FIG. 4 shows a typical switching waveform at turn-off, and it can be seen that there are first and second phases 41 and 42. In the first period 41, the channel disappears and the electron current becomes 0, so the current instantly decreases by that amount. In the next second period, pn-p+
The current flowing due to the action of the bipolar transistor decreases in the oven base state due to recombination annihilation due to carrier lifetime τ. Therefore, this region is determined by the hole current injection level or carrier lifetime τ. In order to make the device compatible with higher frequencies, conventionally, a buffer n1 layer was formed between the p substrate and the n high resistance region to control the hole current injection level (I EEE, I
EDM Technical Digest, 4.
3 (1983) pp. 79 = 82), or by controlling the concentration of the p+ substrate, or by applying lifetime control processes such as electron beam irradiation or heavy metal diffusion to reduce the carrier lifetime τ (I EEE, Trans, 1E1e
ctron, E Law 31 (1984) pp, 179
0 to 1795) was performed. However, in the conventional methods, there has been a strong trade-off relationship with the on-voltage. It is believed that this trade-off can be greatly improved if a method for extracting carriers to the p'' substrate region or another method can be applied.

Now, there is one even bigger problem with IGBTs. As shown in FIG. 3, in addition to the pnp parasitic bipolar transistor 21, the n+ source region 4. p base region 3. Parasitic np consisting of n-drift region 2
An n bipolar transistor 22 is present. These parasitic bipolar transistors each have a current gain αPII
It has P and α, -, resulting in an npnp cyrisk structure.

When the sum of the respective current gains is equal to 1 or greater than l, i.e. aMPII+α1. .

≧1, a phenomenon in which the thyristor turns on, that is, latching occurs. -When latching occurs, I
The GBT loses current gate control and eventually breaks down.

This sudden destructive phenomenon, latching failure, is one of the important issues to be prevented, especially in inverter control applications. Conventionally,
In order to prevent this latching phenomenon, in order to prevent the activation of each parasitic transistor, the base resistance of the p+ well 5 is reduced (I E E E, Trans, Mi 1
ectron, Devicestin-32 (+98
5) p, 2554), reduction of majority carriers in the p-base junction or reduction of current concentrated close to the emitter-base junction of the device (US Patent 4,8
09,045) have been taken. However, it has not yet reached the level of destruction (load short-circuit mode) of the conventional bipolar high-power transistor. It is believed that the latching phenomenon can be greatly improved if the current gain of any of the bipolar transistors can be significantly reduced.

The purpose of the present invention is to solve the above problems and significantly improve the switching speed of the device, especially the trade-off between fall time and on-voltage, as well as to prevent parasitic bipolar transistors formed in the substrate to prevent latching phenomena. An object of the present invention is to provide an IGBT with a reduced current gain α.

[Means to solve the problem]

In order to achieve the above object, the present invention has a high resistance layer on at least one side of an n-type semiconductor layer plate, and a p-type base region is selectively formed on the surface of the high resistance layer. An n-type source region is selectively formed so that a channel region remains between the end of the surface portion of the base region and the exposed portion of the substrate, and a gate electrode is formed on the channel region via a gate insulating film. , and an electrode forming a Schottky barrier junction with the substrate is in contact with the other surface of the semiconductor substrate.

[Effect]

A Schottky diode (SBD) is formed by an electrode and a semiconductor substrate in contact on the opposite side of the insulated gate structure. In an n-type SBD, the main carriers during forward bias are thermally emitted electrons. However, the SBD current component also includes a minority carrier current due to hole injection from the metal side to the semiconductor side. 1lhod
Author: “MeLaiSe+n1conductor Co
ntacts'' (1978), where n is the electron density in the intrinsic state.

When the donor degree is N, P = n+'/N, +, where q is the absolute value of electron charge, Dh is the diffusion constant of holes in the bulk semiconductor, and L is the thickness of the extensive region. .

Then, the ratio of the minority carrier (hole) current jh to the total current J=Jh+J of the SBD is the hole injection rate γh, which is as follows. Here, 80 is the effective Richardson constant.

In a general SBD, φbzO, 8eV, N
d-=10"cm-', L; 5 Xl0-'am
at rh>10-', the hole injection is generally negligible. This is why SBDs are called majority carrier devices. However, from the above theory, it can be seen that rh can be increased to 10-2 or more by increasing the barrier height φ or decreasing N1 degrees. In other words, injection of minority carriers can be realized using a Schottky barrier electrode. If minority carrier injection is possible, conductivity modulation occurs in the n-high resistance region and the on-state voltage can be reduced. The injection level of minority carriers can be controlled by adjusting the barrier height φb and the degree Nda. It is also known that when the total current J flowing through the Schottky junction increases, rh also increases.
A large amount of minority carriers can be expected to be injected along with current.

On the other hand, considering the switch-off time, the holes and electron carriers accumulated in the n-high resistance region are
If so, it is equivalent to the off state during the base oven, and is mostly limited by the reduction by carrier lifetime τ. However, in the Schottky junction IGBT of the present invention,
When the switch is turned off, electrons in the n-high resistance region are easily drawn into the drain electrode. Therefore, a faster switching off time can be achieved. Since there is no need to reduce the carrier life r in the n-high resistance region in the conventional '(7) IGBT, and the Schottky barrier voltage drop is smaller than the PN junction diffusion potential, the on-voltage and switching time can be reduced. The trade-off relationship can be significantly improved. Furthermore, regarding the prevention of the latching phenomenon, which is another major issue, as the mechanism was explained above, in the present invention, one parasitic bipolar transistor has a pn-p bipolar transistor structure in which the Schottky junction is the emitter. The Schottky junction emitter pn-p bipolar transistor has its current gain α much lower than the pn junction pn'''p bipolar transistor, which can largely avoid the device from latching phenomena.

〔Example〕

Hereinafter, an embodiment of the metal collector IGBT of the present invention will be described with reference to a diagram in which parts common to those in FIG. 2 are given the same reference numerals. In the embodiment shown in FIG.
A p base region 3 similar to that shown in FIG. 2 is formed on the surface of the high resistance region 20.
, an n2 source region 4 and a p+ well 5 are formed, and a gate oxide film 6 and a polycrystalline silicon gate electrode 7 are provided on the surface. On the back side, a metal electrode 10 for Schottky barrier bonding is in direct contact with the high resistance region 2,
A solderable fJNi-Au layer or a Ni-Ag layer is coated thereon (not shown).

FIG. 5 shows another embodiment in which, in order to achieve a breakdown voltage in the narrow n-high resistance region 2, an impurity of 5×101' to 10 C11-3 is added under the n-high resistance region at a higher concentration. An n region 11 having a high concentration is formed, and a Schottky barrier metal film 10 is deposited on the n region 11 as a collector electrode. Pd and Al are used as barrier metals.

pt, pt silicide, ^u, Mo, Mo silicide, Cr, Cr silicide, Ni, Ni silicide,
Ti, Ti silicide, etc. are used. A barrier metal having an appropriate barrier height φ is selected depending on the required injection amount of minority carriers. For example, when the Schottky junction total current is 100 A/cd, the injection ratio γ is 1O
- Make sure it is 3 or more. Note that the gate electrode 7 is connected to the gate terminal G via a conductor 71 drawn out through the opening of the emitter electrode 8.

FIG. 6 shows yet another embodiment. This is applied when it is desired to increase the amount of holes injected.The collector part consists of a Schottky barrier contact part 20 and a p'' collector part 1, and the minority carrier injection ratio is determined by this area ratio. It is also possible to control the amount of carriers accumulated in the n-region 2.

Such a metal collector IGET is manufactured by the following manufacturing process. To improve IGBT performance, it is desirable to use a minimum n-high resistance width to obtain the required breakdown voltage. The impurity concentration of n-region 2 is 1014
0Ia-3, the n-region width is approximately 100-15
A thickness of about 0 μm is sufficient. However, it is impractical to perform the manufacturing process using wafers of such thickness. This is because handling extremely thin and fragile wafers from the beginning of the wafer process involves various problems. Therefore, the following manufacturing process is performed. First, n
Type.

F with impurity concentration 8X1013am-ζ crystal axis <100>
Prepare a Z neutron irradiation wafer. Thickness approx. 2H to 25(l)
An n-type diffusion region with a surface impurity concentration of 10"cm-3 is formed at a depth of about 50 μm on an Alm wafer by ion implantation.Then, the wafer is bonded to a CZ wafer with a thickness of about 300 μm through SiO, ll. This creates a wafer with a thickness of about 500 μm.A field oxide film is formed on the FZ wafer surface of this wafer, and a p+ well 5 with a depth of about 8 μm, which will become a part of the base diffusion layer, is formed. After this, a gate oxide film 6 with a thickness of 800 μm is formed, and a gate electrode 7 made of a polycrystalline silicon film with a thickness of 10,000 μm is formed thereon, and the p-base is diffused to a depth of about 5 μm using the electrode film as a mask. Region 3 is formed, and then an n'' source diffusion region 4 is formed to a depth of 0.25 μm from the same mask. A channel region 30 is now formed under the gate electrode 7.

To explain the case of the embodiment shown in FIG.
A VD oxide film is grown, a contact hole is made in it, and a ^1-Si alloy is deposited to form an emitter electrode 8. A gate connection conductor 71 is formed. Next, from the back side, 300~
The 350 μm surface of the FZ wafer is polished until the surface impurity concentration (approximately 10" am-3) is removed. After mirror-finishing this back surface, p
The process is completed by forming a film 10 of T or Pt silicide.

〔Effect of the invention〕

According to the present invention, by bringing an electrode forming a Schottky barrier junction into contact with an n-type semiconductor substrate on the side opposite to the insulated gate portion of the vertical DMO3 structure, and by selecting the barrier height of the barrier metal, It has become possible to significantly improve the trade-off relationship between on-voltage and switching time in IGBTs. Further, by changing the parasitic pnp bipolar transistor from a pn junction bipolar transistor to a Schottky junction emitter bipolar transistor, its current gain α is significantly lowered, and an IGBT in which latching phenomenon is less likely to occur can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an IGBT according to an embodiment of the present invention.
Fig. 2 is a sectional view of the main parts of a conventional IGBT, Fig. 3 is a sectional view showing the current flow and equivalent circuit in the IGET shown in Fig. 2, and Fig. 4 is a diagram of the attenuation waveform of the collector current at turn-off. 5 and 6 are sectional views of main parts of IGBTs according to different embodiments of the present invention, respectively. 1.p'' collector region, 2 high resistance drift region, 3
p base region, 30 channel region, 4n0 source region, 6 insulating film, 7 gate electrode, 8 mitsuta electrode, 10
Schottky barrier metal film. Figure 2 Figure 1 Figure 3

Claims (1)

[Claims] 1) A high-resistance layer is provided on at least one side of an n-type semiconductor substrate, a p-type base region is selectively formed on the surface of this high-resistance layer, and a substrate is formed on an end of the surface of this base region. An n-type source region is selectively formed so that a channel region remains between the exposed portion of the semiconductor substrate, a gate electrode is provided on the channel region via a gate insulating film, and a substrate and a substrate are provided on the other side of the semiconductor substrate. A conductivity modulated MOSFET characterized in that electrodes forming a Schottky barrier junction are in contact with each other.