GB2286484A - Conductivity modulated semiconductor device - Google Patents
Conductivity modulated semiconductor device Download PDFInfo
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- GB2286484A GB2286484A GB9402639A GB9402639A GB2286484A GB 2286484 A GB2286484 A GB 2286484A GB 9402639 A GB9402639 A GB 9402639A GB 9402639 A GB9402639 A GB 9402639A GB 2286484 A GB2286484 A GB 2286484A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000002347 injection Methods 0.000 claims abstract description 73
- 239000007924 injection Substances 0.000 claims abstract description 73
- 239000010410 layer Substances 0.000 claims description 57
- 239000002344 surface layer Substances 0.000 claims description 23
- 238000009413 insulation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 10
- 230000002829 reductive effect Effects 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 abstract description 6
- 229940090044 injection Drugs 0.000 description 62
- 238000010276 construction Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 5
- 230000001939 inductive effect Effects 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
Abstract
To shorten the turn-off time in a bipolar semiconductor device such as an IGBT or thyristor with reduced on-voltage, conductivity modulation is used to reduce switching loss. A minority carrier, which has a conductivity modulation effect, can be supplied from a separately disposed minority carrier injection region (9), and the region (9) can either be connected to or separated from a drain region (8). When a voltage above threshold is applied to a first gate electrode 51 an inversion layer forms below in a base region 3 and electrons are injected from a source 4 into an n-layer 2 and these reach the drain 8. If the voltage on a second gate electrode 53 is high enough, an inversion layer forms below in the minority carrier region 9 thus connecting a source 11 to the drain 8. A short circuit electrode 63 supplies electrons to the source 11 and holes to the region 9, so acting as a converter with holes being injected into the layer 2 from region 9. If the voltage on the second gate 53 is below threshold, the injection stops and minority carriers in the layer 2 are swept to the base 3 and recombine. This allows rapid turn-off from the first gate electrode 51. <IMAGE>
Description
SEMICONDUCTOR DEVICE
The present invention relates to semiconductor devices, and particularly concerns a semiconductor device with a conductivity modulation effect, which can be used as the semiconductor switching element in power converters and power controllers.
Power semiconductor devices, which mainly carry out switching operations in power converters and power controllers, must have a small turn-on voltage drop in order to keep power loss to a minimum, whereas, especially in application fields that require a high blocking voltage, thyristors with a conductivity modulation effect and insulated gate bipolar transistors (hereinafter abbreviated to IGBT) are suitable. To incorporate IGBTs in an integrated circuit, the lateral structure shown in Figure 2 is suitable. In this figure, the IGBTs are built into the surface layer of an n-type epitaxial layer 2 with a high-resistance factor grown on a p- silicon substrate 1 with chips 10 in the integrated circuit by repeating more than twice the unit construction shown normally in a range of Uh, and connected in parallel. This construction Uh is repeated symmetrically in the horizontal direction in the figure. On the left side of the figure, a p-type base region 3 is formed by diffusing impurities from the surface of the n- layer 2, upon which an n+ emitter layer 4 is formed sandwiching a p' contract region 31, while a gate 51 connected to a gate terminal G is disposed on the surface of a part of the p-type base region 3 sandwiched by the n layer 2 and the nt emitter region 4 via a gate oxide film 52. In addition, an emitter electrode 61 connected to a first main terminal T. contacts the emitter region 4 and the contact region 31 at the same time. On the right side of the figure, a p drain region 7 surrounded by an n-type buffer region 21 is formed by diffusing impurities from the surface in the same manner as described above, while a collector electrode 62 connected to a second main terminal
T2 contacts the drain region 7.
In this horizontal type IGBT, the p-type base region 3, the n layer 2 and the p+ drain region 7 constitute one pnp transistor, and this bipolar transistor is turned on and off by controlling the potential of the gate 51 that gives a base current to be injected into the n layer 2 which is the base of the transistor. That is, when positive voltage is applied from the gate terminal G into the gate 51, electrons e which is the majority carrier flow into the n layer 2 from the emitter region 4 via an n-type inversion layer formed on the surface of the p-type base region 3 directly below the gate 51, thereby creating conduction between the main terminals T1 and T2 of the IGBT. Furthermore, because holes h of the minority carrier are injected into the n layer 2 from the p+ drain region 7 via the buffer region 21 by this base current after creating such conduction, its conductivity modulating action reduces the on-voltage between the main terminals T1 and T2 making it, lower than in an ordinary MOSFET. This IGBT may be turned off by stopping the injection of the majority carrier e into the n layer 2 by turning the voltage at the gate 51 off. A depletion layer extends to the n layer 2 after the device is turned off to create a high reverse voltage blocking condition.
A horizontal MOS controlled thyristor (hereinafter referred to as the MCT) is shown in Figure 3, and it can be controlled by a
MOS gate. A p+ emitter region 41 is formed on the surface layer of an n base region 32, which exists on the surface layer of the p-type base region 3. The emitter electrode 61 also contacts the p+ emitter region 41 and the n-type base layer 32, while the gates 51 are disposed on the surface of the n-type base 32 and p-type base 3 regions sandwiched between the n- layer 2 and the p+ emitter region 41, via a gate oxide film 52. Also in this MCT, when a positive voltage is applied from the gate terminal G into the gate 51, electrons flow into the n layer 2 from the n-type base region 32 via the n-type inversion layer formed on the surface of the p-type base region 3 directly below the gate 51, thereby creating a conduction between the main terminals T1 and T2 and causing conductivity modulation as in the case of the IGBT. When the transistor is turned off, a negative voltage is applied to the gate 51. As a result, an n-channel on the surface of the p-type base region 3 is closed, and at the same time, a p-channel is formed on the surface of the n-type base region 32 directly below the gate. As a result, the p-type base region 3 is shorted with the emitter electrode 61 via the p+ emitter region 41, and is turned off.
As described above, the IGBT has an advantage in that it can be turned on and off and can be controlled easily through the insulating gate 51 which has a high input impedance, and when it is on, the on-voltage can be reduced by utilising the conductivity modulation effect in the n layer 2. However, on the other hand, the excessive carrier that contributes to conductivity modulation when the device is on must be swept away to expand the depletion layer during the turning off of the device, which can cause a problem because a lot of time is consumed to remove the carrier, substantially prolonging the turn-off time and as a result, increasing the turn-off loss. This increase in turn-off loss is a major obstacle to the use of the IGBT in a high-frequency circuit that requires high-speed on/off operations. The turn-off loss noticeably Increases especially when driving a inductive load, which generates a counter electromotive force and following extension of the depletion layer during turn-off. The extension of the depletion layer causes the sweeping out of majority carrier that acts as a base current of the PNP transistor and leads to injection of the minority carrier to maintain the current for an inductive load. The constant current and large counter electromotive force simultaneously applied to the device increases the turn-off loss. To improve such turn-off characteristics, minority carrier injected from the drain region 7 into the n- layer 2 during a turn-on operation may be reduced by raising the concentration of impurities in the buffer region 21; however, this action also has its limits because it has a negative effect on the conductivity modulation during operation in the on-state. It may also be possible to shorten the carrier life time to accelerate recombination of the carriers by diffusing heavy metals such as gold and platinum, since these are so-called life-time killers. However, it also has the negative effect of increasing the on-voltage. The problems described above with reference to the IGBT also occur in the case of the MCT.
The purpose of the present invention is to solve these problems by providing a semiconductor device that will improve the turn-off characteristics without adversely affecting the forward-direction characteristics, which are obtained by utilising the conductivity modulation, during the on-state.
In order to achieve the above objective, the present semiconductor device is structured so that one of the main electrodes is formed on the surface of a low-resistance region of the first conductivity type which is itself in contact with a high-resistance region of the first conductivity type, a minority carrier injection region of the second conductivity type is formed, a source region of the first conductivity type is formed on the surface layer of the minority carrier injection region, a gate electrode is disposed via a gate insulation film on the minority carrier injection region at a part sandwiched by an edge close to said main electrode and the source region and an electrode in order to short-circuit the source region and the minority carrier Injection region on the surface. The minority carrier injection region may be formed adjoining the low-resistance region of the first conductivity type, or may be formed at a distance from the low-resistance region of the first conductivity type. It is desirable that base regions of the second conductivity type are formed individually on the surface layer of a high-resistance semiconductor layer, emitter regions of the first conductivity type are formed on the surface layer of the base regions, another gate electrode is disposed via the gate insulation film on the surface layer of the base region at a part sandwiched by the emitter region and said high-resistance layer, while the other main electrode contacts the surfaces of the base region and the emitter region. On the other hand, it is also desirable that the base regions of second conductivity type are formed individually on the surface layer of the high-resistance semiconductor layer of the first conductivity type, base regions of first conductivity type are formed on the surface of the base regions of second conductivity type, emitter regions of the second conductivity type are formed on the surface of the base regions of first conductivity type, another gate electrode is disposed via the gate insulation film on the surface layers of the base regions of the first and second conductivity types at a part sandwiched by the high-resistance semiconductor layer of the first conductivity type and the emitter regions, and the other main electrode contacts the surfaces of the base region of the first conductivity type and the emitter region.
It is also desirable that a punch-through region of the second conductivity type with a depth greater than that of the low-resistance factor region of the first conductivity type, but smaller than that of the minority carrier injection region, is formed beneath the low-resistance factor region of the first conductivity type. In these cases, the minority carrier injection region and the base region contacting the other electrode may be formed on the surface layer of the same main surface as the main surface on which a low-resistance region of the first conductivity type, which contacts one of the main electrodes of the high-resistance factor semiconductor layer of the first conductivity type, is formed.
Alternatively, said minority carrier injection region and base region may be formed on the surface layer of the main surface, which is different from the main surface mentioned above.
For the avoidance of doubt, it is to be understood that the first conductivity type referred to above may be either n-type or p-type, and the second conductivity type referred to above will then be either p-type or n-type, respectively.
The region in which the minority carrier is injected is separately disposed so that the injection of the minority carrier can be controlled by the voltage applied to a minority carrier controlling gate electrode when current caused by the minority carrier flows into the high-resistance factor semiconductor layer.
This construction allows both the minority carrier and the majority carrier to be injected in large quantities during an on-state period, so that the conductivity modulation effect reduces the on-voltage, without impeding the conductivity modulation effect, by stopping the minority carrier injection simultaneously at or immediately before the turn-off operation, thereby also reducing the switching loss.
Therefore, if such a minority carrier injection region is disposed (in place of a drain region with a conductivity type that is different from that of the high-resistance factor semiconductor layer disposed to achieve conductivity modulation effect in the prior art) an IGBT or an MCT that operates with a low on-voltage and causes a smaller switching loss can be obtained.
Embodiments of the present invention are explained below with reference to the drawings, in which parts common to Figures 2 and 3 are indicated by the same reference numbers.
In the drawings:
Figure 1 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to a first embodiment of the present invention;
Figure 2 is a cross section of a horizontal IGBT;
Figure 3 is a cross section of a horizontal MCT;
Figure 4 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to another embodiment of the present invention;
Figure 5 shows current and voltage characteristic curve charts for the semiconductor devices shown in Figures 1 and 4;
Figure 6 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to another embodiment of the present invention;
Figure 7 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to another embodiment of the present invention;
Figure 8 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to another embodiment of the present invention; and
Figure 9 is a cross section of a semiconductor device having the functions of a horizontal IGBT according to another embodiment of the present invention.
In the first embodiment shown in Figure 1, an n+ drain region 8 with a collector electrode 62 in contact therewith (as in the case of an ordinary horizontal MOSFET) is formed in place of the p' drain region 7 of the lateral IGBT shown in Figure 2 and at the same time, a p-region 9 that injects the minority carrier, that is the hole h, into the n layer 2 is formed near the p-type base region 3 in the above n drain region 8. On the surface layer of the minority carrier injection region 9, a p contact region 12 and an n+ source region 11 are formed, while on the surface of the minority carrier injection region 9 situated between the n+ source region 11 and the n+ drain region 8, a gate oxide film 54 is disposed on which is disposed a second gate electrode 53, which is connected to a second terminal G2. The n' source region 11 is connected to the minority carrier injection region 9 through the p+ contact region 12 by a short-circuit electrode 63 in order to make a short circuit. Moreover, an n-buffer region 13 is formed at the interface of the minority carrier injection region 9 and the n layer 2 to prevent punch-through.
Next, the operations of this element are explained. First, when a voltage larger than the threshold voltage at the gate is applied to the first gate electrode 51 connected to the gate terminal
G1, an inversion layer is formed on the surface layer of the p-type base region 3 directly below the first gate, and electrons are injected from the n+ source region 4 into the n layer 2 via this inversion layer. The injected electrons are attracted by the positive potential applied to T2, and eventually reach the drain region 8. Then, if a potential higher than the threshold value has been applied to the second gate electrode 53, an inversion layer is formed on the surface of the minority carrier region 9 directly below the second gate, by which the n+ source region 11 is connected to the drain region 8. This causes the electrons in the n source region 11 to be attracted by the positive potential applied to T2, and eventually to reach the drain region 8. While the electrons in the source region 11 are supplied by a short-circuit electrode 63, this short-circuit electrode 63 maintains neutrality by simultaneously supplying holes in the minority carrier injection region 9. In other words, the short-circuit electrode 63 can perform electron-hole conversion. As a result, the holes h of the minority carrier are injected into the n layer 2 from the minority carrier injection region 9, and conductivity can be modulated as in the lateral IGBT. On the other hand, if the potential at the second gate
G2 drops below the threshold voltage, the inversion layer directly below the second gate vanishes, and the Injection from the minority carrier Injection region 9 ceases because the n+ source region 11 enters a floating condition relative to the drain region 8. In this case, the minority carrier stored in the n layer 2 as a result of the conductivity modulation is swept away in the direction of the p-type base region 3, and finally vanishes as a result of a recombination of carriers. If the first gate is turned off when excessive carriers have vanished or almost vanished, this element can be turned off at a very high speed, as in the case of a MOSFET.
Other than the method described above which turns the first and second gates off at different times, it is also possible to turn them off simultaneously. Although the turn-off speed is slightly reduced in this case because of the presence of excessive carriers, switching loss can also be reduced because it is possible to prevent injection of the minority carrier by sweeping out of the electrons associated with growth of the depletion layer after the first gate has been turned off, as occurs when an inductive load is turned off. The control circuit can be simplified in such a case because the gates are turned off simultaneously.
Figure 4 shows a second embodiment of the present invention, which differs from the first embodiment in that the minority carrier injection region 9 is formed away from the drain region 8, a buffer layer region 13 is not present, and that the second gate electrode 53 is extended to the drain layer side in order to form a field plate.
This embodiment makes it possible to prevent the occurrence of a negative resistance characteristic in the output characteristics, which easily occurs in the first embodiment. This matter can be explained in the following way.
In the first embodiment, shown in Figure 1, an injection from the minority carrier region 9 occurs only after the electron current has reached a certain value. In other words, minority carrier inject ion occurs for the first time when a voltage drop directly below the minority carrier injection region 9, which is caused by the electron current flowing when the first gate is turned on, grows to a value that biases the p-n junction between the minority carrier injection region 9 and the n-buffer layer 13 in the forward direction. Once injection has occurred, the current caused by conductivity modulation becomes predominant and as a result, the forward bias value in the p-h junction between the minority carrier injection region 9 and the n-buffer region 13 increases. This increase then serves to further increase the injection, which causes the resistance to decrease sharply, thus generating the negative resistance that can be seen in Figure 5 as shown by the solid line for the IV characteristic.
In the embodiment shown in Figure 4, because the minority carrier injection region 9 is placed away from the drain region 8, the voltage drop in the n layer 2 directly below the minority carrier injection region is large enough (even if the current is small) to facilitate the injection. Thus an output characteristic with less negative resistance can be obtained. In addition, if a punch-through is caused by the element junction structure, the figure 1 embodiment must have an n-buffer layer 13; however, the embodiment of figure 4 can eliminate the need for a buffer region even under such circumstances because the remaining withstand voltage can be retained by the n layer 2 present between the minority carrier injection region 9 and the drain region 8 even if the depletion layer extending from the p-type base region 3 or the p- substrate reaches the minority carrier injection region 9. The presence of a buffer region 13 with a low resistance tends to make the voltage drop caused by the electron current smaller while facilitating the negative resistance. However, the figure 4 embodiment can prevent such a trend. Furthermore, the construction which extends the second gate electrode 53 toward the drain layer side, thereby forming a field plate, causes the depletion layer to grow more easily from the minority carrier injection region 9, and lowers the intensity of the electric field. Incidentally, the embodiment shown in Figure 4 also has a field plate, which has been formed to extend laterally from both sides of the collector electrode 62 of the drain region 8.
The third embodiment of the present invention, which is shown in Figure 6, is an example of a minority carrier controlled construction applied to a lateral MCT. That Is, the area around the emitter electrode 61 is constructed in the same way as the area around the lateral MCT shown in Figure 3; however, the construction is similar to that shown in Figure 4, in that the p+ drain region 7 is absent, a collector electrode contacts the nt drain region 8, the minority carrier injection region 9 is formed between the drain region 8 and the p-type base region 3, and the n source region 11 is formed on the surface layer of the minority carrier injection region 9. It is also possible in this case to reduce the on-voltage in a turned-on state and increase the turn-off speed by controlling the injection of the minority carrier, as has already been done in the case of an IGBT. Furthermore in this embodiment, the deficiencies inherent in the MCT (i.e. that the depletion layer cannot be extended because carriers are present in large numbers, and that the area of the safe operation region is reduced during a turn-off operation) can be corrected by stopping minority carrier injection immediately before the turn-off operation.
Figure 8 shows a fourth embodiment of the present invention. The difference between this embodiment and the first embodiment is that in this case a p-type punch-through region 91 is formed surrounding the drain region 8, and is linked to the minority carrier injection region 9. Because the drain region 8 is completely surrounded by the p-region in this embodiment, minority carrier injection is possible even in a low-current region, which completely prevents the negative resistance as indicated by the broken lines in
Figure 5. Furthermore, minority carrier injection can be stopped during the turn-off operation of the second gate as in the first embodiment by the punch-through effect of the punch-through region 91 sufficiently thin and keep the impurity concentration low. The following section explains this operation.
When the second gate is turned on, only a very slight potential difference is generated between the n source region 11 and the minority carrier injection region 9, which is connected by the short circuit electrode 63, and between the punch-through region 91 and the drain region 8 because the n source region 11 is shorted with the drain region 8 by an inversion layer directly below the second gate electrode 53. Therefore, minority carrier injection can occur via the punch-through region 91 in a low current region; however, because the punch-through region 91 has a low concentration and a small injection coefficient, a forward voltage across the n-buffer region 13 and the minority carrier injection region 9 rises as the current Increases, slowly making the inject ion from the minority carrier injection region 9 predominant. Since this arrangement continuously increases the injection via the small current region, no negative resistance can be generated.
On the other hand, when the second gate is turned off, a current that has been flowing through the inversion layer directly below the second gate electrode 53 is interrupted, and the reverse direction voltage at a junction between the punch-through region 91 and the drain region 8 rises. When the depletion layer formed by this reverse direction voltage gets as far as the n-buffer region 13, or in other words, punch-through occurs between the n-buffer region 13 and the drain region 8, the electrons in the vicinity of the n-buffer region 13 reach the drain region 8 without being recombined with holes in the punch-through region 91. This means that injection of the holes h ceases because no holes h are present in the punch-through region 91. In addition, since the minority carrier injection region 9 enters a floating condition because the punch-through region 91 has been depleted, the injection therefrom also stops. Therefore, by designing the thickness and impurity concentration of the punch-through region 91 so as to punch-through at 2 V to 3 V, the negative resistance which is generated easily in the first embodiment can be prevented, and a MOSFET operation mode can be created as in the first embodiment, thus making high-speed switching possible.
Figure 9 shows a fifth embodiment of the present invention.
The difference between this embodiment and the first embodiment is that the positions of the drain region 8 and the minority carrier injection region 9 are reversed. Because in this embodiment the drain region 8 is placed on a side closer to the first gate, the majority carrier can be efficiently pulled off the n layer 2 when the region 91 is punched-through, making high-speed switching possible.
In addition, the constructional arrangements of the fourth and fifth embodiments can also be applied to the MCT as in the case of the third embodiment.
The method causing conductivity modulation by utilising the minority carrier injection region according to the present invention can be applied not only to the lateral devices, but also to the vertical devices. Figure 7 shows a semiconductor element that has the same functions as the vertical IGBT realized in such a manner.
In other words, the semiconductor is constructed so that the p-type base region 3, the n source region 4 and the first gate electrode 51 are disposed on one side of the n- substrate 2, while the emitter electrode 61 contacts the p-type base region 3 and the n+ source region 4, whereas on the other side the n+ drain region 8 contacting the collector electrode 62, the p-region 9 which has a minority carrier injecting action, the n+ source region 11 on the surface layer thereof, the short-circuit electrode 63, and the second gate electrode 53 are formed, thus allowing the same operations as in the element seen in Figure 4 to be performed. Vertical configuration for other embodiments is also possible as well as this embodiment.
Although the above embodiments have been explained with reference to the first gate electrode applying MOS gate type with a majority carrier injection construction it also may be applied to a junction-gate type having a majority carrier injection construction such as is used in a static induction-type transistor.
Bipolar-type semiconductors such as IGBTs require a long time for a turn-off operation because minority carrier injection into a semiconductor region does not stop even after the turn-off operation is completed. Given this fact, the present invention has installed an injection region for the minority carrier in the semiconductor device which can either be connected to or separated from a drain region, which contacts a main electrode via a separate gate, wherein the minority carrier is injected from the injection region connected to the drain region by increasing the voltage applied to a sub gate during an 'on' operation with a voltage higher than a threshold value, while minority carrier inject ion is stopped by separating the Inject ion region from the drain region by decreasing the voltage applied to a sub gate to a value lower than the threshold value, when the turn-off operation is started. As a result, while retaining the advantage of reducing the on-voltage as a result of the on-state conductivity modulation In the semiconductor region, the carrier that needs to be swept off in order to expand a depletion layer in the semiconductor region during a turn-off operation is reduced, substantially reducing the turn-off time and making it shorter than that in the conventional case, thereby minimising the turn-off loss.
The present invention can be widely applied in various patterns to semiconductor devices with a conductivity modulating action such as static inductive thyristors, besides the IGBTs and
MCTs as already described. The present invention therefore serves to reduce switching loss, raise the power conversion efficiency, shorten the turn-off time, and expand the applicable frequency range, especially when the invention is applied to semiconductor devices with a high withstand voltage and a large current capacity.
Claims (9)
1. A semiconductor device, in which a low-resistance region of the first conductivity type with one of the main electrodes formed on the surface of a high-resistance region of the first conductivity type and a minority carrier injection region of the second conductivity type are formed, a source region of the first conductivity type is formed on the surface layer of the minority carrier injection region, a gate electrode is disposed via a gate insulation film on the minority carrier injection region at a part sandwiched by an edge close to said main electrode and the source region, and an electrode is disposed to short-circuit the source region and the minority carrier injection region on the surface.
2. A semiconductor device as claimed in Claim 1, wherein the minority carrier injection region is formed adjoining the low-resistance region of the first conduction type.
3. A semiconductor device as claimed in Claim 1, wherein the minority carrier injection region is formed some distance from the low-resistance region of the first conductivity type.
4. A semiconductor device as claimed in any of Claims 1 to 3, wherein the base regions of second conductivity type are formed individually on the surface layer of a high-resistance semiconductor layer of the first conductivity type, emitter regions of the first conductivity type are formed on the surface layer of the base regions, another gate electrode is disposed via a gate insulation film on the surface layer of the base region at a part sandwiched by the emitter region and said high-resistance layer, and the other main electrode contacts the surfaces of the base region and the emitter region.
5. A semiconductor device as claimed in any of Claims 1 to 4, wherein a punch-through region of the second conductivity type with a depth greater than that of the low-resistance factor region of first conductivity type, but smaller than that of the minority carrier injection region, is formed beneath the low-resistance region of the first conduction type.
6. A semiconductor device as claimed in any of Claims 1 to 3, wherein the base regions of the second conductivity type are formed individually on the surface layer of the high-resistance factor semiconductor layer of the first conductivity type, base regions of the first conduction type are formed on the surface layer of the base regions, emitter regions of the second conductivity type are formed on the surface layers of the base regions of the first conductivity type, another gate electrode is disposed via the gate insulation film on the surface layers of the base regions of the first and second conductivity types at a part sandwiched by the high-resistance semiconductor layer of the first conductivity type and the emitter regions, and the other main electrode contacts the surfaces of the base region of the first conductivity type and the emitter region.
7. A semiconductor device as claimed in Claims 4 to 6, wherein the minority carrier injection region and the base region are formed on the same main surface of semiconductor wafer.
8. A semiconductor device as claimed in Claims 4 to 6, wherein the minority carrier Injection region are formed on one of the main surface of the semiconductor wafer and the base region are formed on the other main surface of semiconductor wafer.
9. A semiconductor device substantially as described herein with reference to Figures 1, 4, 6, 7, 8 or 9 of the accompanying drawings.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9402639A GB2286484A (en) | 1994-02-11 | 1994-02-11 | Conductivity modulated semiconductor device |
| JP9084494A JPH07226511A (en) | 1994-02-11 | 1994-04-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9402639A GB2286484A (en) | 1994-02-11 | 1994-02-11 | Conductivity modulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9402639D0 GB9402639D0 (en) | 1994-04-06 |
| GB2286484A true GB2286484A (en) | 1995-08-16 |
Family
ID=10750229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9402639A Withdrawn GB2286484A (en) | 1994-02-11 | 1994-02-11 | Conductivity modulated semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH07226511A (en) |
| GB (1) | GB2286484A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19750827A1 (en) * | 1997-11-17 | 1999-05-20 | Asea Brown Boveri | Power semiconductor component with anode and cathode |
| DE10334797B3 (en) * | 2003-07-30 | 2005-05-25 | Infineon Technologies Ag | Semiconductor component with field stop layer with p or n channel transistor has transistor gate arranged so potential exists between gate, bounding part of spatial charging zone area to cause a current to flow through field stop layer |
| DE102005031139B4 (en) * | 2004-08-27 | 2009-09-03 | Mitsubishi Denki K.K. | Semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0520909D0 (en) * | 2005-10-14 | 2005-11-23 | Eco Semiconductors Ltd | Power semiconductor devices |
| JP5055813B2 (en) * | 2006-04-10 | 2012-10-24 | 富士電機株式会社 | SOI lateral semiconductor device |
| JP4632068B2 (en) * | 2008-05-30 | 2011-02-16 | 三菱電機株式会社 | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2173037A (en) * | 1985-03-29 | 1986-10-01 | Philips Electronic Associated | Semiconductor devices employing conductivity modulation |
| US5198688A (en) * | 1989-03-06 | 1993-03-30 | Fuji Electric Co., Ltd. | Semiconductor device provided with a conductivity modulation MISFET |
| US5245202A (en) * | 1991-05-31 | 1993-09-14 | Fuji Electric Co., Ltd. | Conductivity modulation type misfet and a control circuit thereof |
| EP0559910A1 (en) * | 1991-10-01 | 1993-09-15 | Nippondenso Co., Ltd. | Insulated-gate bipolar transistor |
-
1994
- 1994-02-11 GB GB9402639A patent/GB2286484A/en not_active Withdrawn
- 1994-04-28 JP JP9084494A patent/JPH07226511A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2173037A (en) * | 1985-03-29 | 1986-10-01 | Philips Electronic Associated | Semiconductor devices employing conductivity modulation |
| US5198688A (en) * | 1989-03-06 | 1993-03-30 | Fuji Electric Co., Ltd. | Semiconductor device provided with a conductivity modulation MISFET |
| US5245202A (en) * | 1991-05-31 | 1993-09-14 | Fuji Electric Co., Ltd. | Conductivity modulation type misfet and a control circuit thereof |
| EP0559910A1 (en) * | 1991-10-01 | 1993-09-15 | Nippondenso Co., Ltd. | Insulated-gate bipolar transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19750827A1 (en) * | 1997-11-17 | 1999-05-20 | Asea Brown Boveri | Power semiconductor component with anode and cathode |
| DE10334797B3 (en) * | 2003-07-30 | 2005-05-25 | Infineon Technologies Ag | Semiconductor component with field stop layer with p or n channel transistor has transistor gate arranged so potential exists between gate, bounding part of spatial charging zone area to cause a current to flow through field stop layer |
| DE102005031139B4 (en) * | 2004-08-27 | 2009-09-03 | Mitsubishi Denki K.K. | Semiconductor device |
| US7723802B2 (en) | 2004-08-27 | 2010-05-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07226511A (en) | 1995-08-22 |
| GB9402639D0 (en) | 1994-04-06 |
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| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |