JP2001332728A - Igbt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IGBT capable of holding a low on voltage without increasing a switching loss in a non-punch through type IGBT having a trench gate. SOLUTION: In the non-punch through type IGBT having the trench gate, an impurity concentration of a collector layer 9 is raised, hence an excess carrier at a collector side is increased as compared with a drift layer 7, a voltage drop in this part is held low, while the excess carrier at an emitter side of the layer 7 is held low, a loss at a switching time is thereby reduced and hence a low on-voltage and a low switching loss are resultantly realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-punch-through IGBT (insulated-gate bipolar transistor), and more particularly to a non-punch-through IGBT having a trench gate.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view showing a cell structure of a conventionally known punch-through IGBT having a trench gate. 10, reference numeral 1 denotes an emitter electrode made of an Al-Si alloy or the like, 2 denotes an oxide film as an interlayer insulating film for insulating the emitter electrode from the gate electrode, and 3 denotes a trench formed via a gate oxide film in the trench. a gate electrode made of polysilicon, the gate oxide film 4, 5a, 5b are n ⁺ -type emitter diffusion layer of, channel diffusion layer of the p-type 6
7 is an n ⁻ type drift layer, 8 is an n ⁺ type buffer layer, 9
Denotes a p-type collector layer, and 10 denotes a collector electrode.

In a punch-through IGBT having a trench gate shown in FIG. 10, a lifetime killer mainly by electron beam irradiation or the like has been conventionally introduced in order to increase the switching speed. FIG. 11 shows an excess carrier distribution in a cross section taken along line AA ′ of FIG. As is clear from the figure, it is known that the excess carrier distribution in the ON state (substantially the same number of electrons and holes) has a minimum value near the center of the drift layer 7.

Further, in a punch-through IGBT having a trench gate, the so-called IEGT in which the accumulation of excess carriers in the drift layer 7 is increased by preventing the discharge of minority carriers near the surface in order to lower the ON voltage. (Injection-Enhanced Gate Bipolar Tran
sistor, see JP-A-5-243561).

[0005]

However, an increase in accumulated carriers near the surface causes an increase in gate capacitance,
This causes problems such as an increase in delay time at turn-on and turn-off and an increase in drive power, that is, an increase in switching loss.

On the other hand, a non-punch-through IGBT having a trench gate as shown in FIG. 12 has attracted attention in contrast to a punch-through IGBT (see: T. Laskae).
t.al, "1200V-Trench-IGBT study with Square Shor
t Circuit SOA ", proc.ISPSD98, pp.433-436, 1998).

The non-punch-through type IGBT has a structure in which the thickness of the drift layer 7 is optimally designed so that the depletion layer does not extend from the collector layer 9. The low manufacturing cost due to the use of a wafer is one of its features. In the case of punch-through type turn-off, the drift layer 7 is used.
It is necessary to perform lifetime control in order to eliminate a large amount of carriers in the above.However, in the non-punch-through type, it is possible to turn off only by discharging carriers by suppressing the injection of holes from the collector side itself. Generally, the lifetime control as used in the punch-through type is not performed, and therefore, the minority carrier lifetime in the drift layer 7 becomes as long as 1 μsec or more. There is a limit to improving the switching speed and, consequently, reducing the switching loss.

Accordingly, the present invention has been made in view of the above points, and a non-punch-through IGBT has been developed.
IGBT that can improve switching speed and reduce switching loss without increasing on-voltage
The purpose is to provide.

[0009]

An IGBT according to the present invention
Is characterized in that in a non-punch-through IGBT, the distribution of accumulated carriers in the drift layer in the on state is maximized in the collector-side region rather than in the center of the drift layer. If this is the case, the capacitance between the gate and the collector can be reduced, the switching speed can be improved, and the switching loss can be reduced.

Further, the IGBT according to the present invention has a trench gate.

The trench gate IGBT has a large gate area, and the capacitance between the gate and the collector is easily affected by excess carriers on the emitter side. Therefore, by reducing the excess carriers on the emitter side (increased on the collector side), the capacitance between the gate and the collector can be reduced, and this has a great effect on improving the switching speed and reducing the switching loss.

Further, in the IGBT according to the present invention, the distribution of accumulated carriers in the drift layer uniformly decreases from the collector side to the emitter side, and becomes minimum at the emitter end. According to such a configuration, the distribution of accumulated carriers is not minimized in the middle of the drift layer, and therefore, the distribution of accumulated carriers on the emitter side can be efficiently minimized.

Further, in the IGBT according to the present invention, the collector layer has an impurity peak concentration of 5 × 10 ¹⁶ cm ^−3.
According to such a configuration, the on-state voltage can be significantly reduced as compared with, for example, a planar gate IGBT. In this case, the lifetime of the minority carrier in the drift layer may be 1 μsec or more. Further, in the IGBT according to the present invention, a channel diffusion layer having an emitter layer and connected to the emitter electrode between the plurality of trench gates, and a floating layer not forming the emitter layer and not connecting to the emitter electrode According to such a configuration, holes under the floating layer are hardly discharged to the emitter electrode and accumulate here, and the carrier concentration distribution of the drift layer is It becomes close to that of the diode, resulting in a low on-voltage.

Further, in the IGBT according to the present invention,
A collector layer is formed using ion implantation;
According to this structure, the collector layer is formed without exceeding the melting point of aluminum Al used for the electrode material of the emitter. And the impurity peak concentration of the collector layer is set to 5 × 10 ¹⁶ c
m ⁻³ or more.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, when describing embodiments of the present invention, first, the basic configuration and principle of the present invention will be described. According to the present invention, for example, in a non-punch-through type IGBT having a trench gate (hereinafter also referred to as a non-punch-through type trench gate IGBT), the excess carrier concentration on the collector side of the drift layer is increased by increasing the accumulated carrier concentration of the collector layer. While maintaining a low voltage drop in this area, reducing the excess carrier concentration on the emitter side of the drift layer,
Switching loss is reduced,
As a result, low on-voltage (conventional non-punch-through IGB)
T without increasing the on-state voltage) and low switching loss.

First, characteristics of the non-punch-through type trench gate IGBT will be described with reference to FIGS. FIG. 1 shows a non-punch-through type trench gate IGB having the same on-voltage and different collector layer impurity concentrations.
12 shows an excess carrier distribution of T (BB ′ section in FIG. 12) and a voltage drop in the drift layer 7.

As apparent from FIG. 1, as the impurity concentration of the collector increases, the excess carrier concentration on the emitter side decreases, while the excess carrier concentration on the collector side increases. Further, when the collector layer 9 has a high concentration, the change rate of the voltage drop on the emitter side is large, but the change rate of the voltage drop on the collector side is small. In contrast, when the collector layer has a low concentration, the rate of change of the voltage drop on the emitter side is small, and the rate of change of the voltage drop on the collector side is large.

These facts indicate that in order to keep the on-voltage low, a certain amount of the accumulated carriers in the drift layer 7 is required, but if the total number of the accumulated carriers is almost the same, the distribution Is not affected by the bias of
This shows that substantially the same ON voltage can be realized whether the accumulated carriers are concentrated on the emitter side or the collector side.

Furthermore, I having these same on-voltages
FIG. 2 shows the relationship between the impurity concentration of the collector layer 9 and the delay time at turn-on (the time from when the ON signal is applied to the gate until the collector current starts to increase) in the GBT.

As is apparent from FIG. 2, this delay time becomes shorter as the impurity concentration of the collector layer 9 becomes higher, that is, as the excess carriers on the emitter side decrease. Such a relationship is the same at the time of turn-off. This is because, compared to the planar gate, the trench gate IG
Since BT has a large gate area, it is greatly affected by excess carriers on the emitter side.

That is, in an element having a distribution in which excess carriers on the emitter side are increased in the ON state, the gate electrode 3 / gate oxide film 4 / drift layer 7
The capacity between the gate and the collector composed of the collector / collector electrode 10 increases, and a larger amount of charge is required to charge and discharge this capacity at the time of switching. As a result, the delay time becomes longer or the gate becomes larger. A current is required, and the gate drive power (switching loss) increases.

On the other hand, in an element having a distribution in which the excess carriers on the collector layer 9 side are increased, the drift layer having the capacitance of the gate electrode 3 / gate oxide film 4 / drift layer 7 / collector electrode 10 is used. The distribution capacitance of the portion is smaller than that of the element having the excess carrier distribution biased to the emitter side, so that the capacitance between the gate and the collector is reduced, and conversely, the switching delay time is shortened, and the switching delay is shortened. Loss can be reduced.

As described above, the excess carrier distribution in which the collector side is high and the emitter side is low cannot be obtained in the conventional punch-through IGBT shown in FIG. This is because, in the punch-through IGBT, the excess carrier distribution in the drift layer 7 is controlled by controlling the concentration and thickness of the n-buffer layer 8 provided in the collector layer 9 and controlling the lifetime of minority carriers in the drift layer 7. This is because it is determined based on the results performed in combination. With the current technology, it is not practical to form the n-buffer layer 8 that can obtain an appropriate ON voltage without performing lifetime control. Therefore, as shown in FIG. 9, the excess carrier distribution of the punch-through type trench IGBT has a minimum value at the center of the drift layer 7, and on-voltage is further reduced. Then, the excess carrier distribution on the emitter side also increases, and the above-described problem associated with the increase in the capacitance between the gate and the collector occurs.

On the other hand, a non-punch-through type IGB
T can be obtained by changing the distribution of excess carriers mainly by changing the impurity concentration of the collector layer 9, and basically, lifetime control is not performed. Therefore, it is possible to realize a distribution that does not have the minimum value of the excess carrier distribution at the center of the drift layer 7. Therefore, in the present invention, the distribution of accumulated carriers in the drift layer in the ON state is maximized in the collector side region from the center of the drift layer, the accumulated carrier concentration at the emitter end of the drift layer is minimized, and the collector side is shifted from the collector side to the emitter side. To have a distribution that decreases uniformly toward.

In the non-punch-through IGBT, "breaking" is apt to occur during the production due to the thinning of the wafer. Therefore, the thickness of the non-punch-through IGBT is about 180 μm in the case of the withstand voltage class of 1200 V, for example. In the process, after all the surface structures have been formed (in a state where the emitter electrode and the protective film on the surface have been formed), the collector layer 9 is formed.
Is formed. In this state, since the emitter electrode 1 has already been formed, processing cannot be performed at a high temperature such as 1000 ° C. which exceeds the melting point of the electrode material of the emitter. Therefore, since the non-punch-through type IGBT generally uses Al for the emitter electrode 1, the maximum process temperature is 4 ° C.
It is appropriate that the temperature be 50 ° C. or lower.

As described above, in the embodiment of the present invention, the n-buffer layer 9 formed by the punch-through IGBT is used.
In the non-punch-through IGBT in which the concentration, thickness control, and lifetime control of the non-punch-through type IGBT are unnecessary, and thus the distribution of the accumulated carriers in the drift layer can be easily biased toward the collector layer side, the accumulated carriers are biased as described above. By improving the switching speed and the switching loss without increasing the on-voltage without increasing the on-voltage, the gate area is further increased, and the capacitance between the gate and the collector is easily affected by excess carriers on the emitter side. Therefore, by reducing excess carriers on the emitter side (increased on the collector side),
By providing a trench gate structure in which the capacitance between collectors can be significantly reduced, it is an object to obtain an IGBT capable of improving the switching speed and lowering the switching loss.

Hereinafter, specific embodiments will be described. FIG. 3 shows a basic cell structure of a non-punch-through type trench gate IGBT having a withstand voltage class of 600 V using the present invention and a hole distribution in an on state (collector current density = 200 A / cm ² ) predicted by simulation. . In FIG. 3, the same parts as those in the conventional example shown in FIG.

The trench gate IGBT is formed by using an FZ wafer (silicon substrate manufactured by a floating zoning method) having a specific resistance of 30 ohm.
An example of a trench gate IGBT having a thickness of 5 μm, a trench depth of 5 μm, and a junction depth of the channel diffusion layer of 3 μm is taken. After forming the structure of the emitter electrode 1 to the channel diffusion layer 6 on the drift layer 7, the back surface of the wafer is
The collector layer 9 is formed by ion implantation, and finally the collector electrode 10 is formed. The impurity concentration in the drift layer 7 increases linearly from the channel diffusion layer 6 side to the collector layer 9, and the impurity concentration on the collector side in the drift layer 7 is approximately 2 × 10 ^{16 to} 5 × 10 ¹⁶ cm ^−3. The impurity concentration on the emitter side is approximately 3 × 10 ^{15 to} 7 × 10 ¹⁵ cm ⁻³ . The impurity peak concentration of the collector layer 9 is about 1 × 10
¹⁷ cm ^-3 .

FIG. 4 shows a measurement of the device at room temperature.
This shows output characteristics. As shown in FIG.
Pressure is collector current density 200A / cm ^TwoIn 1.
It is kept very low at 5V.

FIG. 5 shows this element and, for comparison,
By comparing the turn-on waveforms measured under the same gate conditions for devices that achieved the same on-voltage by lowering the impurity concentration of the collector and increasing the concentration of excess carriers on the emitter side by the IE effect (carrier injection enhancement effect) in the same manner, I have. As is clear from these results, the device of the present invention has a short turn-on delay time and a small turn-on loss despite the same on-voltage.

FIG. 6 shows a withstand voltage class of 600 V.
3 shows the relationship between the collector layer impurity concentration on the back surface and the ON voltage in the non-punch-through type trench gate IGBT. As can be understood from FIG. 6, when the impurity concentration of the collector layer 9 is 5 × 10 ¹⁶ cm ⁻³ or less, the difference from the planar gate IGBT is not so much obtained, and the superior point of the trench gate is lost. Therefore, it is desirable that the impurity concentration of the collector layer on the back surface of the non-punch-through type trench gate IGBT is 5 × 10 ¹⁶ cm ⁻³ or more.
In this case, the life time of the minority carrier in the drift layer 7 is 1 μsec or more.

FIG. 7 shows the relationship between the temperature of the heat treatment after ion implantation and the impurity peak concentration of the collector layer 9 when the collector layer 9 is formed. Heat treatment time is 3
0 minutes. As can be understood from FIG.
It can be seen that an impurity concentration of ¹⁶ cm ^-3 or more can be obtained by performing a heat treatment at 350 ° C. or more. Furthermore, the surface has Al
Is used as the emitter electrode 1, so that the upper limit of the heat treatment is suitably about 450 ° C. That is, the collector layer is formed by ion implantation, and
It is desirable to form by heat treatment of 50 ° C. or less.

FIG. 8 is a sectional view taken in a direction crossing a trench gate in a different embodiment. 8 differs from FIG. 3 in that emitter diffusion layers 5a and 5b opposed to the trench of the trench gate via gate oxide film 4.
This is the point that a floating layer 6a in which no is formed is provided.
The floating layer 6a is a layer formed simultaneously with the channel diffusion layer 6, but is in a floating state without being connected to the emitter electrode 1. In this embodiment, holes under the floating layer 6a are hardly discharged to the emitter electrode 1 and accumulate there, and the carrier concentration distribution of the drift layer becomes close to that of the diode, resulting in a low on-state voltage. In addition, since the impurity concentration of the collector layer 9 is increased and the distribution of accumulated carriers in the drift layer 7 in the on state is maximum on the collector side, the turn-on delay time is short, and the turn-on loss can be reduced.

FIG. 9 is a cross-sectional view taken in a direction crossing a trench gate in still another embodiment. FIG.
8 is different from FIG. 8 in that the emitter diffusion layers 5a, 5b
That is, a trench portion having no trench is provided.

[0035]

As described above in detail, according to the present invention, in the non-punch-through type IGBT, the distribution of accumulated carriers in the drift layer in the ON state is maximized in the collector side region with respect to the center of the drift layer. By doing so, there is an effect that the ON voltage can be suppressed low and low-loss switching can be simultaneously realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an excess carrier distribution and a voltage drop in an ON state of a non-punch through type trench IGBT used for describing the present invention.

FIG. 2 is an explanatory diagram of a relationship between a turn-on delay time and a collector layer impurity concentration used in the description of the present invention.

FIG. 3 is an explanatory diagram showing a basic cell structure of a non-punch-through type trench gate IGBT having a withstand voltage class of 600 V according to the present invention and a hole distribution in an on state (collector current density = 200 A / cm ² ) predicted by simulation. .

FIG. 4 is an output characteristic diagram of the element shown in FIG.

FIG. 5 is an explanatory diagram comparing a turn-on waveform of the device shown in FIG. 3 with a conventional device.

FIG. 6 is an explanatory diagram of a relationship between an impurity concentration of a collector layer and an ON voltage.

FIG. 7 is an explanatory diagram of a relationship between a temperature of a heat treatment after ion implantation and an impurity peak concentration of a collector layer.

FIG. 8 is a cross-sectional view taken in a direction crossing a trench gate according to a different embodiment of the present invention.

FIG. 9 is a cross-sectional view taken in a direction crossing a trench gate according to still another embodiment of the present invention.

FIG. 10 is a sectional structural view of an IGBT according to a conventional example.

FIG. 11 is an explanatory diagram of an excess carrier distribution in an ON state of an IGBT according to a conventional example.

FIG. 12 shows a non-punch-through type trench I according to a conventional example.
FIG. 2 is a sectional structural view of a GBT.

[Explanation of symbols]

1 emitter electrode, 2 oxide film, 3 gate electrode, 4
Gate oxide film, 5a, 5b Emitter diffusion layer, 6 channel diffusion layer, 6a floating layer, 7 drift layer, 9 collector layer, 10 collector electrode.

Claims (7)

[Claims] 1. A non-punch-through IGBT,
The distribution of accumulated carriers in the drift layer in the ON state is
An IGBT characterized in that it is maximum in a collector-side region rather than a center portion of a drift layer. 2. The IGBT according to claim 1, wherein said non-punch-through IGBT has a trench gate. 3. The IGB according to claim 1, wherein
At T, the accumulated carrier distribution in the drift layer is
An IGBT characterized by a uniform decrease from the collector side to the emitter side and a minimum at the emitter end. 4. The IGBT according to claim 1, wherein the collector layer has an impurity peak concentration of 5 × 10 ¹⁶ cm ⁻³ or more.
T. 5. The IGBT according to claim 4, wherein the minority carrier has a lifetime of 1 μs in the drift layer.
ecBT or more. 6. The IGBT according to claim 2, wherein an emitter layer is provided between the plurality of trench gates, the channel diffusion layer is connected to the emitter electrode, the emitter layer is not formed, and the emitter electrode is formed. An IGBT having a floating layer not connected to the IGBT. 7. The IGBT according to claim 1, wherein the collector layer is formed by ion implantation and formed by a heat treatment at 350 ° C. or more and 450 ° C. or less. IGBT that features.